415 results about "Floating point" patented technology

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The invention discloses a high-density NAND storage medium self-adaptive repairing method which comprises the following steps: a main control chip separates a target feature vector representing the real aging trend of a storage unit from original read data containing random physical noise; the main control chip deduces the target feature vector by using a full-integer recursive prediction model to obtain a health state prediction result of the storage unit in a future preset time period; wherein the health state prediction result comprises an optimal read reference voltage offset and an estimated bit error rate growth curve; and the main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit in the data writing stage according to the health state prediction result. By means of the mode, the problems of firmware assembly line blocking and performance jitter caused by floating point operation and huge model parameter loading can be solved under the limited hardware environment that the main control chip only supports integer operation and on-chip cache is extremely small.

The invention discloses a method for applying linear programming to CDN (Content Delivery Network) scheduling, which relates to the technical field of content delivery networks and comprises the steps of data preparation, strategy layer version smooth configuration, macroscopic layer and microscopic layer linear solution and online execution. Basic data are collected, cleaned and repaired, and a version change rule is set; the macroscopic layer constructs a linear programming model, and the cross-provincial bearing quota is solved with the aim of minimizing the cross-provincial cost; the micro layer takes the quota as a boundary and generates domain name class-node weight vectors in parallel; and adapting a routing request online through weighted rendezvous hashing and request features. According to the method, a dynamic cost matrix and a weight granularity control technology are integrated, the engineering problem of linear programming is solved, second-level response, approximate global optimal scheduling and accurate execution of floating-point-level weight are realized, memory overhead is reduced, smooth updating of a strategy and system stability are guaranteed, and CDN service quality and operation efficiency are improved.

The invention provides a kernel function trajectory-based deep learning inference service performance analysis method, which comprises the following steps of: based on service indexes and hardware theoretical computing power acquired from a production cluster, defining floating point operation times per request (FPR) index to quantify service resource efficiency, and identifying high FPR hotspot services; positioning a reasoning iteration candidate boundary based on a GPU kernel function trajectory, verifying iteration integrity through fingerprint matching and chi-square test, and calculating a second reasoning iteration number IIPS and a model reasoning efficiency MIE; aiming at calculation-intensive operators on the key path, combining a dynamic Roofline model to estimate an operator theoretical performance upper limit, and based on actual execution time, calculating efficiency and a BottleScore index to identify a key bottleneck operator; and outputting targeted optimization suggestions according to analysis results of service efficiency analysis, model efficiency analysis and operator efficiency analysis. According to the method, the inference behavior pattern can be automatically identified from massive kernel trajectories, and the efficiency loss of each level is quantified.

The SRT operational circuit comprises an input module, a floating point conversion module, a calculation module and an output module, the input module is configured to output an initial operand, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; if the calculation module is configured to perform division operation or root extraction operation by adopting the first operand based on the SRT algorithm, the output module is configured to perform mantissa rounding on a division result or a root extraction result after the calculation of the calculation module is completed and output a floating point result, so that the operation accuracy of an integer in the circuit is improved, and the universality of the circuit is improved.

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

The invention belongs to the field of storage, and discloses a high-energy-efficiency mixed-precision charge domain in-storage computing architecture and a working method thereof. Comprising a single-slope analog-to-digital converter, a sparsity perception input alignment module, a multi-bit input accumulation module, a controller and an accumulation module, wherein the single-slope analog-to-digital converter consists of an index calculation array, a mantissa calculation array, a shared ramp voltage generator and a bidirectional counter. According to the invention, serial input binary coding based on capacitor voltage is suitable for floating point and integer multiply-accumulate operation with flexible bit width; according to the invention, a shared single-slope analog-to-digital converter (SS-ADC) is introduced to realize maximum index search and index difference calculation; according to the method, a sparsity perception calculation scheme is provided, low-importance input-weight pairs are filtered out through an adjustable threshold value, and invalid power consumption is reduced; according to the method, a multi-bit input accumulation method is further combined, and an ADC redundancy optimization quantization and normalization process is utilized, so that the overall energy efficiency is improved.

The invention discloses an ambiguity fixing method, device and equipment, and the method comprises the steps: obtaining an ambiguity floating point solution vector and a covariance matrix with a corresponding ambiguity mode under a current epoch based on Kalman filtering, and the ambiguity floating point solution vector comprises a plurality of original ambiguity; according to the covariance matrix, determining an arrangement sequence of the plurality of original ambiguity; according to the ambiguity mode and the arrangement sequence, multiple target ambiguity are selected from the multiple original ambiguity for two-stage fixation, and if two-stage fixation succeeds, fixed values of the target ambiguity after fixation are output; if the two-stage fixation fails, outputting an unfixed floating point value of the original ambiguity, and recording that the current epoch fixation fails; and repeating the above steps for the next epoch, and when the number of continuous fixed failed epochs is equal to a preset number, initializing parameters of Kalman filtering, and then repeating the above steps for the next epoch. According to the method, the calculation complexity and the processing delay can be reduced, and the adaptive capacity in a multi-frequency environment is enhanced.

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

The invention relates to an SP application optimization method and device based on a multi-core NUMA architecture. The method comprises the following steps of: in a compiling stage, performing compiling optimization based on a multi-core NUMA (Non Uniform Memory Access) architecture, and performing memory management by adopting a memory allocator perceived by the NUMA; in the initialization stage, an MPI process is bound to a specific NUMA node, an OpenMP thread in the MPI process is bound to a physical core of the node, and a memory area in charge of the MPI process is initialized in parallel through the thread so as to achieve data locality; in the execution stage, a NEON instruction is adopted to carry out vectorization optimization on the step of calculating the residual vector local sum. By adopting the method, the memory access delay across the NUMA nodes can be remarkably reduced through multi-level collaborative optimization, and the instruction execution efficiency and the floating point operation throughput rate are improved, so that the execution performance and the parallel expandability of an SP reference program on a multi-core NUMA architecture server are effectively improved.

The embodiment of the invention relates to a data processing method, a computing unit, electronic equipment, a storage medium and a program product. The method is executed by a calculation unit and comprises the steps that first data to be processed are obtained, and the first data correspond to a weight matrix; analyzing the first data into a plurality of data segments, the plurality of data segments including a plurality of first data segments and a second data segment, the plurality of first data segments corresponding to the floating point value of the first precision; based on a preset corresponding relation, multiple basic values corresponding to the multiple first data segments and a scaling factor corresponding to the second data segment are determined, the multiple basic values correspond to floating point values of second precision, the second precision is higher than the first precision, and the product of the multiple basic values and the scaling factor corresponds to multiple weight values in a weight matrix; and performing multiplication calculation of the weight matrix and the input matrix based on the plurality of base values and the scaling factor. In this way, the decoding and calculation efficiency of the data can be effectively improved.

The invention discloses a GPU shader rendering computer implementation method of a finite element result. The method comprises the steps that a static three-dimensional grid is adopted as a rendering geometry; the 32-bit floating point type scalar data corresponding to the vertexes are subjected to lossless coding at a CPU end to obtain four-channel 8-bit RGBA vertex color attributes; during data updating, lightweight vertex color data are only transmitted to the GPU; hardware interpolation is carried out on the encoded color attributes by using a GPU rasterizer; and finally, in the fragment shader, decoding the interpolation result of each pixel to reconstruct a scalar value, and mapping the scalar value into a final color. According to the method, the bottleneck of topological calculation of a CPU end and transmission of massive geometric data to the GPU is avoided, the calculation load is transferred to the GPU in a large scale for parallel processing, the rendering efficiency is remarkably improved, and high-frame-rate dynamic visualization of a finite element result is realized.

The invention discloses a floating point arithmetic unit, a floating point processing device and method, a chip and electronic equipment, and the floating point arithmetic unit comprises a logic processing module which is used for carrying out the logic operation of a to-be-processed operand inputted into the floating point arithmetic unit, and obtaining an operation result; the delay control module is used for controlling the delay between the input logic processing module of the operands to be processed and the input floating point arithmetic unit; and / or controlling the delay between the operation result output by the logic processing module and the operation result output by the floating point operation unit. Therefore, the delay of the floating point operation can be effectively balanced, the operation efficiency is improved, and the overall performance of the floating point operation is improved.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

The invention discloses an airborne Beidou positioning method and device suitable for an extra-high voltage converter station. The method comprises the following steps: acquiring original observation data of a base station and a moving station in an extra-high voltage converter station scene, and preprocessing the original observation data to obtain preprocessed observation values; performing cycle slip detection on a carrier phase in the observation value according to a preset criterion to obtain cycle slip information; constructing a factor graph optimization model according to the preprocessed observation value and the cycle slip information; performing floating point solution on the factor graph optimization model to obtain an ambiguity floating point solution; and carrying out ambiguity fixation on the ambiguity floating point solution to obtain a high-precision ambiguity fixed solution.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

Block decoding in an artificial neural network is provided. An encoded block comprising a plurality of encoded values, each encoded value comprising a mantissa, is read. The encoded block's scaling information, which includes an exponent and a mantissa, is read. Each of the plurality of encoded values is decoded according to the scaling information to produce a plurality of decoded values.

The invention discloses a Softmax operator circuit and method based on a semi-precision floating-point number, and relates to the technical field of circuits, and the method comprises the steps that the circuit comprises an addition module, a multiplication module, a reciprocal module, an index calculation module and a main control unit; the addition module is used for carrying out addition calculation on the semi-precision floating-point number; the multiplication module is used for carrying out multiplication calculation on the semi-precision floating-point number; the reciprocal calculation module is used for performing reciprocal calculation on the semi-precision floating-point number; the index calculation module is used for performing index calculation on the semi-precision floating-point number; and the main control unit is used for synchronizing the state of each module through the corresponding confirmation signal after each module completes the corresponding calculation. Based on modular and parallel design, the precision of the semi-precision floating-point number is still kept on the premise that hardware resources and the area are remarkably saved, redundant operation and resource consumption are greatly reduced, higher numerical accuracy is achieved, and efficient, high-precision and low-power-consumption calculation acceleration can be achieved under the limited hardware condition.

Disclosed herein are various techniques for converting a vector from a high precision floating point format to a microscaling (MX) format. An example of a precision floating point format is the FP32 format described above, however, the initial format may be another type of standard floating point format as well (reference to the FP32 number format hereinafter is merely for exemplary purposes and not intended to be limiting). The techniques for converting to the MX-compliant format are improvements over the standard technique suggested in the MX specification by at least accounting for the amount of data in the mantissa of the original precision floating point format to mitigate the amount of data that is lost during the conversion. Therefore, the benefits of representing multiple data points of a vector in the single MX format representation without sacrificing as much of the data contained in the original high precision format that may occur following the standard technique described in the MX specification (portions of which are described below).

The invention discloses a wide-lane ambiguity fixing method and device, a computer storage medium and a terminal, according to the embodiment of the invention, a high-precision double-difference ionized layer estimation value is obtained through joint calculation based on a multi-baseline ionized layer adjustment value and an ionized layer interpolation value, and the defect that a wide-lane observation equation analysis method is not easy to operate under the conditions of an ionized layer active area and a long baseline is effectively overcome. The delay of the ionized layer is obviously increased; when the difference between the ionosphere adjustment value and the ionosphere interpolation value is smaller than or equal to a preset threshold value, a pseudo observation equation established according to the ionosphere estimation value is fused into a Kalman filtering equation, measurement updating is carried out on a wide-lane ambiguity floating point solution, and under the condition that the efficiency advantage of direct resolving of a wide-lane observation equation analytical method is reserved, the wide-lane ambiguity floating point solution is obtained. The ambiguity floating point solution is constrained through the pseudo observation equation, the influence of the ionosphere on ambiguity fixation is effectively inhibited, and the reliability and resolving efficiency of ambiguity fixation are improved.

An artificial intelligence (AI) calculation circuit is provided. The AI calculation circuit can support various integer and floating-point calculations through the adjustment of circuit configuration. Integer multiplication and floating-point mantissa multiplication share the multiplication unit, integer comparison and floating-point comparison share the same comparison unit, integer addition and floating-point addition share the same addition unit.

The invention discloses an ultrasonic guidance navigation system based on multi-modal detection and a CNB ejection mechanism, and belongs to the technical field of ultrasonic auxiliary diagnosis, multi-modal detection loads a directional bounding box model and a segmentation model when the system is initialized, and the directional bounding box model performs directional detection of a puncture needle on an input frame; in the result extraction stage, puncture needle information is extracted from a directional bounding box model detection result, a focus mask is extracted from a segmentation result, and the focus mask is adjusted to be the same as an input frame in size; when the focus mask is extracted, the validity of a segmentation result is verified, then first effective mask data are extracted from multiple types of segmentation results, the mask data are transmitted to a CPU from a GPU memory, a floating point probability value is converted into an integer binary mask, and puncture needle direction detection and segmentation of multiple types of anatomical structures are achieved. According to the CNB ejection mechanism, a mathematical model of the ejection process is established through an ejection trajectory calculation function, and a reliable mathematical basis is provided for CNB ejection operation diagnosis.

The invention provides a business processing method of a smart factory platform based on a Beidou grid code, and the method comprises the steps: carrying out the multi-stage grid subdivision of a factory physical space through the Beidou grid code, and generating a unique grid code; the grid coding adopts an integer format to represent position information; equipment sensor data, personnel positioning data and business logic data are bound with the grid codes, and a space-time joint index table is constructed; performing real-time deviation correction on the positioning data through a grid neighborhood topological relation and personnel moving speed constraint to generate a high-precision positioning track; and mapping the service logic to the grid codes through a rule engine, and triggering automatic operation according to grid attributes. Traditional floating point latitude and longitude coordinates are replaced by integer coding, data calculation efficiency is optimized through bit operation, cross-level business association and fast path planning are supported, and business response efficiency is improved.

Apparatuses, systems, and techniques to enable efficient use of mixed precision hardware architecture. In at least one embodiment, one or more first precision circuits and one or more second precision circuits are used on portions of data sets.

The invention relates to the technical field of data transmission, and discloses a speed reducer remote monitoring and parameter configuration system, which comprises the following modules: a calculation module used for establishing QUIC protocol connection between a speed reducer terminal and a cloud server to realize communication; the speed reducer terminal collects vibration, temperature and load data, extracts a main frequency amplitude and calculates a comprehensive index of the health state of the equipment; the scheduling module is used for determining the priority of the current data for the cloud server to perform flow scheduling; the reporting module is used for calculating the size of a data aggregation window by the speed reducer terminal in combination with the smooth round-trip time and priority of the QUIC connection; a plurality of time sequence telemetering floating point values collected in the window size are converted into fixed-length binary sequences, and after the fixed-length binary sequences are spliced to form aggregated data blocks, bit compression coding is carried out, and the aggregated data blocks are reported; and the feedback module is used for realizing asynchronous feedback of an instruction execution state after the speed reducer terminal executes the instruction. According to the invention, the real-time performance of data transmission and the reliability of connection are improved.

An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

The embodiment of the application discloses a data format conversion device and method, electronic equipment and computer storage medium, the data format conversion device comprises: a first shift module, which is used for first extended shift of a normalized format number to be converted integer, and obtains a shift integer; the bit number of the shift integer is n times of the bit number of the integer to be converted; n is a positive integer; a second shift module is used for second extended shift of a normalized format number to be converted decimal, and obtains a shift decimal; an addition module is used for adding the shift integer and the shift decimal, and obtains a shift number; a floating point conversion module is used for floating point format conversion of the shift number, and obtains a floating point format number of the shift number; the floating point format number of the shift decimal is a target floating point number.

The application relates to the field of deep learning, and provides a super-resolution reconstruction method, a device and a storage medium. The method comprises the following steps: acquiring a pre-trained floating-point super-resolution model and a calibration data set; based on the calibration data set, performing sorting-based quantization boundary initialization, which comprises the following steps: statistically sorting the weight and activation value data of the floating-point super-resolution model by using the calibration data set, and determining a quantization interval by using a percentile method based on the sorted data distribution; based on the quantization interval, performing bias compensation quantization, which comprises the following steps: calculating a bias compensation mean value, and applying adaptive offset to the weight and activation value data of the floating-point super-resolution model; and using the quantization model optimized by using the calibration data set to perform super-resolution reconstruction on a low-resolution image. According to the technical scheme, the quantization interval is optimized, and the data bias is corrected, so that the reconstruction precision of the super-resolution model after quantization is effectively improved.