2241 results about "Floating point" patented technology

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A multi-ladar sensor system is proposed for operating in dense environments where many ladar sensors are transmitting and receiving burst mode light in the same space, as may be typical of an automotive application. The system makes use of several techniques to reduce mutual interference between independently operating ladar sensors. In one embodiment, the individual ladar sensors are each assigned a wavelength of operation, and an optical receive filter for blocking the light transmitted at other wavelengths, an example of wavelength division multiplexing (WDM). Each ladar sensor, or platform, may also be assigned a pulse width selected from a list, and may use a pulse width discriminator circuit to separate pulses of interest from the clutter of other transmitters. Higher level coding, involving pulse sequences and code sequence correlation, may be implemented in a system of code division multiplexing, CDM. A digital processor optimized to execute mathematical operations is described which has a hardware implemented floating point divider, allowing for real time processing of received ladar pulses, and sequences of pulses.

Strategies are described for processing image information in a linear form to reduce the amount of artifacts (compared to processing the data in nonlinear form). Exemplary types of processing operations can include, scaling, compositing, alpha-blending, edge detection, and so forth. In a more specific implementation, strategies are described for processing image information that is: a) linear; b) in the RGB color space; c) high precision (e.g., provided by floating point representation); d) progressive; and e) full channel. Other improvements provide strategies for: a) processing image information in a pseudo-linear space to improve processing speed; b) implementing an improved error dispersion technique; c) dynamically calculating and applying filter kernels; d) producing pipeline code in an optimal manner; and e) implementing various processing tasks using novel pixel shader techniques.

A system (300, 500) for scrambling digital samples (115, 200, 250, 260, 270) of multimedia data, including audio and video data samples, such that the content of the samples is degraded but still recognizable, or otherwise provided at a desired quality level. The samples may be in any conceivable compressed or uncompressed digital format, including Pulse Code Modulation (PCM) samples, samples in floating point representation, samples in companding schemes (e.g., μ-law and A-law), and other compressed bit streams. The quality level may be associated with a particular signal to noise ratio, or quality level that is determined by objective and / or subjective tests, for example. A number of LSBs can be scrambled in successive samples in successive frames (FRAME A, FRAME B, FRAME C). Moreover, the parameters for scrambling may change from frame to frame. Furthermore, all or part of the scrambling key (310) can be embedded (340) in the scrambled data and recovered at a decoder (400, 600) to be used in descrambling. After descrambling, the scramble key is no longer recoverable because the scramble key itself is scrambled by the descrambler.

Configuration software is used for generating hardware-level code and data that may be used with reconfigurable / polymorphic computing platforms, such as logic emulators, and which may be used for conducting signals intelligence analysis, such as encryption / decryption processing, image analysis, etc. A user may use development tools to create visual representations of desired process algorithms, data structures, and interconnections, and system may generate intermediate data from this visual representation. The Intermediate data may be used to consult a database of predefined code segments, and segments may be assembled to generate monolithic block of hardware syhthesizable (RTL, VHDL, etc.) code for implementing the user's process in hardware. Efficiencies may be accounted for to minimize circuit components or processing time. Floating point calculations may be supported by a defined data structure that is readily implemented in hardware.

A system, such as a PC, incorporating a dedicated physics processing unit adapted to generate physics data for use within a physics simulation or game animation. The hardware-based physics processing unit is characterized by a unique architecture designed to efficiently calculate physics data, including multiple, parallel floating point operations.

A data processing system comprises a pressure-sensitive input device for assigning a floating-point value to a parameter under control of a pressure applied to the device. The system is operative to detect a rate of change of the pressure to control the assigning, e.g., to validate the current value as being input or to unlock the value as set.

A computer is programmed to emulate a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments of the just-described computer emulate a fixed-point operation by: expanding at least one fixed-point operand into a floating-point representation (also called “floating-point equivalent”), performing, on the floating-point equivalent, a floating-point operation that corresponds to the fixed-point operation, and reducing a floating-point result into a fixed-point result. The just-described fixed-point result may have the same representation as the fixed-point operand(s) and / or any user-specified fixed-point representation, depending on the embodiment. Also depending on the embodiment, the operands and the result may be either real or complex, and may be either scalar or vector. The above-described emulation may be performed either with an interpreter or with a compiler, depending on the embodiment. A conventional interpreter for an object-oriented language (such as MATLAB version 6) may be extended with a toolbox to perform the emulation. Use of type propagation and operator overloading minimizes the number of changes that a user must make to their program, in order to be able to use such emulation.

A method and processor for providing context-based adaptive binary arithmetic CABAC coding. Binarization is performed on one or more syntax elements to obtain a binary sequence. Data bits of the said binary sequence are provided to an arithmetic encoding unit in bulk. Binarization is performed on one or more syntax elements to generate exp Golomb code by converting mapped syntax-element values to corresponding floating point type values. Re-normalization of CABAC encoding is performed by restructuring the re-normalization into two processing units including an arithmetic encoding unit and a bit writing unit. The bit writing unit is configured to format signal bits into a multiple-bit sequence, and write multiple bits simultaneously during an execution of a bit writing loop.

System and method for displaying signals. First user input requesting display of a first signal is received, e.g., to a graphical user interface (GUI) comprised in a signal analysis function development environment, and the first signal programmatically analyzed in response to the first user input. A display tool operable to display the first signal is programmatically determined based on said analyzing, and the first signal displayed in the display tool, e.g., a data type of the first signal is determined, e.g., integer, floating point, Boolean, or user-defined data in a time-domain, frequency-domain, or spatial-domain, and the display tool programmatically determined based on the determined data type, e.g., via a loop-up table, where the display tool comprises an indicator operable to display the signal data. The signal comprises signal data, e.g., signal plot data, where the display tool comprises a graph, or tabular data, where the display tool comprises a table.