129 results about "Arbiter" patented technology

The invention discloses a patent disclosure auxiliary writing method and system based on multi-agent collaboration. The method comprises the steps that a multi-agent system composed of a collaboration agent, an agent agent and an expert agent is constructed, a knowledge base and a decision module of each agent are configured, and a collaboration architecture of a task scheduler, an arbiter and a shared information space is established; the method comprises the following steps: receiving an original technical scheme of a user, and constructing a structured intermediate representation through multi-agent parallel semantic analysis and feature extraction; based on the representation, a writing task sequence is generated through dynamic task decomposition, intelligent agent division is coordinated through a contract network protocol, and content generation and verification are completed based on a multi-round debate mechanism; performing multi-dimensional consistency detection on the generated draft, and eliminating logic conflicts and expressing defects through iterative revision; and finally, an interest portrait is generated based on the user technical scheme and the optimized draft, interest retrieval is performed, a technical content report is output, and the efficiency and quality of disclosure book writing are improved.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

The invention provides a TCAM-based message header data processing method and related equipment, and the method comprises the steps: caching and inputting message header data through an FIFO queue, and scheduling the message header data to a message header processing assembly line composed of a TCAM memory, an RAM memory and a parallel processor through an arbiter; a round processing mechanism is combined and adopted, a lookup key value of the current round is matched with an index value in a TCAM in each round of processing, an action table in an RAM is read according to the index value, and a message header analysis instruction of the current round, a group key instruction of the next round and a jump state value of the next round are obtained; executing the instruction through the parallel processor to obtain and update message metadata; when each round is finished, whether the round is finished or not is judged based on the jump state value of the next round; and after the round is finished, outputting the obtained final message metadata by the order-preserving cache queue. According to the invention, the message header data is analyzed by using the TCAM-based data processing technology, so that the flexibility of message header analysis is improved.

The invention relates to the technical field of computers, and discloses a topological structure generation method, a communication method, equipment, a chip and a program product. The topological structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between a plurality of master ports and a plurality of slave ports and first data bit widths of the plurality of master ports and the plurality of slave ports, and the mapping relationship comprises that at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same slave port in the plurality of slave ports. At least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topological structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters; and generating a topological structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, the topological structure file comprising connection lines among the plurality of master ports, the plurality of slave ports and the at least one arbiter. A user does not need to manually configure an arbiter and calculate, and the labor cost is saved.

The invention discloses a high-speed multi-port cache arbiter with a variable word length. Along with the high-speed development of the modern network technology, storage management and scheduling take up most of time in the processing of data packets by network equipment, so that the low-speed caching capability of most memories becomes a bottleneck for limiting the further improvement of a network processor. Therefore, by managing the shared cache of not less than 32 blocks of 256Kbit SRAM units and supporting simultaneous cache writing of a plurality of ports through an arbitration mechanism, write scheduling and read scheduling can be realized without mutual influence, and concurrent read-write conflicts are avoided; meanwhile, each port supports eight priority queues, so that the data transmission bandwidth of each port can reach 1G bps; by processing a data packet, caching and data scheduling according to packets are supported, the length of the data packet is 64-1024 bytes variable, and the influence of the length of the data packet on memory resources can be avoided; and the purpose of storing resources can be achieved by dynamically adjusting space saving through memory recovery, and the data storage efficiency is improved.

The embodiment of the invention discloses a data transmission method and device of a network-on-chip, a routing node and a storage medium, and the method comprises the steps: confirming a target output direction of a data message under the condition that the data message sent by an upstream routing node is received; writing the data message into a target output register or a target backup register in the target output direction based on an arbitration result of the target arbiter in the target output direction for the data message, or sending a retransmission signal for the data message to an upstream routing node; sending a data message to a downstream routing node in the target output direction through the target output register or the target backup register, and temporarily storing the data message in the target backup register or the target output register before confirming that the downstream routing node receives the data message; and sending the data message to the downstream routing node from the target backup register or the target output register under the condition that a retransmission signal sent by the downstream routing node to the data message is received.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.

A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes circuits to receive a packet, determine a size of the packet, determine a group of a plurality of groups of the packet based on the size of the packet, determine a port for the packet using a round-robin for the group of the packet, and send the packet via the port. Described systems include circuits to receive packet sizes from an application, initialize packet arbiter circuits based on the sizes, receive a packet associated with the application, determine a size of the packet, associate the packet with one of the packet arbiter circuits, and route the packet to a selected port.

A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

The present disclosure provides a memory controller for managing memory access requests from a plurality of masters. The memory controller may include a master decoding engine configured to decode memory access response traffic for the plurality of masters, a master latency storage configured to store a plurality of latency parameters, per-master first-in-first-out (FIFO) buffers configured to store a plurality of responses pending transmission to a respective master, a timer module configured to determine elapsed time and to accumulate latency error statistics, an adaptive weight generation engine configured to receive the latency error statistics and to generate one or more arbitration weights for each of the plurality of masters based on the latency error statistics, and a weighted arbiter configured to arbitrate between the plurality of responses ready for transmission from the per-master FIFO buffers.

The invention relates to a ZYNQ-based multichannel AD9361 controller and a control method, and relates to the technical field of digital signal processing. Comprising an ARM processing system and a programmable logic system, and a controller module and a signal processing algorithm module are arranged in the programmable logic system; the controller module comprises an AD9361 controller 1 arranged in the ARM processing system, and an AD9361 controller 2, an arbiter, an AXI controller and a data distributor which are arranged in the programmable logic system, and further comprises independent SPI interfaces and independent GPIO interfaces which are in one-to-one correspondence with the AD9361 chips; the AD9361 controller 1 and the AD9361 controller 2 apply for a data transmission control right to the arbiter according to a control demand; each independent SPI interface and each independent GPIO interface are respectively connected with an SPI pin and a GPIO pin of the corresponding AD9361 chip; the ARM processing system and the programmable logic system are interconnected through an AXI bus. The circuit can be externally connected with a plurality of AD9361 chips, and supports multi-channel parallel control.

In described examples, a coherent memory system (600) includes a central processing unit (CPU) and first and second levels of cache. The memory system (600) can include a pipeline (630) for accessing data stored in one of the caches. A requestor (e.g., 601) can access the data stored in one of the caches by sending requests that can be arbitrated (e.g., 63) by the pipeline (630) concurrently.

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.

The invention provides a memory access method, a memory, a storage medium and electronic equipment. The memory access method comprises the following steps: uniformly distributing a target Bank number for an operation request by a Bank number distributor; the intelligent scheduling arbiter judges whether the operation requests corresponding to the same Bank have read-write conflicts or not based on the target Bank numbers of the operation requests; when it is determined that the operation requests corresponding to the same Bank have read-write conflicts, the intelligent scheduling arbiter stores one or more operation requests in the queue in a multi-input multi-output register based on CSR setting; and the intelligent scheduling arbiter controls the execution sequence of the operation requests in the queue and the operation requests in the multi-input multi-output register. Through the method, read-write conflicts for the same Bank can be avoided, global dynamic priority setting is supported, the output bandwidth of a memory is fully utilized, and the processing efficiency of data requests is improved.

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

The invention discloses a method and a system for generating SQL (Structured Query Language) statements in a template configuration manner, and belongs to the technical field of database access. The method comprises the following steps: firstly, solidifying four tuples of stmttype, field,: tbl and where on a template side by using XML / JSON, locking one of four styles of% s,-, {} and: name at one time by using a placeholder style arbiter, and generating a golden sequence vector after DOM / JSON double analysis and regular global scanning; then, parameters are obtained on the data side through db / file / API three-state routing, a single quotation is automatically added to string / data class values through a silicon-level quotation hardening circuit, number class values are directly transmitted in an unvarnished mode, and object-by-object fusing check is conducted through a key integrity sniffer in a batch scene; and finally, performing mmap original text re-loading on each record by a template hot loading isolator on a generation side, and realizing page-level isolation and zero-residue output by combining SIMD replacement and cache line scouring. The method is suitable for high-security, high-concurrency and high-real-time scenes such as cloud, edges and production lines.

An arbiter is operable to pick commands from a command queue to dispatch to a memory. The arbiter includes a traffic throttling circuit to cooperate with one or more additional arbiters to mitigate excess power usage increases. The traffic throttling circuit includes a monitoring circuit and a throttling circuit. The monitoring circuit is to measure a number of read and write commands picked by the arbiter and the one or more additional arbiters within a first predetermined time period. The throttling circuit is to limit a number of read and write commands issued by the arbiter during a second predetermined time period in response to a low activity state.

A system comprises a reconfigurable processor including a network of a plurality of switches; an array of configurable units connected to the network and configured to execute an application. Each switch includes a plurality of input and output ports. A first input port of a switch is coupled to a first memory having a first bandwidth and a second input port of the switch is coupled to a memory having a second bandwidth. The switch is coupled to transfer a first data from the first memory via the first input port and a second data from the second memory via the second input to a common output port. The system includes an arbiter that selects the first input port and the second input port to transfer data to the common output port for a time proportional to the first bandwidth and the second bandwidth respectively.

The application discloses a virtual machine monitor-based interrupt processing method and device, a terminal device and a chip. The method comprises the following steps: an arbitrator arranged in a privileged virtual machine (VM) configures an interrupt use right for a non-privileged VM; and a virtual machine monitor establishes a pass-through between the non-privileged VM and a physical peripheral according to the interrupt use right of the non-privileged VM. The application can improve the efficiency of interrupt response based on the virtual machine monitor, and improve the flexibility of the pass-through function between the VM and the physical peripheral.

Embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. An intelligent arbiter notifies chiplets of VR events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding VR requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. As chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.

The application relates to the electronic information technical field and provides a universal serial bus Type-C interface protection method, a universal serial bus Type-C interface, a control arbitrator, a chip and a chip module. The method comprises the following steps: obtaining a hardware counting result; the hardware counting result is obtained by a hardware counter according to an external device insertion detection signal of a hardware switch; the external device insertion detection signal represents whether an external device is inserted into the universal serial bus Type-C interface; obtaining a software counting result; the software counting result is obtained by a software counter according to a software function calling signal; and in the case that the sum of the hardware counting result and the software counting result indicates that the universal serial bus Type-C interface is not inserted with the external device, the universal serial bus Type-C interface is controlled to be in a power-off state. By adopting the method, it can be ensured that in the universal serial bus Type-C interface protection scene, the universal serial bus Type-C interface can still work normally when one of the hardware aspect or the software aspect is invalid or has a problem.

The application discloses a server and an AXI interconnection device and method thereof, applied to the technical field of device interconnection, and comprises a decoder configured to receive and parse a sideband signal transmitted by a first device; an internal router connected with the first device and at least two second devices through an AXI bus, configured to determine an operation object of the first device according to a parsing result, receive operation content transmitted by the first device and send the operation content to the operation object for execution, and feed back feedback information to the first device; and an arbitrator connected with the first device and at least two third devices through the AXI bus, configured to send, in an arbitration manner, operation content transmitted by any one of the third devices to the first device for execution, and feed back feedback information of the first device to the third device. The application can realize AXI interconnection, has a simple structure, and can avoid the problems of large chip area occupation, resource and space waste.

The invention provides a dynamic dual-state deployment management method and system for a hybrid cloud environment, belongs to the technical field of cloud computing and edge computing fusion deployment, and aims to solve the problems that deployment of a large cloud platform and an all-in-one machine platform needs multi-branch maintenance, scripts are manually changed, and separate deployment packages are easy to select mistakenly. In the construction stage, a pre-compiling engine scans a condition compiling instruction in an SQL and configuration template, environment exclusive resources are generated according to platform types, and resource hash and deployment package fingerprints are calculated; in the deployment stage, a dynamic arbiter judges a target environment according to the priorities of forced configuration, Kubernetes node tags, hardware fingerprints and default values, and loads matching configuration and pre-compiling resources; and the consistency verification module executes matching verification of the template hash, the resource hash and the runtime hash, and gives an alarm and stops or returns in case of abnormality. Uniform delivery, reliable deployment and traceable rollback are realized by only loading applicable functions in different environments through the same deployment package and combining version migration and security isolation.

This invention belongs to the field of hardware security technology and discloses a two-stage reliability enhancement circuit and response generation method suitable for Response Feedback Authentication Function (APUF). It includes a delay difference detection circuit and a majority voting circuit. The delay difference detection circuit comprises two identical additional delay modules symmetrically arranged vertically and three arbitrators. The two additional delay modules are respectively connected to the upper and lower delay chains of the APUF and are composed of multiple inverters connected in series. The delay difference between the delay modules is changed by altering the number of inverters. The three arbitrators are used to generate three different responses. The majority voting circuit includes a counter, initially set to 0, which increments by 1 when the APUF response is "1". This invention filters the APUF response delay during the feedback phase, only feeding back responses with larger delay differences. Compared to a pure voting method, this reduces the number of majority votes required for reliability enhancement and improves the efficiency of the authentication protocol.

Embodiments of the present disclosure provide a data transmission device, a data transmission method, a processor and an electronic device. The data transmission device comprises at least one first ring link, the first ring link comprising a plurality of arbitrators connected in sequence, each of the plurality of arbitrators being connected with at least one data sending unit of a plurality of data sending units and / or at least one data receiving unit of a plurality of data receiving units, the arbitrator being configured to: monitor whether there is a bandwidth surplus on the first ring link, in response to the existence of the bandwidth surplus, allow the data sending unit connected with the arbitrator to send a first data packet onto the first ring link and transmit along the first ring link; and / or receive a second data packet transmitted along a transmission direction from the first ring link, and determine whether to transmit the second data packet to the data receiving unit connected with the arbitrator. The data transmission device can effectively avoid the congestion and delay problems caused by data centralization.

The invention discloses a lightweight arbiter PUF entropy enhancement method and system based on order-variable XOR confusion, and the method comprises the steps: constructing an order-variable XOR confusion lightweight arbiter PUF which comprises a configurable link, a k XOR gate group and a multiplexer; the excitation is input into an XOR confusion lightweight arbiter PUF with uncertain order, and a signal transmission path is selected according to the value of the excitation; on the basis of a signal transmission path, an enable signal is input into the order-variable XOR confusion lightweight arbiter PUF, signal transmission is carried out according to the characteristics of a configurable link, an intermediate response signal is obtained, the intermediate response signal is processed by a k XOR gate group and a multiplexer, a final response is obtained, and entropy enhancement of the PUF is completed. According to the method, the actual excitation range of the PUF can be fuzzified, and the capability of resisting machine learning modeling attack is remarkably improved.

The invention discloses a self-adaptive QoS arbitration method and device for an image system, and belongs to the field of computer hardware and data communication. According to the method, a priority locking mechanism and a credit refreshing mechanism triggered by authorization switching are introduced, so that the bus utilization rate is improved, the arbitration logic overhead is reduced, and concurrent access management of multiple channels on shared memory resources is realized. According to the structural design, a channel transaction management module and a GST-WA core arbitration module are designed, high decoupling of read-write transactions and arbitration logic is achieved, and standardized processing is conducted on data streams with channels as units. Meanwhile, an arbiter combines credit depletion forced propulsion and a deadlock prevention mechanism to realize effective balance between QoS guarantee and long-term fairness of a high-weight channel.

The embodiment of the invention provides an optimization method and device of a high-speed data path, computer equipment and a storage medium. The method comprises the steps that cache spaces of a ping-pong register and an output register are set in a buffer; if the cache space is empty, writing input data into the cache space, modifying an input write fifo interface and a fifo full flag bit interface into an input handshake interface, and modifying an output read fifo interface and a fifo empty flag bit interface into an output handshake interface; taking the maximum storage capacity of the internal effective count fifo as an additional newly-added output interface; if the fifo storage space is full, actively outputting data in the storage space, setting a stack cache space in an arbiter, taking the requests input at the same time as a request group, and putting the request group into the stack cache space according to an input sequence; and arbitration sorting is carried out on the request group, so that the problems of interface conversion, data routing and the like can be solved by combining an optimized buffer, a first-in first-out queue and an arbiter.

A memory scheduling device includes a pre-processing storage, a selector, a current storage, and an arbiter. The pre-processing storage provides a plurality of main commands and a plurality of secondary commands. The selector selects the main commands and / or the secondary commands based on a selection signal. The current storage receives the main commands and / or the secondary commands transmitted from the selector. The arbiter precomputes a predict burst length corresponding to the main commands expected to be received by the current storage based on a round-robin sequence. If the predict burst length corresponding to the main commands is less than a threshold burst length, the arbiter transmits the selection signal to the selector, such that the pre-processing storage transmits a portion of main commands and at least one secondary command of the secondary commands to the current storage through the selector.