225 results about "Arbiter" patented technology

The invention discloses a patent disclosure auxiliary writing method and system based on multi-agent collaboration. The method comprises the steps that a multi-agent system composed of a collaboration agent, an agent agent and an expert agent is constructed, a knowledge base and a decision module of each agent are configured, and a collaboration architecture of a task scheduler, an arbiter and a shared information space is established; the method comprises the following steps: receiving an original technical scheme of a user, and constructing a structured intermediate representation through multi-agent parallel semantic analysis and feature extraction; based on the representation, a writing task sequence is generated through dynamic task decomposition, intelligent agent division is coordinated through a contract network protocol, and content generation and verification are completed based on a multi-round debate mechanism; performing multi-dimensional consistency detection on the generated draft, and eliminating logic conflicts and expressing defects through iterative revision; and finally, an interest portrait is generated based on the user technical scheme and the optimized draft, interest retrieval is performed, a technical content report is output, and the efficiency and quality of disclosure book writing are improved.

The invention belongs to the technical field of electronic measuring instruments, and particularly relates to an output protection method of a source meter, which comprises the following steps of: configuring an operation mode of a digital controller; executing closed-loop control of the main regulator; the arbiter continuously monitors the output state, and intelligently arbitrates and switches the main regulator, the clamping regulator and the output channel according to the measurement feedback value, the clamping threshold value and the over-limit threshold value, thereby achieving the precise clamping and over-limit protection of the output. By adopting the technical scheme, the flexibility, refined protection and adaptability of source table output control can be remarkably improved, the hardware cost is reduced, and the system reliability is improved.

The invention discloses a whole-body collaborative voice control system and method for a humanoid robot, relates to the technical field of robots, and aims to solve the problems of semantic understanding superficial layer, action planning localization and safety control lagging in existing humanoid robot voice control. Through closed-loop cooperation of the multi-mode intention understanding module, the whole-body action planning module, the dynamic balance security arbiter and the microkernel security scheduler, a unified control architecture is constructed. According to the system, natural language instructions are deeply analyzed into whole-body motion constraints through a semantic-action mapping knowledge base, anthropomorphic collaborative motion trails are generated, pre-security verification is conducted through a boundary model based on Lyapunov stability, and finally hard real-time execution and full-cycle security guarding are achieved through a microkernel security scheduler. According to the method, direct conversion from natural language to safe, stable and anthropomorphic whole-body motion is realized, and the task execution capability and the interaction naturalness of the humanoid robot in a complex scene are remarkably improved.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

The invention provides an LLM output stability control method and system based on reinforcement learning, and the method comprises the steps: carrying out the multi-modal structured analysis of literature data, extracting a content unit, and constructing a feature vector set and an association mapping table; the text logic processing module and the visual semantic processing module are driven in parallel to interpret the cross-modal task unit, and an initial abstract set is constructed; in a cross-modal consistency reward-driven iterative closed loop, constructing a joint action according to a current joint state, calculating a reward signal by a cross-modal consistency arbiter, and constructing a near-end strategy optimization algorithm to update a strategy network until the reward signal converges; and based on the association mapping table, the sequence-to-sequence language model is driven to reconstruct the final text abstract and the information description set of the final joint state set, and a final abstract is generated. Through structured analysis and multi-mode cooperative control, the consistency and stability of abstract contents are ensured, and the method is suitable for the field of natural language processing and reinforcement learning.

The invention provides an artificial intelligence processor, an electronic device and a data transmission method. The artificial intelligence processor comprises: a data transmission assistance unit configured to transmit a data transmission request for target data; the communication device is configured to transmit a data transmission request for the data transmission assistance unit, a plurality of external communication channels used for transmitting target data by a communication network connected with the artificial intelligence processor are configured in the communication device, each external communication channel is configured to provide a plurality of virtual sub-channels, and each virtual sub-channel is configured to transmit the target data to the data transmission assistance unit. Wherein the communication device comprises an arbiter, and the communication device is configured to arbitrate a plurality of provided virtual sub-channels to obtain a target virtual sub-channel by using the arbiter, and transmit target data by using the target virtual sub-channel. According to the artificial intelligence processor, the data transmission capability between the artificial intelligence processors can be effectively improved, and the congestion phenomenon is avoided.

The invention discloses a polling arbitration method and a polling arbitration system for dynamically updating weight by an EWMA algorithm, and the method comprises the following steps: monitoring and receiving a request signal sent by each AHB bus channel on a matrix bus in real time; taking a preset arbitration period as a time window, collecting the current request access times of each AHB bus channel, reading the historical request times stored in the last period, calculating the request variation of each channel, and performing uniform quantization; and on the basis of the historical weight value and the quantized value, an exponentially weighted moving average value is calculated through an EWMA algorithm. When the method is used, the actual weight value of each AHB channel can be adaptively and dynamically adjusted every fixed arbitration period number, resource allocation and system fairness are improved, and it is ensured that an arbiter can more accurately reflect the actual demand of each AHB channel on a matrix bus.

The invention provides a TCAM-based message header data processing method and related equipment, and the method comprises the steps: caching and inputting message header data through an FIFO queue, and scheduling the message header data to a message header processing assembly line composed of a TCAM memory, an RAM memory and a parallel processor through an arbiter; a round processing mechanism is combined and adopted, a lookup key value of the current round is matched with an index value in a TCAM in each round of processing, an action table in an RAM is read according to the index value, and a message header analysis instruction of the current round, a group key instruction of the next round and a jump state value of the next round are obtained; executing the instruction through the parallel processor to obtain and update message metadata; when each round is finished, whether the round is finished or not is judged based on the jump state value of the next round; and after the round is finished, outputting the obtained final message metadata by the order-preserving cache queue. According to the invention, the message header data is analyzed by using the TCAM-based data processing technology, so that the flexibility of message header analysis is improved.

A graphics processing unit (GPU) and method for processing primitives using a rendering space subdivided into a plurality of tiles are described. The GPU includes a partitioning module that includes a plurality of tile pipelines and a tile arbiter. The tile arbiter receives tile-primitive indications, wherein each of the tile-primitive indications indicates an association between a tile and a set of one or more primitives. The tile arbiter determines to which of the tile pipelines each of the tile-primitive indications is to be sent, according to a dynamic allocation scheme that does not have a fixed mapping between a tile and tile pipeline. The tile arbiter transmits each of the tile-primitive indications to the tile pipeline that is determined for the tile-primitive indication.

The invention relates to the technical field of computers, and discloses a topological structure generation method, a communication method, equipment, a chip and a program product. The topological structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between a plurality of master ports and a plurality of slave ports and first data bit widths of the plurality of master ports and the plurality of slave ports, and the mapping relationship comprises that at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same slave port in the plurality of slave ports. At least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topological structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters; and generating a topological structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, the topological structure file comprising connection lines among the plurality of master ports, the plurality of slave ports and the at least one arbiter. A user does not need to manually configure an arbiter and calculate, and the labor cost is saved.

A pod-pinning tool selects a Kubernetes pod to act as an arbiter pod that controls pod allocation for nodes from a plurality of candidate pods. Responsive to determining that a scaling operation is to be performed, the pod-pinning tool instructs the arbiter pod to generate a placeholder node while an assigned node is instantiated. The pod-pinning tool instructs the arbiter pod to bind one or more particular pods to the placeholder node. Responsive to determining that the assigned node is instantiated, the pod-pinning tool instructs the arbiter pod to clear the placeholder node.

The invention provides a multi-channel request priority arbitration method and system, and the method comprises the steps: carrying out the grouping of all requests based on a grouping device, gating a request group from a plurality of grouped request groups based on a gating device, and enabling the gated request group to enter an arbiter; a plurality of requests in the gated group of requests are arbitrated in an arbiter based on a fixed priority policy. According to the invention, all requests are grouped by using a grouping device, the requests in the same group are arbitrated according to a fixed priority, and the arbitration sequence is controlled between the request groups by using a gating device; it is guaranteed that requests of low-priority channels in a high-priority group cannot occupy arbitration channels by high-priority channels in a low-priority group, and therefore the problem that when multi-priority tasks are processed at the same time in a complex system, system functions are not converged due to task dependence and priority conflicts is solved; and the problem of low-priority channel hunger caused by high-priority channel occupation is effectively relieved.

The invention belongs to the field of exchange chips, and relates to a dynamic allocation device and method for a shared cache quota of an exchange chip, and the device comprises a rate difference index calculator, a burst index calculator, a back pressure index calculator, a quota index calculator and a quota calculator. According to the method, the characteristics of data traffic are monitored from multiple dimensions, burst traffic is well absorbed, the method adapts to the difference of transmitting and receiving rates, and the waiting time of input data is considered. According to the method, the shared cache quota can be dynamically and adaptively adjusted in real time, meanwhile, the weight of the arbiter at the destination end to each source port also changes along with linkage of the shared cache quota, fairness is considered on the whole, and efficiency is improved. Compared with a traditional dynamic cache sharing method, the method can solve the problem that some channels occupy large or all shared caches under the unreasonable condition, and other channels do not have or only have small available caches.

The invention discloses a high-speed multi-port cache arbiter with a variable word length. Along with the high-speed development of the modern network technology, storage management and scheduling take up most of time in the processing of data packets by network equipment, so that the low-speed caching capability of most memories becomes a bottleneck for limiting the further improvement of a network processor. Therefore, by managing the shared cache of not less than 32 blocks of 256Kbit SRAM units and supporting simultaneous cache writing of a plurality of ports through an arbitration mechanism, write scheduling and read scheduling can be realized without mutual influence, and concurrent read-write conflicts are avoided; meanwhile, each port supports eight priority queues, so that the data transmission bandwidth of each port can reach 1G bps; by processing a data packet, caching and data scheduling according to packets are supported, the length of the data packet is 64-1024 bytes variable, and the influence of the length of the data packet on memory resources can be avoided; and the purpose of storing resources can be achieved by dynamically adjusting space saving through memory recovery, and the data storage efficiency is improved.

The embodiment of the invention discloses a data transmission method and device of a network-on-chip, a routing node and a storage medium, and the method comprises the steps: confirming a target output direction of a data message under the condition that the data message sent by an upstream routing node is received; writing the data message into a target output register or a target backup register in the target output direction based on an arbitration result of the target arbiter in the target output direction for the data message, or sending a retransmission signal for the data message to an upstream routing node; sending a data message to a downstream routing node in the target output direction through the target output register or the target backup register, and temporarily storing the data message in the target backup register or the target output register before confirming that the downstream routing node receives the data message; and sending the data message to the downstream routing node from the target backup register or the target output register under the condition that a retransmission signal sent by the downstream routing node to the data message is received.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.

A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes circuits to receive a packet, determine a size of the packet, determine a group of a plurality of groups of the packet based on the size of the packet, determine a port for the packet using a round-robin for the group of the packet, and send the packet via the port. Described systems include circuits to receive packet sizes from an application, initialize packet arbiter circuits based on the sizes, receive a packet associated with the application, determine a size of the packet, associate the packet with one of the packet arbiter circuits, and route the packet to a selected port.

A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

The present disclosure provides a memory controller for managing memory access requests from a plurality of masters. The memory controller may include a master decoding engine configured to decode memory access response traffic for the plurality of masters, a master latency storage configured to store a plurality of latency parameters, per-master first-in-first-out (FIFO) buffers configured to store a plurality of responses pending transmission to a respective master, a timer module configured to determine elapsed time and to accumulate latency error statistics, an adaptive weight generation engine configured to receive the latency error statistics and to generate one or more arbitration weights for each of the plurality of masters based on the latency error statistics, and a weighted arbiter configured to arbitrate between the plurality of responses ready for transmission from the per-master FIFO buffers.

The invention relates to a ZYNQ-based multichannel AD9361 controller and a control method, and relates to the technical field of digital signal processing. Comprising an ARM processing system and a programmable logic system, and a controller module and a signal processing algorithm module are arranged in the programmable logic system; the controller module comprises an AD9361 controller 1 arranged in the ARM processing system, and an AD9361 controller 2, an arbiter, an AXI controller and a data distributor which are arranged in the programmable logic system, and further comprises independent SPI interfaces and independent GPIO interfaces which are in one-to-one correspondence with the AD9361 chips; the AD9361 controller 1 and the AD9361 controller 2 apply for a data transmission control right to the arbiter according to a control demand; each independent SPI interface and each independent GPIO interface are respectively connected with an SPI pin and a GPIO pin of the corresponding AD9361 chip; the ARM processing system and the programmable logic system are interconnected through an AXI bus. The circuit can be externally connected with a plurality of AD9361 chips, and supports multi-channel parallel control.

In described examples, a coherent memory system (600) includes a central processing unit (CPU) and first and second levels of cache. The memory system (600) can include a pipeline (630) for accessing data stored in one of the caches. A requestor (e.g., 601) can access the data stored in one of the caches by sending requests that can be arbitrated (e.g., 63) by the pipeline (630) concurrently.

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.

The invention provides a memory access method, a memory, a storage medium and electronic equipment. The memory access method comprises the following steps: uniformly distributing a target Bank number for an operation request by a Bank number distributor; the intelligent scheduling arbiter judges whether the operation requests corresponding to the same Bank have read-write conflicts or not based on the target Bank numbers of the operation requests; when it is determined that the operation requests corresponding to the same Bank have read-write conflicts, the intelligent scheduling arbiter stores one or more operation requests in the queue in a multi-input multi-output register based on CSR setting; and the intelligent scheduling arbiter controls the execution sequence of the operation requests in the queue and the operation requests in the multi-input multi-output register. Through the method, read-write conflicts for the same Bank can be avoided, global dynamic priority setting is supported, the output bandwidth of a memory is fully utilized, and the processing efficiency of data requests is improved.

The invention discloses a multi-task priority determination method, a resource allocation method and a resource arbiter, and relates to the technical field of computers. In the method, the initial priorities of the multiple tasks are adjusted based on the initial priorities of the multiple tasks and the access information when the multiple tasks access the shared resources, that is, fixed priorities are not set for the tasks, so that the fairness when the tasks access the shared resources is improved; the priority of the task is adjusted, so that the priority of the previous task with low priority may become higher, namely, the delay of the previous task with low priority is reduced; due to the fact that the tasks are sorted according to the priorities, when the tasks access the shared resources according to the priority sequence, low delay of the tasks with the high priorities is guaranteed, and the efficiency of accessing the shared resources by the tasks is improved; and thirdly, the weights of the tasks are determined based on various factors such as the classification levels of the tasks, the membership degrees when the tasks belong to the corresponding classification levels and the rule weights, so that the accuracy of the target priorities of the multiple tasks is improved.

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

The invention provides an artificial intelligence chip and an operation method thereof. The AI chip includes an AI core, a flow control circuit, an arbiter, and a cache. The arbiter is coupled between the AI core and the cache. The flow control circuit is coupled between the AI core and the arbiter. The flow control circuit counts a back voltage condition of feedback data in a first feedback data path from the cache through the arbiter to the AI core. The flow control circuit dynamically determines whether to block the access request handshake between the AI core and the cache according to the back pressure condition of the feedback data.

Aspects of the disclosure relate to high performance connection schedulers, and in particular, to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, a dispatch queue, and a quality of service arbiter to support dispatching a large number of connections at a high rate.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

A distribution system receives data access requests associated with at least two virtual channels over at least two physical data communication channels. The requests are allocated into at least two sequencers of the allocation system based on a virtual channel associated with each request. The distribution system comprises at least two memory modules, and each physical data communication channel of the at least two physical data communication channels corresponds to one memory module. Requests stored in a sequencer are written to a memory module according to a successive ordered pattern that assigns successive requests associated with a common virtual channel to the memory module. The request is then granted by an arbiter of the distribution system by retrieving requests associated with the common virtual channel from the memory modules using successive ordering of the memory modules.