342 results about "Arbiter" patented technology

The invention provides a deep learning training and reasoning task dynamic cooperation system based on GPU space-time resource sharing, and the system comprises a GPU resource state perceptron which is used for monitoring a GPU kernel function call sequence and a video memory distribution state of a distributed training task in real time, dynamically capturing a calculation gap and video memory fragments generated by the training task, and transmitting the calculation gap and the video memory fragments to the GPU resource state perceptron; generating a two-dimensional resource spatial-temporal characteristic spectrum, and predicting a GPU calculation idle period caused by communication synchronization based on an LSTM model; the kernel function dynamic scheduling decision maker is used for performing priority division and dynamic resource quota allocation on an online reasoning task and an offline reasoning task by adopting a self-adaptive allocation strategy on the basis of a resource spatial-temporal characteristic spectrum so as to realize spatial-temporal resource decoupling of the training task and the reasoning task; and the kernel function execution arbiter is used for dynamically controlling submission and blockage of the reasoning task kernel function according to the scheduling decision through video memory space multiplexing and a calculation instruction arbitration mechanism. According to the method, the GPU resource utilization rate is remarkably improved, on the premise that stable training task performance is guaranteed, fragmented resources are effectively utilized to support parallel execution of multiple types of reasoning tasks, and efficient resource collaboration of a deep learning task cluster is achieved.

The invention relates to the technical field of data processing, in particular to a data fusion intelligent equipment linkage management and control system based on a large model, and the system comprises a data collection module which outputs standardized data carrying privacy grading identifiers; the data processing module outputs an optimization algorithm identifier and a collaborative strategy identifier which are synchronously bound; the privacy algorithm fusion scheduling module generates atomization calculation graph data and strategy audit logs fusing privacy operation; the multiple optimization resource module executes calculation graph data and drives a parallel simulation environment rehearsal resource scheme, and the double-closed-loop feedback module is activated when an arbiter continuously detects that deviation exceeds the standard for three times; the safety instruction generation module fuses the output result and the audit log to generate a digital signature equipment control instruction; and the double-closed-loop feedback module updates knowledge base weight parameters through a data feedback loop, and controls the feedback loop to adjust a resource allocation threshold in a grading manner according to simulation confidence, so that dynamic balance between resource efficiency and privacy intensity is realized.

The invention discloses a patent disclosure auxiliary writing method and system based on multi-agent collaboration. The method comprises the steps that a multi-agent system composed of a collaboration agent, an agent agent and an expert agent is constructed, a knowledge base and a decision module of each agent are configured, and a collaboration architecture of a task scheduler, an arbiter and a shared information space is established; the method comprises the following steps: receiving an original technical scheme of a user, and constructing a structured intermediate representation through multi-agent parallel semantic analysis and feature extraction; based on the representation, a writing task sequence is generated through dynamic task decomposition, intelligent agent division is coordinated through a contract network protocol, and content generation and verification are completed based on a multi-round debate mechanism; performing multi-dimensional consistency detection on the generated draft, and eliminating logic conflicts and expressing defects through iterative revision; and finally, an interest portrait is generated based on the user technical scheme and the optimized draft, interest retrieval is performed, a technical content report is output, and the efficiency and quality of disclosure book writing are improved.

The invention discloses a task-driven universal robot intelligent control method and system. According to the method, the skill library is constructed through the skill elements, so that a training robot does not need to face a huge data set when executing a task, and only needs to train a small amount of data to form the skill elements, thereby being beneficial to reducing data requirements, improving task success rate, keeping high performance and remarkably reducing data cost; meanwhile, by adding a skill generator and a skill arbiter, skill elements have better fineness and universality, reuse across different scenes and tasks is allowed, and complex tasks of the robot in a generalization scene are completed.

The invention discloses a data transmission controller and method, electronic equipment and a computer storage medium. The data transmission controller comprises N protocol layer controllers, an arbiter and a data link layer controller, wherein N is an integer greater than or equal to 2; the N protocol layer controllers are configured to transmit N pieces of protocol layer data; the arbiter is configured to receive N pieces of protocol layer data of the N protocol layer controllers and determine transmission priorities of the N pieces of protocol layer data; the data link layer controller is configured to transmit N protocol layer data according to a transmission priority. According to the data transmission controller, different protocol layers can share the same physical link resource, so that the utilization rate and the flexibility of the link are improved; meanwhile, isolation and protection of data of different protocol layers are realized.

In some embodiments, a system can include a first stream to be opened with an arbiter device, the first stream associated with a first set of capabilities, a second stream to be opened with the arbiter device, the second stream associated with a second set of capabilities, and a wireless network architecture that determines a network messaging schedule based on the first set of capabilities and the second set of capabilities. The network messaging schedule can be sent to one or more client devices associated with the first stream or the second stream.

The invention provides a multi-channel arbiter, which comprises a basic arbiter and a polling arbiter, and is characterized in that the basic arbiter is responsible for judging whether high-priority application signals exist in application signals or not, and arbitrating the high-priority signals in sequence until all the high-priority application signals are completed; during the period, the polling arbiter does not work; after the high-priority arbitration is completed, the polling arbitrator performs polling arbitration on the low-priority application signal, and the execution sequence is determined by a loop pointer; finally, arbitration results of the basic arbiter and the polling arbiter are output into an arbitration result signal through a first gate. According to the invention, efficient and ordered task scheduling can be realized.

The invention belongs to the technical field of electronic measuring instruments, and particularly relates to an output protection method of a source meter, which comprises the following steps of: configuring an operation mode of a digital controller; executing closed-loop control of the main regulator; the arbiter continuously monitors the output state, and intelligently arbitrates and switches the main regulator, the clamping regulator and the output channel according to the measurement feedback value, the clamping threshold value and the over-limit threshold value, thereby achieving the precise clamping and over-limit protection of the output. By adopting the technical scheme, the flexibility, refined protection and adaptability of source table output control can be remarkably improved, the hardware cost is reduced, and the system reliability is improved.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

The invention discloses a whole-body collaborative voice control system and method for a humanoid robot, relates to the technical field of robots, and aims to solve the problems of semantic understanding superficial layer, action planning localization and safety control lagging in existing humanoid robot voice control. Through closed-loop cooperation of the multi-mode intention understanding module, the whole-body action planning module, the dynamic balance security arbiter and the microkernel security scheduler, a unified control architecture is constructed. According to the system, natural language instructions are deeply analyzed into whole-body motion constraints through a semantic-action mapping knowledge base, anthropomorphic collaborative motion trails are generated, pre-security verification is conducted through a boundary model based on Lyapunov stability, and finally hard real-time execution and full-cycle security guarding are achieved through a microkernel security scheduler. According to the method, direct conversion from natural language to safe, stable and anthropomorphic whole-body motion is realized, and the task execution capability and the interaction naturalness of the humanoid robot in a complex scene are remarkably improved.

The present invention relates to the field of communications, and provides an on-chip network device and a routing method, the device comprising: a plurality of core nodes of a hexagonal topological structure, each core node comprising six communication channel modules and a routing module, the six communication channel modules being respectively connected with six adjacent core nodes; the routing module comprises an input distributor, an output arbiter, a synchronous first-in first-out queue unit and a local output cache, and the input distributor is used for distributing a data packet to a specific output channel according to a target address of the data packet and a routing algorithm; the output arbiter is used for selecting a data packet with a higher priority for transmission when a plurality of data packets compete for the same output channel; the six communication channel modules are sequentially in the X < Y + > direction, the X + direction, the Y-direction, the X < Y-> direction, the X-direction and the Y + direction in the clockwise direction. According to the invention, the problems of low communication bandwidth and difficulty in adapting to different congestion scenes of the network-on-chip in the prior art are solved, and a routing mechanism with high communication bandwidth and no deadlock is realized.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

The invention provides an LLM output stability control method and system based on reinforcement learning, and the method comprises the steps: carrying out the multi-modal structured analysis of literature data, extracting a content unit, and constructing a feature vector set and an association mapping table; the text logic processing module and the visual semantic processing module are driven in parallel to interpret the cross-modal task unit, and an initial abstract set is constructed; in a cross-modal consistency reward-driven iterative closed loop, constructing a joint action according to a current joint state, calculating a reward signal by a cross-modal consistency arbiter, and constructing a near-end strategy optimization algorithm to update a strategy network until the reward signal converges; and based on the association mapping table, the sequence-to-sequence language model is driven to reconstruct the final text abstract and the information description set of the final joint state set, and a final abstract is generated. Through structured analysis and multi-mode cooperative control, the consistency and stability of abstract contents are ensured, and the method is suitable for the field of natural language processing and reinforcement learning.

The invention provides an artificial intelligence processor, an electronic device and a data transmission method. The artificial intelligence processor comprises: a data transmission assistance unit configured to transmit a data transmission request for target data; the communication device is configured to transmit a data transmission request for the data transmission assistance unit, a plurality of external communication channels used for transmitting target data by a communication network connected with the artificial intelligence processor are configured in the communication device, each external communication channel is configured to provide a plurality of virtual sub-channels, and each virtual sub-channel is configured to transmit the target data to the data transmission assistance unit. Wherein the communication device comprises an arbiter, and the communication device is configured to arbitrate a plurality of provided virtual sub-channels to obtain a target virtual sub-channel by using the arbiter, and transmit target data by using the target virtual sub-channel. According to the artificial intelligence processor, the data transmission capability between the artificial intelligence processors can be effectively improved, and the congestion phenomenon is avoided.

The invention discloses a polling arbitration method and a polling arbitration system for dynamically updating weight by an EWMA algorithm, and the method comprises the following steps: monitoring and receiving a request signal sent by each AHB bus channel on a matrix bus in real time; taking a preset arbitration period as a time window, collecting the current request access times of each AHB bus channel, reading the historical request times stored in the last period, calculating the request variation of each channel, and performing uniform quantization; and on the basis of the historical weight value and the quantized value, an exponentially weighted moving average value is calculated through an EWMA algorithm. When the method is used, the actual weight value of each AHB channel can be adaptively and dynamically adjusted every fixed arbitration period number, resource allocation and system fairness are improved, and it is ensured that an arbiter can more accurately reflect the actual demand of each AHB channel on a matrix bus.

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

The invention provides a TCAM-based message header data processing method and related equipment, and the method comprises the steps: caching and inputting message header data through an FIFO queue, and scheduling the message header data to a message header processing assembly line composed of a TCAM memory, an RAM memory and a parallel processor through an arbiter; a round processing mechanism is combined and adopted, a lookup key value of the current round is matched with an index value in a TCAM in each round of processing, an action table in an RAM is read according to the index value, and a message header analysis instruction of the current round, a group key instruction of the next round and a jump state value of the next round are obtained; executing the instruction through the parallel processor to obtain and update message metadata; when each round is finished, whether the round is finished or not is judged based on the jump state value of the next round; and after the round is finished, outputting the obtained final message metadata by the order-preserving cache queue. According to the invention, the message header data is analyzed by using the TCAM-based data processing technology, so that the flexibility of message header analysis is improved.

A graphics processing unit (GPU) and method for processing primitives using a rendering space subdivided into a plurality of tiles are described. The GPU includes a partitioning module that includes a plurality of tile pipelines and a tile arbiter. The tile arbiter receives tile-primitive indications, wherein each of the tile-primitive indications indicates an association between a tile and a set of one or more primitives. The tile arbiter determines to which of the tile pipelines each of the tile-primitive indications is to be sent, according to a dynamic allocation scheme that does not have a fixed mapping between a tile and tile pipeline. The tile arbiter transmits each of the tile-primitive indications to the tile pipeline that is determined for the tile-primitive indication.

The invention relates to the technical field of computers, and discloses a topological structure generation method, a communication method, equipment, a chip and a program product. The topological structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between a plurality of master ports and a plurality of slave ports and first data bit widths of the plurality of master ports and the plurality of slave ports, and the mapping relationship comprises that at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same slave port in the plurality of slave ports. At least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topological structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters; and generating a topological structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, the topological structure file comprising connection lines among the plurality of master ports, the plurality of slave ports and the at least one arbiter. A user does not need to manually configure an arbiter and calculate, and the labor cost is saved.

A pod-pinning tool selects a Kubernetes pod to act as an arbiter pod that controls pod allocation for nodes from a plurality of candidate pods. Responsive to determining that a scaling operation is to be performed, the pod-pinning tool instructs the arbiter pod to generate a placeholder node while an assigned node is instantiated. The pod-pinning tool instructs the arbiter pod to bind one or more particular pods to the placeholder node. Responsive to determining that the assigned node is instantiated, the pod-pinning tool instructs the arbiter pod to clear the placeholder node.

The invention provides a multi-channel request priority arbitration method and system, and the method comprises the steps: carrying out the grouping of all requests based on a grouping device, gating a request group from a plurality of grouped request groups based on a gating device, and enabling the gated request group to enter an arbiter; a plurality of requests in the gated group of requests are arbitrated in an arbiter based on a fixed priority policy. According to the invention, all requests are grouped by using a grouping device, the requests in the same group are arbitrated according to a fixed priority, and the arbitration sequence is controlled between the request groups by using a gating device; it is guaranteed that requests of low-priority channels in a high-priority group cannot occupy arbitration channels by high-priority channels in a low-priority group, and therefore the problem that when multi-priority tasks are processed at the same time in a complex system, system functions are not converged due to task dependence and priority conflicts is solved; and the problem of low-priority channel hunger caused by high-priority channel occupation is effectively relieved.

An electronic device according to various embodiments may comprise: a memory and a processor operatively connected to the memory. The processor may include: a central processing unit including a cache memory; a neural processing unit; and an interconnector connected to the neural processing unit. The central processing unit may include an arbiter for connecting the cache memory to any one of a processing circuit of the central processing unit and the interconnector. The neural processing unit may exchange data with the cache memory through the arbiter.

A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

The invention belongs to the field of exchange chips, and relates to a dynamic allocation device and method for a shared cache quota of an exchange chip, and the device comprises a rate difference index calculator, a burst index calculator, a back pressure index calculator, a quota index calculator and a quota calculator. According to the method, the characteristics of data traffic are monitored from multiple dimensions, burst traffic is well absorbed, the method adapts to the difference of transmitting and receiving rates, and the waiting time of input data is considered. According to the method, the shared cache quota can be dynamically and adaptively adjusted in real time, meanwhile, the weight of the arbiter at the destination end to each source port also changes along with linkage of the shared cache quota, fairness is considered on the whole, and efficiency is improved. Compared with a traditional dynamic cache sharing method, the method can solve the problem that some channels occupy large or all shared caches under the unreasonable condition, and other channels do not have or only have small available caches.

A network filter request arbiter is provided. An interface (e.g., user interface and / or programmatic interface, such as an application programming interface (API)), is for configuring and automatically implementing one or more filters in an internal and / or external network. The filters may be used to stop distributed denial of service (DDOS) attacks and / or prevent malicious network traffic from reaching a target network or target device(s) within the target network. Filters implemented in a target network may also be distributed to other (e.g., upstream) networks. The distributed filters may similarly be used to stop DDOS attacks and / or prevent malicious network traffic from being carried by the networks and from reaching a target network or target device(s) within the target network.

The embodiment of the invention discloses a bandwidth allocation method and device for a network-on-chip and an arbiter. The method comprises the following steps: obtaining the number of confirmation signals received by each arbitration request channel in a target period and an input weight value of each arbitration request channel in the target period, and determining a single-round deviation value of each arbitration request channel in the target period according to the input weight value and the number of confirmation signals; and obtaining an accumulated deviation value according to the single-round deviation value, and distributing the bandwidth of each arbitration request channel in the next period according to the accumulated deviation value and the input weight value. Therefore, the utilization rate and the balance of bandwidth resources can be improved, and the overall performance of the system is further improved.

The present application discloses a geometry processing method and apparatus, a device, a storage medium, and a program product. The geometry processing method comprises: each primitive distribution unit acquires primitive cluster data in a geometry data stream, wherein the primitive cluster data comprises a first label used for determining the sequence of the primitive cluster data in the geometry data stream; the primitive distribution unit further divides the primitive cluster data into primitive group data, and distributes the primitive group data to corresponding geometry processing pipelines; the geometry processing pipelines process the primitive group data to obtain primitive group processing results, and output the primitive group processing results to a corresponding merging arbiter; and the merging arbiter performs merging processing on the primitive group processing results on the basis of a second label, so as to obtain geometry output data corresponding to the primitive cluster data.

The invention discloses a high-speed multi-port cache arbiter with a variable word length. Along with the high-speed development of the modern network technology, storage management and scheduling take up most of time in the processing of data packets by network equipment, so that the low-speed caching capability of most memories becomes a bottleneck for limiting the further improvement of a network processor. Therefore, by managing the shared cache of not less than 32 blocks of 256Kbit SRAM units and supporting simultaneous cache writing of a plurality of ports through an arbitration mechanism, write scheduling and read scheduling can be realized without mutual influence, and concurrent read-write conflicts are avoided; meanwhile, each port supports eight priority queues, so that the data transmission bandwidth of each port can reach 1G bps; by processing a data packet, caching and data scheduling according to packets are supported, the length of the data packet is 64-1024 bytes variable, and the influence of the length of the data packet on memory resources can be avoided; and the purpose of storing resources can be achieved by dynamically adjusting space saving through memory recovery, and the data storage efficiency is improved.