337 results about "Arbiter" patented technology

A client is permitted to send data access commands directly to network data storage of a network file server after obtaining a lock on at least a portion of the file and obtaining metadata indicating storage locations for the data in the data storage. For example, the client sends to the file server at least one request for access to a file. In response, the file server grants a lock to the client, and returns to the client metadata of the file including information specifying data storage locations in the network data storage for storing data of the file. The client receives the metadata, and uses the metadata to produce at least one data access command for accessing the data storage locations in the network storage. The client sends the data access command to the network data storage to read or write data to the file. For a write operation, the client may modify the metadata. When the client is finished writing to the file, the client returns any modified metadata to the file server.

One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

The invention provides a distributed storage system and method based on a data arbiter copy and used for online distributed data storage. The method comprises the following steps that: S1, the distributed storage system receives a data write-in operation request; S2, the distributed storage system starts data write-in operation after receiving the data write-in operation request and synchronously writes the written data into a data copy storage module; S3, the data write-in operation of the data copy storage module is completed, and the data copy storage module directly returns writing operation confirmation information; S4, a data arbiter copy module continuously and asynchronously write in data from the data copy storage module, and a complete data arbitration information backup used for data migration and restoration is carried out; and S5, the write-in operation of the data arbiter copy module is completed, and asynchronous writing operation confirmation information is returned. The distributed storage system and method solve the problems in the prior art that an existing distributed storage system has a relatively small effectively storage space, is low in reading and writing efficiency and has difficulty in data restoration, and a conventional double-copy storage method leads to a brain-split phenomenon.

Differential uncloneable variability-based cryptography techniques are provided. The differential cryptography includes a hardware based public physically uncloneable function (PPUF) to perform the cryptography. The PPUF includes a first physically uncloneable function (PUF) and a second physically uncloneable function. An arbiter determines the output of the circuit using the outputs of the first and second PUFs. Cryptography can be performed by simulating the PPUF with selected input. The output of the simulation, along with timing information about a set of inputs from where the corresponding input is randomly selected for simulation, is used by the communicating party that has the integrated circuit with the PPUF to search for an input that produces the output. The input can be configured to be the secret key or a part of the secret key.

The invention is a kind of multi-processor system and the method for sharing guiding model, which refers to multi-CPU system with PCI controller in communication field. The system includes several processors, each processor has matched control state register, dynamic RAM, static RAM, series port, the processors are connected together through PCI bus, and uses a PCI arbiter, one processor with the guiding model is uses as the primary processor, the other processors are used as slave processors. When powdered on, the primary CPU takes instruction form itself guiding model, and the slave processor acquires instruction from RAM, the primary CPU resets the slave CPUs after initializing them, now, it can run. The invention is simple; it can save the guiding model, and the Ethernet controller.

A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.

The invention discloses a crypto chip system and a secret key extraction method. The system comprises a public key crypto engine, a symmetry crypto engine, a HASH engine, a one-way function engine, a nonvolatile memory, an execution engine, t secret key assistant management parties and a double-arbiter physical unclonable function module DAPUF. The other purpose of the invention aims at providing a secret key extraction method of the crypto chip system. The method comprises the steps of (1) a secret key generation stage, and (2) a secret key reconstruction stage. According to the invention, an effective bit is selected by an exclusive-or result of the DAPUF, and in combination with the steps and under a condition that multiple challenge/response characteristics are provided, the system and the method enable the obtained response to have the characteristics of no 01 deviation on probability, reliable reconstruction certainty, low average time complexity, small challenge and response redundancy, physical invasion attack sensation and the like.

A scalable OCN for supporting an application using processing elements integrated in an IC including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet comprising one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.

The invention discloses a physical unclonable function circuit structure based on double delay chains. The physical unclonable function circuit structure comprises a rising edge generator, challenge generators, a delay chain D1, a delay chain D2 and an arbiter. The signal output end of the rising edge generator is respectively connected with the signal input end of the delay chain D1 and the signal input end of the delay chain D2, the signal output end of the delay chain D1 and the signal output end of the delay chain D2 are connected with the signal input end of the arbiter, the delay chain D1and the delay chain D2 are respectively formed by connecting N delay nodes, each delay node is provided with a challenge position used for adjusting delay time of input signals, and each challenge position is connected with the corresponding challenge generator which generates a random challenge value for the challenge position. The physical unclonable function circuit structure has the advantages that the same circuit structure is adopted for the delay chain D1and the delay chain D2, the same transmission signals and challenge values are input, but the two delay chains are isolated from each other without any intersection or connection, and if large fixed delay difference exists between the two delay chains, the delay difference can be balanced by setting the challenge values of all the delay nodes.

The present invention discloses a scientific computation-oriented high performance DMA (Direct Memory Access) part in a GPDSP (General-Purpose Digital Signal Processor). The scientific computation oriented high performance DMA part comprises: a host portion for completing read/write request calculation according to a configured transmission parameter, and comprising a logical channel controller and two general physical channels; a slave computer portion for simultaneously providing a channel for the DMA to return out-of-kernel storage volume data read by the host to an in-kernel storage volume and providing a channel for a out-of-kernel device to read/write the in-kernel storage volume, and comprising an FIFO (First In, First Out) for buffering a out-of-kernel read/write request, a special channel arbiter, a matrix transpose module, a read/write AM special channel and a read/write SM special channel, wherein when an in-kernel request flows out of the read/write request FIFO, the special channel arbiter sends the request to different modules according to a mark signal and a target address of a request packet; and a bus controller, wherein both the host portion and the slave computer portion are connected to the bus controller. The scientific computation-oriented high performance DMA part in the GPDSP provided by the present invention has the advantages of supporting multiple types of transmission modes, improving the data transmission speed, improving the program execution efficiency and the like.

A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

In a system for the regulation of information trains for packet switches, there is provided one queue per path in each input module liable to be driven by an arbitrator placed in each of the output modules bearing these channels.

The invention relates to an arbitration control method, a communication method using the arbitration control method, an arbitrator and a communication system using the arbitrator. The arbitration control method comprises the following steps of: sequencing communication requests, wherein the sequencing is related to the link distance and submission time of the communication requests; screening the sequenced communication requests and submitting the screened communication requests; arbitrating the communication requests according to the types of the submitted communication requests and returning an arbitration failure response or arbitration success response; and updating a link record and a credit record according to the arbitration response. By the centralized management and allocation of credit and links of communication resources, the arbitration process is simplified, the streamline arbitration capability is improved and the communication efficiency of the links is increased.

An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.

An apparatus or method integrates device policy and network policy in order to arbitrate a priority between packet data applications or services for a data connection. In response to a request, a data connection to a wireless network is established for a first application of a first type of application or service if no data session is in progress or if a second application of a second type of application or service can share an existing data session. A hybrid arbitrator performs hybrid arbitration between the first application and the second application in response to determining that the first type and the second type cannot share the existing data session, either based upon a network policy that specifies a difference in priority between the first type and the second type, or based upon a device policy if the network policy does not specify a difference in priority.