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Multiprocessor system and method for sharing bootstrap module thereof

A technology of a multi-processor system and a guiding module, which is applied in the fields of electrical digital data processing, instruments, and a combination of various digital computers, can solve the problems of complex processing of RAM devices, and achieves a simple method, considerable economic benefits, and saves Ethernet control. effect of the device

Inactive Publication Date: 2004-09-01
ZTE CORP
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A patent application document "System of connecting multiple processors in cascade" (serial multiprocessor connection system) retrieved from the United States Trademark and Patent Office with the application number 20020138156 involves the startup of multiple systems, which utilizes serial bootStrap (Bootstrap) bus to complete the transmission of the startup code of each CPU subsystem of the multi-CPU system, but this method needs to design a set of bootStrap bus on the hardware, and the processing of the RAM devices of each CPU system is also more complicated.

Method used

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  • Multiprocessor system and method for sharing bootstrap module thereof
  • Multiprocessor system and method for sharing bootstrap module thereof
  • Multiprocessor system and method for sharing bootstrap module thereof

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Embodiment Construction

[0029] In the system of the present invention, the main CPU has BOOT FLASH, but the slave CPU does not have BOOT FLASH. All CPUs are connected together through the PCI bus and share a PCI arbiter. When the system is powered on, the main CPU fetches instructions from its own BOOT FLASH, and the slave CPU fetches instructions from RAM, but at this time the obtained instructions are illegal and cannot run, but after the master CPU initializes the slave CPU, it will let it Reset, at which point it operates normally.

[0030] The core of the present invention is to utilize a kind of soft reset to make the slave CPU fetch instructions from the RAM without performing other operations. Using this feature, after the system is powered on or the main CPU is reset, the main CPU configures the PCI space of the slave CPU, and the various control status registers CSR (Controll Status Registers), DRAM, SRAM, etc. inside the slave CPU system, The PCI controller is mapped to the main CPU, so ...

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Abstract

The invention is a kind of multi-processor system and the method for sharing guiding model, which refers to multi-CPU system with PCI controller in communication field. The system includes several processors, each processor has matched control state register, dynamic RAM, static RAM, series port, the processors are connected together through PCI bus, and uses a PCI arbiter, one processor with the guiding model is uses as the primary processor, the other processors are used as slave processors. When powdered on, the primary CPU takes instruction form itself guiding model, and the slave processor acquires instruction from RAM, the primary CPU resets the slave CPUs after initializing them, now, it can run. The invention is simple; it can save the guiding model, and the Ethernet controller.

Description

technical field [0001] The present invention relates to a kind of multiprocessor (CPU) system and the method for multi-CPU system sharing BOOT FLASH (guide module), relate in particular to the multi-CPU system and The method for multiple CPUs to share the boot module in the system. Background technique [0002] At present, in order to increase the processing capacity and integration of single boards in embedded systems, multiple sets of CPU systems are often designed on the same single board. Each system comes with a BOOT FLASH, and often uses PCI controllers. CPLD (Complex Programmable Logic Device, Complex Programmable Logic Device) designs a PCI arbiter by itself, and downloads the version file from the network port or FLASH. Such as figure 1 and image 3 shown. figure 1 It is a hardware principle block diagram of a multi-CPU system designed according to the prior art method. In the system, two or more sets of CPU systems each have a BOOT FLASH, a PCI arbiter, and at ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/14G06F15/16
Inventor 赵凯陈诗军苏绣江黄钟琪
Owner ZTE CORP
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