208 results about "Complex programmable logic device" patented technology

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

The invention provides a PCIe equipment fault monitoring and dynamic processing method based on intelligent prediction, and the method comprises the steps: obtaining operation parameters from a BMC (baseboard management controller), an operation system and a PCIe equipment register, carrying out the processing and time sequence feature extraction, and inputting a lightweight long short-term memory network LSTM model deployed in the BMC for fault probability prediction. And combining the prediction result and the operation parameters to calculate an equipment health score, and triggering an alarm, bandwidth degradation or hardware isolation operation according to the score. And the hardware isolation module sends a control instruction to the complex programmable logic device CPLD through the IC bus to realize non-interruption power-off isolation of the target equipment. And uploading real-time data to a cloud server through encryption communication, executing fine adjustment of the model, and returning an update weight to realize continuous optimization and version control of the model. The method can be widely applied to computing equipment such as a server, and the availability and the fault-tolerant capability of the system are improved.

The invention relates to a PCB over-temperature protection device, method and equipment, and relates to the technical field of servers, the device comprises at least one control circuit and a complex programmable logic device CPLD, and the control circuit comprises a thermistor and at least one voltage comparator; the thermistor is arranged in a monitoring area of a printed circuit board (PCB) and is used for converting the temperature of the monitoring area into a target voltage signal; the forward input end of the voltage comparator receives a target voltage signal, the reverse input end of the voltage comparator receives a reference voltage signal corresponding to the voltage comparator, and the voltage comparator is used for outputting a high level when the target voltage signal is higher than the reference voltage signal; the CPLD comprises a plurality of input pins respectively corresponding to the voltage comparators, each input pin is electrically connected with the output end of the corresponding voltage comparator, and the CPLD is used for triggering over-temperature protection operation corresponding to the input pin when the high level is received through the input pin, so that the timeliness of PCB over-temperature protection is improved.

The embodiments of the present application provide a method and apparatus for monitoring a hardware partition of a server host system. The method comprises: determining a target partition management system on a baseboard management controller, wherein the target partition management system is any partition management system among a plurality of partition management systems divided on the baseboard management controller; selecting, for the target partition management system, a target link unit among a plurality of link units divided on a complex programmable logic device, wherein the target link unit is configured to connect the target partition management system and a target hardware partition among a plurality of hardware partitions divided on the server host system; and monitoring the running of the target hardware partition by means of the target partition management system and the target link unit. The present application improves the running monitoring efficiency of a server. The present application relates to the field of computers.

The invention discloses a multi-channel transceiving integrated system based on an RFSOC (Radio Frequency System On Chip) and a radio frequency SIP (Session Initiation Protocol). The multi-channel transceiving integrated system comprises an RFSOC system, a multi-channel clock synchronization module, a radio frequency SIP system and a power supply network, the RFSOC system comprises a control sampling module, a storage module and an optical fiber module, the control sampling module comprises a plurality of RFSOC chips, a CPLD (Complex Programmable Logic Device) chip and a main control chip, and the RFSOC chips are used for processing intermediate frequency signals and realizing data interaction with the optical fiber module; the CPLD chip is used for enabling a power supply network; the main control chip is used for performing control coordination among the plurality of RFSOC chips; the storage module is used for realizing program solidification of the RFSOC system; the optical fiber module is used for realizing high-speed transmission of broadband receiving data; the multi-channel clock synchronization module is used for providing a clock reference of the whole system; the radio frequency SIP system comprises a radio frequency SIP module, a Balun network and a local oscillator power division amplification module. The radio frequency SIP module realizes receiving, transmitting and processing of multi-channel radio frequency signals. According to the invention, a multi-channel transmit-receive integrated system with high integration, large bandwidth and miniaturization can be realized.

The invention relates to a method and a device for intelligently identifying server configuration and adaptively configuring PCIe (Peripheral Component Interconnect Express) bandwidth. The method comprises the following steps of: configuring a wiring mode of an I / O (Input / Output) expander in each server expansion card connected with a server mainboard and an onboard PCIe slot; starting a server power supply, and after the substrate management controller is initialized, acquiring a register value of an I / O expander on each server expansion card through an IIC communication protocol; the substrate management controller sends register values of all the I / O expanders to the complex programmable logic device; the complex programmable logic device sends register values of all the I / O expanders to a central processing unit of a server through a vGPIO communication protocol; and based on the register value of the I / O expander, the basic input / output system allocates bandwidth and resources to the onboard PCIE slot in each server expansion card. According to the method, the number of the universal server board cards can be reduced, the PCIe bandwidth can be adaptively configured, and the error probability is reduced.

The invention discloses a server, and relates to the field of computers, the server comprises a substrate management controller, a server interface and a plurality of server hardware, the substrate management controller comprises a link controller and a plurality of transmitters, the plurality of transmitters are connected with the plurality of server hardware in a one-to-one correspondence manner, and the server interface is connected with the link controller; the link controller is used for detecting current to-be-controlled target server hardware from a target control request currently received by the server interface and controlling a target transmitter in the plurality of transmitters to construct a communication link with the server interface; and the target transmitter in the plurality of transmitters is used for acquiring the target control request from the server interface through the communication link and transmitting the target control request to the target server hardware, thereby solving the technical problems of high dependency degree of the control process of the server hardware on the complex programmable logic device and the like.

The present application provides a complex programmable logic device (CPLD)-based data processing method and system, and a computing device. The CPLD is arranged on a hard disk backplane of a server, and the hard disk backplane supports a universal backplane management (UBM) protocol; the hard disk backplane comprises an HFC connector for connecting to a RAID controller and a DFC connector for connecting to a hard disk slot, and the CPLD is connected to the HFC connector and the DFC connector, respectively. The method comprises: when a hard disk is inserted into the hard disk slot, determining an interface type of the hard disk according to a signal level transmitted by the DFC; processing interaction data between the RAID controller and the hard disk according to the hard disk interface type, wherein the interaction data comprises data indicating the hard disk interface type, data indicating a hard disk state and read / write operation command data; and transmitting the processed data to the RAID controller or the hard disk so as to achieve hard disk management, wherein the hard disk comprises a hard disk of an SAS / SATA / NVME interface type. In this way, new logic functionality is added to an existing logic chip of the hard disk backplane to achieve the functionality of the UBM protocol.

The invention provides a system and a method for automatically identifying OCP network card bandwidth. According to the system for automatically identifying the bandwidth of the OCP network card, dynamic bandwidth allocation is achieved through cooperation of the multiple computing nodes, the CPLD and the OCP network card, each computing node is connected with a connector on the side of the OCP network card through a certain x8 MCIO connector in a set of x8 MCIO connectors, each computing node distinguishes the node identity through differential voltage configuration of a reserved detection pin, and therefore the bandwidth of the OCP network card can be automatically identified. And the CPLD acquires node identity detection signals to judge an access mode, determines a bandwidth allocation strategy by combining with the slot in-place detection signal group, generates a bandwidth configuration control signal group according to the bandwidth allocation strategy, and feeds back the bandwidth configuration control signal group to the OCP network card. According to the system, the OCP network card bandwidth identification and distribution are carried out by using hardware, and the application of OCP network cards with different bandwidths in various access modes can be dealt with only through a CPLD (Complex Programmable Logic Device) under the condition that firmware of each hardware is not frequently replaced.

The invention discloses a data communication method, a data communication device, data communication equipment and a medium, relates to the technical field of computers, and is applied to a complex programmable logic device which communicates with a south bridge chip in a preset type server and an external target substrate management controller chip through a simplified pin bus. Comprising the steps that target data sent by a south bridge chip is transmitted to a target substrate management controller chip, and after a TAR signal is monitored, a first synchronous communication signal fed back by the target substrate management controller chip is acquired; converting the first synchronous communication signal into a second synchronous communication signal; and transmitting the second synchronous communication signal to a south bridge chip, so that the south bridge chip communicates with the target substrate management controller chip based on the simplified pin bus after executing the preset short-time waiting operation. According to the application, the communication between the preset type server and the target substrate management controller chip based on the simplified pin bus is realized by connecting the complex programmable logic device in series.

A system, method, apparatus and device for adjusting power consumption, and a medium are provided. The system includes a Power Supply Unit (PSU) and a Complex Programmable Logic Device (CPLD). An input end of the PSU is connected to a server, and the PSU is configured to receive an initial electrical signal of the server in real time, and determine a current power supply condition according to the initial electrical signal to obtain a final electrical signal. The CPLD is connected to an output end of the PSU, and the CPLD is configured to receive the final electrical signal, increase a power of the server when the final electrical signal is a signal representing that the current power supply condition is high output power, and decrease the power of the server when the final electrical signal is a signal representing that the current power supply condition is low output power.

The invention discloses a method for solving conflict between a baseboard management controller (BMC) and a central processing unit (CPU) accessing a real-time clock (RTC), which relates to the technical field of computer firmware, and comprises the following steps: before a central processing unit (CPU) of a server accesses the RTC, a first signal representing that the CPU accesses the RTC is transmitted to the BMC through a complex programmable logic device (CPLD); the information indicating that the RTC is occupied by the CPU is notified to the BMC; after the CPU transmits the first signal representing that the CPU accesses the RTC to the BMC, the CPU accesses the RTC through a hardware link between the CPU and the RTC, wherein the hardware link is controlled by the BMC and the CPLD to be communicated with the CPU and the RTC; and before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first signal representing that the CPU accesses the RTC, and delays accessing the RTC when determining that the CPU accesses the RTC so as to eliminate access conflicts. In the invention, the BMC and the CPU do not access the RTC at the same time, and time abnormity caused by access conflicts can be eliminated.

A mainboard protection system and method are provided. A precision resistor is arranged between an overcurrent protection component and a voltage regulator, and the precision resistor is connected to a current monitoring circuit. The current monitoring circuit is connected to a complex programmable logic device, and transmits, w detecting that a voltage difference of the precision resistor is greater than a set threshold, an early-warning signal to the complex programmable logic device. The complex programmable logic device is connected to a processor and sends, when receiving the early-warning signal, an interrupt signal to the processor. in response to receiving the interrupt signal, the processor cuts off outputting of the overcurrent protection component.

The invention provides a CPLD (Complex Programmable Logic Device) configuration information power-on loading method and system based on dynamic voltage regulation in the technical field of CPLD management. The method comprises the following steps: S1, generating an offset sub-address of each byte data in configuration information by a CPU (Central Processing Unit) based on an offset address; s2, sending a protection identifier, the first byte data and a corresponding offset sub-address to an I2C slave controller, and respectively writing the protection identifier, the first byte data and the corresponding offset sub-address into a protection register, a data register and an address register; s3, after the logic controller verifies the protection identifier written in the protection register, controlling the I2C main controller to read the byte data and the offset sub-address from the corresponding register so as to write the byte data into the EEPROM based on the offset sub-address, and executing the writing of the next byte data until all the writing is completed; and S4, when the CPLD is powered on, the I2C main controller automatically loads the byte data stored in the EEPROM to the configuration register. The CPLD configuration information loading method has the advantages that the convenience, flexibility, safety and reliability of CPLD configuration information loading are greatly improved.

A programmable logic device, and a server, which relate to the technical field of chip upgrading. A stage of second multi-path selection switch MUX2 is added before a first multi-path selection switch MUX0 between a complex programmable logic device (CPLD) and a platform controller hub (PCH) flash, in order to establish a hardware path between a baseboard management controller (BMC) and the PCH flash; moreover, a stage of third multi-path selection switch MUX3 is added before a fourth multi-path selection switch MUX1 between the CPLD and a BMC flash, in order to establish a hardware path between the PCH and a BMC chip, i.e., the BMC flash. Thus, a selection signal at the second multi-path selection switch MUX2 and the third multi-path selection switch MUX3 is realized, and the selection signal can be sent to the CPLD so as to complete the switching of a selection path. Therefore, during an upgrading process for BMC / PCH FW, the security of upgrading firmware is ensured, and hardware support is also provided for simplifying the upgrading process.

The invention provides a fan control method and a related device, which can improve the reliability of a heat dissipation system and guarantee the heat dissipation effect of electronic equipment. The fan control method can be applied to the heat dissipation system, the heat dissipation system comprises a baseboard management controller (BMC) and a complex programmable logic device (CPLD), and the BMC comprises a first process and a second process. The method comprises the steps that a first process generates a first rotating speed control parameter and provides the first rotating speed control parameter to a second process; the second process responds to the received first rotating speed control parameter and provides the first rotating speed control parameter for the CPLD; and the second process generates a second rotating speed control parameter in response to the fact that the first process does not work, and provides the second rotating speed control parameter for the CPLD.

The invention provides a communication system and a communication method used between multiple nodes and I2C equipment, and relates to the technical field of servers. The system is arranged in I2C equipment and comprises a CPLD (Complex Programmable Logic Device) module, a multiplexing switch module and a plurality of connectors, and the connectors are connected with a BMC (Baseboard Management Controller) and the CPLD module of a node to form a direct connection channel of the BMC and the CPLD; the multiplexing switch module is connected with the CPLD module, and the connector is also connected with I2C equipment through the multiplexing switch module; the CPLD module receives a permission request instruction of a multi-node BMC to an I2C bus through a direct connection channel, generates a channel selection instruction for indicating to gate a channel between a target BMC and I2C equipment, and sends the instruction to the multiplexing switch module; and the multiplexing switch module only gates the communication connection between the target BMC and the I2C equipment based on the instruction, so that the problem of I2C bus abnormity caused by communication arbitration of a plurality of BMCs is effectively avoided.

The present application relates to a control method and system for a baseboard management controller of a node server, and a complex programmable logic device. The method comprises: detecting a signal sent by a watchdog timer of a baseboard management controller, and if it is detected that the signal sent by the watchdog timer is a non-square wave signal, restarting the baseboard management controller; and when a remote reset signal of the baseboard management controller sent by a network interface card is received, identifying whether the baseboard management controller needs to be restarted or not, and if yes, restarting the baseboard management controller. According to the method, when it is automatically detected that the baseboard management controller of the node server goes wrong, the baseboard management controller is restarted, and a remote reset signal sent remotely is received, so that the baseboard management controller works normally by remotely restarting the baseboard management controller when the baseboard management controller fails.

A liquid leakage detection circuit, comprising a sensing line anomaly detection trigger sub-circuit and a liquid leakage detection sub-circuit; are connected by a liquid leakage sensing line, wherein the sensing line anomaly detection trigger sub-circuit is configured to be conducted according to a liquid leakage simulation signal generated by a complex programmable logic device, so as to perform anomaly detection on the liquid leakage sensing line by the liquid leakage detection sub-circuit; and the liquid leakage detection sub-circuit is configured to perform anomaly detection on the liquid leakage sensing line according to a change condition of an input voltage when it is determined that the sensing line anomaly detection trigger sub-circuit is conducted, and to perform liquid leakage detection after it is determined that the liquid leakage sensing line has no anomaly condition.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The invention belongs to the technical field of FPGA (Field Programmable Gate Array) peripheral configuration, and discloses a CPLD (Complex Programmable Logic Device)-based SelectMAP configuration mode implementation method and system. The method comprises the following steps: electrifying equipment; clearing the configuration register; a sampling configuration mode pin; a mode is configured for the SelectMAP synchronously; checking the ID of the equipment; loading the configuration data; performing CRC (cyclic redundancy check); starting a sequence; and the SalveSelectMAP configuration control module at the CPLD end is used for pre-storing bit stream configuration data into FIFO (First In First Out) when the configuration data is valid, and then configuring the bit stream configuration data into an FPGA-K7 through a SelectMAP interface by matching with a configuration clock generated by the SalveSelectMAP configuration control module. According to the invention, a high-performance configuration data transmission channel is realized. The configuration scheme has the characteristics of simplicity in development, low configuration cost, high speed and flexibility in use, and has very high practicability.

The invention provides a method for modifying server hardware configuration, which relates to the technical field of computers, and comprises the following steps: reading a hardware configuration table from an EEPROM (Electrically Erasable Programmable Read-Only Memory) through a CPLD (Complex Programmable Logic Device) and The CPLD analyzes the hardware configuration table after passing the verification, and starts or disables the corresponding hardware module according to the hardware configuration information; receiving a configuration updating instruction through the BMC, switching an I2C channel to connect the BMC and the EEPROM after the target hardware configuration table passes the verification, and writing the target hardware configuration table into the EEPROM; and after writing is completed, the connection between the CPLD and the EEPROM is recovered, and hardware configuration updating is completed. The technical problems that in the prior art, hardware configuration management depends on manual operation and firmware adjustment, so that configuration updating is inconvenient, and hardware module control is limited are solved, and the technical effect of improving the flexibility and accuracy of server hardware configuration management and the overall stability is achieved.

The invention discloses a universal single event lock-in effect protection circuit with adjustable multi-channel lock-in current threshold values, and belongs to the field of single event lock-in protection. The circuit comprises a switching circuit, a current monitoring and converting circuit, a voltage comparison circuit, a CPLD (Complex Programmable Logic Device) execution circuit, an MCU (Microprogrammed Control Unit) control circuit and a locking current threshold setting circuit, a locking protection threshold of current can be preset, and any locking threshold current setting can be realized even if the protection circuit is in hardware connection with a load device. Meanwhile, multiple paths of real-time current and voltage can be monitored, and when one path or multiple paths of current reach a locking threshold value, any path or multiple paths of voltage can be cut off, single event locking effect protection is completed, and a load device is protected.

A dual system server includes: a central processing unit, a first baseboard management controller, a second baseboard management controller and a complex programmable logic device. The first baseboard management controller is connected to the central processing unit through a first peripheral component interconnect express interface. The second baseboard management controller is connected to the central processing unit through a second peripheral component interconnect express interface. The complex programmable logic device is connected to the first baseboard management controller through a first inter-integrated circuit interface, and is connected to the second baseboard management controller through a second inter-integrated circuit interface.

The invention discloses a controller communication system and method, a computer product, equipment and a storage medium, and relates to the technical field of controller communication, and the controller communication system comprises a first controller which is provided with a first processor and a first complex programmable logic device; the second controller is provided with a second processor and a second complex programmable logic device; the first processor is connected with the first complex programmable logic device through a first connecting line, the first complex programmable logic device is connected with the second complex programmable logic device through a second connecting line, and the second complex programmable logic device is connected with the second processor through a third connecting line. A plurality of pins are arranged on the complex programmable logic device; and according to different target fault information types and a link formed by the plurality of pins and the plurality of connection lines corresponding to the different target fault information types, fault information transmission between the controllers is realized. The technical problem of low service switching efficiency between the controllers is solved, and the communication efficiency of the controllers can be improved.

An abnormality detection method, device, host device, system and storage medium, the method comprises: shielding all channels in an I2C (Inter-Integrated Circuit) multiplexer, and detecting an I2C controller by using a CPLD (Complex Programmable logic device) to obtain a first detection result; when the first detection result is that the I2C controller is normal, controlling the I2C controller to detect the I2C multiplexer to obtain a second detection result; when the second detection result is that the I2C multiplexer is normal, opening the channels, and controlling the I2C controller to detect an I2C slave device connected to each channel to obtain a third detection result; when the third detection result is that the I2C slave device is normal, exiting detection; when there is an abnormal result in the first detection result, the second detection result and the third detection result, outputting an alarm information corresponding to the abnormal result.

The invention discloses a communication device, a communication control method, an electronic device, a medium and a program product, and relates to the technical field of communication, by adopting the technical scheme provided by the invention, a target physical layer device is directly connected to a first multiplexer instead of being directly connected to a complex programmable logic device serving as a control element, so that the communication efficiency is improved. Therefore, when a plurality of physical layer devices need to be managed, a large number of MDIO pins do not need to be arranged on the control element so as to support switching control of MDIO signals. Therefore, the technical problem of shortage of pin resources and logic unit resources faced by a complex programmable logic device can be solved, and the technical effects of remarkably reducing the system cost and facilitating commercial application of products are achieved.

Systems and methods for secure modular hardware binding in a Data Center Modular Hardware System (DC-SCM) environment are described herein. According to one embodiment, an Information Handling System (IHS) includes multiple Complex Programmable Logic Devices (CPLDs), and computer-executable logic to, for each of the CPLDs: store an encrypted secret key in a platform Root-of-Trust (ROT) and the CPLD, and receive, by the platform ROT, a request to authenticate a firmware stack installed on the CPLD. The logic may then present, by the CPLD, an encrypted secret key to the platform ROT, authenticate, by the platform ROT, the firmware stack by comparing the encrypted secret key received from the CPLD with its stored version of the encrypted secret key, and allow operation of the CPLD based on the authentication.

The SGPIO multi-path expansion circuit provided by the embodiment of the utility model comprises a mainboard management controller BMC and at least two complex programmable logic devices CPLDs connected with the BMC in series, each CPLD comprises an SGPIO slave node Slave and a first multiplexer MUX connected with the SGPIO slave node Slave, an output interface of the BMC is connected with the SGPIO slave node Slave in each CPLD, and an output interface of the BMC is connected with the first multiplexer MUX. Different SGPIO Slaves are configured to analyze signals of preset storage space digits in first signals transmitted by the output interface of the BMC. According to the technical scheme, the SGPIO Slave in the CPLD receives the signals transmitted by the output interface of the BMC, then the SGPIO Slave only analyzes the signals with the preset storage space bits in the first signals, and then the unanalyzed signal data is transmitted to the next CPLD to be analyzed, so that logic resources consumed by the CPLD are reduced, and the real-time performance of data transmission is improved.

The invention relates to the technical field of servers, in particular to a hard disk alarm method and device of a server, the server and a medium, the method is applied to a substrate management controller in the server, and the server further comprises a backboard and a plurality of hard disks; a complex programmable logic device is arranged on the back plate; the complex programmable logic device and the backboard are connected with the substrate management controller. The method comprises the following steps: reading a target hard disk in-place signal of the complex programmable logic device, wherein the target hard disk is any one of a plurality of hard disks; reading the hard disk state of the target hard disk; determining whether the target hard disk is a fault hard disk according to the in-place signal and the hard disk state of the target hard disk; if the target hard disk is the fault hard disk, alarm information of the target hard disk is output, and the alarm information is used for fault alarm of the target hard disk; the problem that the substrate management controller can still give an alarm under the condition that the card end of the redundant array of independent disks of the hard disk is not recognized is solved, and the accuracy of determining the faulty hard disk is improved.