96 results about "Complex programmable logic device" patented technology

The present application provides a complex programmable logic device (CPLD)-based data processing method and system, and a computing device. The CPLD is arranged on a hard disk backplane of a server, and the hard disk backplane supports a universal backplane management (UBM) protocol; the hard disk backplane comprises an HFC connector for connecting to a RAID controller and a DFC connector for connecting to a hard disk slot, and the CPLD is connected to the HFC connector and the DFC connector, respectively. The method comprises: when a hard disk is inserted into the hard disk slot, determining an interface type of the hard disk according to a signal level transmitted by the DFC; processing interaction data between the RAID controller and the hard disk according to the hard disk interface type, wherein the interaction data comprises data indicating the hard disk interface type, data indicating a hard disk state and read / write operation command data; and transmitting the processed data to the RAID controller or the hard disk so as to achieve hard disk management, wherein the hard disk comprises a hard disk of an SAS / SATA / NVME interface type. In this way, new logic functionality is added to an existing logic chip of the hard disk backplane to achieve the functionality of the UBM protocol.

The invention provides a communication system and a communication method used between multiple nodes and I2C equipment, and relates to the technical field of servers. The system is arranged in I2C equipment and comprises a CPLD (Complex Programmable Logic Device) module, a multiplexing switch module and a plurality of connectors, and the connectors are connected with a BMC (Baseboard Management Controller) and the CPLD module of a node to form a direct connection channel of the BMC and the CPLD; the multiplexing switch module is connected with the CPLD module, and the connector is also connected with I2C equipment through the multiplexing switch module; the CPLD module receives a permission request instruction of a multi-node BMC to an I2C bus through a direct connection channel, generates a channel selection instruction for indicating to gate a channel between a target BMC and I2C equipment, and sends the instruction to the multiplexing switch module; and the multiplexing switch module only gates the communication connection between the target BMC and the I2C equipment based on the instruction, so that the problem of I2C bus abnormity caused by communication arbitration of a plurality of BMCs is effectively avoided.

A liquid leakage detection circuit, comprising a sensing line anomaly detection trigger sub-circuit and a liquid leakage detection sub-circuit; are connected by a liquid leakage sensing line, wherein the sensing line anomaly detection trigger sub-circuit is configured to be conducted according to a liquid leakage simulation signal generated by a complex programmable logic device, so as to perform anomaly detection on the liquid leakage sensing line by the liquid leakage detection sub-circuit; and the liquid leakage detection sub-circuit is configured to perform anomaly detection on the liquid leakage sensing line according to a change condition of an input voltage when it is determined that the sensing line anomaly detection trigger sub-circuit is conducted, and to perform liquid leakage detection after it is determined that the liquid leakage sensing line has no anomaly condition.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The SGPIO multi-path expansion circuit provided by the embodiment of the utility model comprises a mainboard management controller BMC and at least two complex programmable logic devices CPLDs connected with the BMC in series, each CPLD comprises an SGPIO slave node Slave and a first multiplexer MUX connected with the SGPIO slave node Slave, an output interface of the BMC is connected with the SGPIO slave node Slave in each CPLD, and an output interface of the BMC is connected with the first multiplexer MUX. Different SGPIO Slaves are configured to analyze signals of preset storage space digits in first signals transmitted by the output interface of the BMC. According to the technical scheme, the SGPIO Slave in the CPLD receives the signals transmitted by the output interface of the BMC, then the SGPIO Slave only analyzes the signals with the preset storage space bits in the first signals, and then the unanalyzed signal data is transmitted to the next CPLD to be analyzed, so that logic resources consumed by the CPLD are reduced, and the real-time performance of data transmission is improved.

The invention relates to the technical field of servers, in particular to a hard disk alarm method and device of a server, the server and a medium, the method is applied to a substrate management controller in the server, and the server further comprises a backboard and a plurality of hard disks; a complex programmable logic device is arranged on the back plate; the complex programmable logic device and the backboard are connected with the substrate management controller. The method comprises the following steps: reading a target hard disk in-place signal of the complex programmable logic device, wherein the target hard disk is any one of a plurality of hard disks; reading the hard disk state of the target hard disk; determining whether the target hard disk is a fault hard disk according to the in-place signal and the hard disk state of the target hard disk; if the target hard disk is the fault hard disk, alarm information of the target hard disk is output, and the alarm information is used for fault alarm of the target hard disk; the problem that the substrate management controller can still give an alarm under the condition that the card end of the redundant array of independent disks of the hard disk is not recognized is solved, and the accuracy of determining the faulty hard disk is improved.

The present application relates to the technical field of hanging debugging, and discloses a debugging method, device and equipment for a hanging management engine and a storage medium, which are applied to a baseboard management controller, wherein the baseboard management controller, a complex programmable logic device and a platform path controller are communicatively connected in pairs; the method comprises the following steps: when an abnormal state of the management engine is detected, obtaining state information of the platform path controller; the abnormal state information of the abnormal state is obtained by communication between the complex programmable logic device and the platform path controller and is sent to the baseboard management controller; based on the state information, the management engine is debugged to determine the abnormal source of the management engine. In this way, when the management engine is in an abnormal state, the state information of the platform path controller is obtained to debug the management engine and determine the abnormal source of the management engine, thereby improving the timeliness and completeness of the relevant debugging information obtained when the management engine is hanging, and thus the debugging efficiency of the hanging management engine is improved.

The application relates to the technical field of servers and discloses a method for acquiring network card information, a server board card, equipment and a medium, the method for acquiring network card information comprises the following steps: outputting a clock signal and a data loading enable signal to a network card through a complex programmable logic device, and reading a data signal sent by the network card by using the clock signal and the loading enable signal; processing the data signal sent by the network card through the complex programmable logic device, generating internal register data, and transmitting the internal register data to a baseboard management controller; and updating a log file based on the internal register data through the baseboard management controller; wherein the log file stores the data signal sent by the network card. The application enriches the read data signal sent by the network card, increases the flexibility and practicality of network card management, and reduces the difficulty of network card problem processing.

The invention relates to a hard disk control system and method. The hard disk control method is executed by a complex programmable logic device, and comprises the following steps: detecting a first voltage of a first data line connected with a first node and a second voltage of a second data line connected with a second node under the triggering of a management instruction, and judging at least one of the first node and the second node as a target node according to the first voltage and the second voltage, reading a pre-stored mapping table corresponding to the target node, judging a target hard disk address according to the pre-stored mapping table and the target logic address, and controlling a hard disk corresponding to the target hard disk address according to the target operation.

The invention relates to a current-limiting protection method and system for a controller, belongs to the technical field of controllers, and solves the problems of complex control, inflexibility, low efficiency and higher cost caused by the need of adding an additional CPLD (Complex Programmable Logic Device) chip or selecting a main control chip with a CBC mode function in the existing current-limiting method. Comprising the following steps: in the working process of a controller, continuously detecting a hardware overcurrent signal of the controller; if the hardware overcurrent signal is detected to be effective, triggering an interrupt service program; and the interrupt service program carries out overcurrent control on the controller and outputs an overcurrent fault signal, if the overcurrent fault signal is effective, the interrupt service program enters a fault mode, and otherwise, the interrupt service program continues to wait for triggering.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The invention relates to the technical field of server design, and discloses a GPIO (General Purpose Input / Output) resource operation method and system, a server and a computer readable storage medium, the method is applied to the server, and the method comprises the following steps: obtaining target pin information and operation information through a baseboard management controller, and searching a preset register mapping table on the GPIO subsystem according to the target pin information to obtain a target register address, and operating GPIO resources of the complex programmable logic device by the substrate management controller according to the target register address and the operation information. By means of the mode, GPIO resource operation on the server is more convenient, hardware and the application program can be decoupled, even if the pins change due to subsequent hardware updating, the application program does not need to be modified as long as the information of the pins achieving the same function is the same, and the user experience is improved. And the substrate management controller can find the corresponding target pin according to the target pin information and operate the target pin.

The invention relates to a general equipment switch cover control circuit device based on a CPLD (Complex Programmable Logic Device). The general equipment switch cover control circuit device comprises a logic control circuit taking a complex programmable logic device as a core, an input circuit for signal isolation conditioning, an output circuit for power driving isolation, a state indication circuit and a multi-path isolation power supply circuit. According to the invention, the hardware parallel processing capability of the CPLD is utilized to realize nanosecond-level real-time response and strict hardware interlocking of multiple paths of sensor signals; through the design of multi-stage optoelectronic isolation and independent power supply, the anti-interference capability and the system reliability in severe industrial environments such as oil wells and underwater are greatly improved; meanwhile, different devices can be adapted by updating CPLD logic, and high universality and reconfigurability are achieved. The device effectively solves the problems that a traditional PLC is slow in response and a relay system is poor in reliability.

The invention provides a multi-phase power supply time sequence control circuit and an automatic testing device, and is applied to the technical field of integrated circuits. The multi-phase power supply time sequence control circuit comprises a mainboard circuit, a direct current power supply and an automatic test system, and compared with a complex programmable logic device and a multi-phase power supply which are included in a traditional PI test, the mainboard circuit further comprises a reserved circuit. Wherein the complex programmable logic device is used for providing a first enable signal for the multi-phase power supply when the mainboard circuit is electrified and the working scene state is an untested state; the reserved circuit is used for providing a second enable signal for the multi-phase power supply when the direct-current power supply provides the corresponding input voltage and the working scene state is the test state, so that the time sequence of the second enable signal obtained by the multi-phase power supply is later than the time sequence of the input voltage. Therefore, according to the multi-phase power supply time sequence control circuit provided by the invention, the time sequence of the enable signal is ensured to accord with various working scenes, and the efficiency and the accuracy of a multi-phase power supply PI test are improved.

Provided in the present application are a backplane cascade system, an address allocation method and a computer device. The backplane cascade system comprises a mainboard and N backplanes; the mainboard comprises a connector and a complex programmable logic device; each backplane comprises an uplink connector, a downlink connector and a shift register, N>1, and N being a positive integer; the mainboard is connected to the first backplane via the connector and is used for transmitting an address signal to the first backplane by means of the connector; the uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane; the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane which is used for shifting bits of the address signal; the downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane and is used for transmitting the bit-shifted address signal to the (i+1)-th backplane. Only one CPLD is required to be provided on the mainboard, and the mainboard can automatically allocate addresses to external devices on each of the backplanes, thus aiding in maintenance and reducing cost.

The application discloses a substrate management controller repairing method and electronic equipment, and relates to the technical field of substrate management controller repairing, and comprises the following steps: when it is detected that the substrate management controller is in a universal bootloader stage, obtaining firmware information; detecting whether the current working state of the substrate management controller meets certain abnormal conditions according to the firmware information; when the condition is met, controlling the substrate management controller to enter a network boot mode, starting a diskless system, downloading an image file of abnormal firmware from a preset terminal, and executing the flashing of the abnormal firmware, so that after the repairing, the network boot mode is exited, the problems that hardware design is complex, upgrading is prone to failure and threatens safety due to the complex programmable logic device and the network module in remote refreshing, and the problem that the efficiency is low in manual firmware transmission in universal bootloader repairing are solved, the technical effect that external dependence is reduced, and the substrate management controller is repaired in batches automatically by scripts is achieved, and maintainability is improved.

The utility model discloses a server power-on detection device, and relates to the technical field of servers, the server power-on detection device comprises a clock detection circuit, a power-on control circuit and a state indication circuit, the clock detection circuit and the power-on control circuit reuse a complex programmable logic device; the clock detection circuit is used for detecting an internal clock signal of the complex programmable logic device; the power-on control circuit is used for sending a power-on control signal to the at least one step-down power supply module through the complex editable logic device, the power-on control signal is used for indicating to execute power-on operation on the server, and the at least one step-down power supply module is used for executing power-on operation on at least one server component in the server; the state indicating circuit comprises a display unit, and the display unit is used for displaying the power-on sequence of the at least one step-down power supply module, so that the power-on detection efficiency of the server is improved, and the problem that the power-on detection efficiency of the server is low in the prior art is solved.

The application relates to a data transmission system, method, computer device and storage medium. The system comprises a baseboard management controller, a complex programmable logic device, a first multiplexer group, a second multiplexer group, a processor and a plurality of storage chips; the baseboard management controller and the processor are connected with the complex programmable logic device; the storage chips at least comprise a first storage chip, a second storage chip, a third storage chip and a fourth storage chip; the first multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device to turn on any data transmission channel between the baseboard management controller and the first storage chip, the second storage chip and the third storage chip; and the second multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device and turning on any data transmission channel between the processor and the third storage chip and the fourth storage chip according to the control signal. The above system can improve the reliability of data transmission.

This invention relates to the field of server technology, and discloses a flash memory information display method and a server. In response to a system switching command sent by a baseboard management controller (BMC), a complex programmable logic device (CLP) selects a target basic input / output system (BIOS) from the set of input / output systems and switches to the target BOS. The BMC records the switch from the current BOS to the target BOS and saves the flash memory information of the target BOS. The target BOS performs a power-on self-test and retrieves the flash memory information from the BMC. The flash memory information is displayed to characterize the model of the BOS connected to the server host. In this way, the flash memory information of the target BOS can be obtained, allowing users to understand the operating status of the BOS and determine the currently running BOS based on the flash memory information, ensuring the normal operation of the server.

This application provides a synchronization method, apparatus, and vehicle. The method includes determining a synchronization mode for a LiDAR and a camera device based on the resource status of a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA), wherein the synchronization mode for the LiDAR and camera device includes a first synchronization mode or a second synchronization mode; and synchronizing the LiDAR and camera device according to the synchronization mode. This method allows for the determination of the synchronization mode between the LiDAR and camera based on the resource status of the CPLD or FPGA, and enables time or spatiotemporal synchronization of the LiDAR and camera device according to the determined synchronization mode, thereby improving the accuracy and reliability of data fusion between the radar and camera devices.

The invention provides a serial port selection method, device and equipment and a readable storage medium, and is applied to a CPLD (Complex Programmable Logic Device) in UART (Universal Asynchronous Receiver / Transmitter). The method comprises the following steps: receiving a serial port selection instruction issued by an upper computer; the serial port selection instruction carries a baud rate corresponding to a target serial port, and a mapping relation between serial port numbers of optional serial ports and the baud rate is pre-stored in the CPLD; identifying a target serial port according to a serial port selection instruction issued by the upper computer, and connecting the target serial port with the UART path; and generating a corresponding sampling clock and sampling time according to the baud rate corresponding to the target serial port, and completing communication connection with the target serial port by using the sampling clock and the sampling time. According to the technical scheme, the flexibility of serial port switching and the debugging convenience are improved.

Embodiments of the present application provide a method and apparatus for monitoring a hardware partition of a server host system. The method includes: determining a target partition management system on a baseboard management controller, wherein the target partition management system is any partition management system among a plurality of partition management systems divided on the baseboard management controller; selecting, for the target partition management system, at least one target link unit among a plurality of link units divided on a complex programmable logic device, wherein the target link unit is configured to connect the target partition management system and a target hardware partition among a plurality of hardware partitions divided on the server host system; and monitoring the operation of the target hardware partition via the target partition management system and the target link unit. The present application improves the operation monitoring efficiency of a server. The present application relates to the field of computers.

A dual system server includes: a central processing unit, a first baseboard management controller, a second baseboard management controller and a complex programmable logic device. The first baseboard management controller is connected to the central processing unit through a first peripheral component interconnect express interface. The second baseboard management controller is connected to the central processing unit through a second peripheral component interconnect express interface. The complex programmable logic device is connected to the first baseboard management controller through a first inter-integrated circuit interface, and is connected to the second baseboard management controller through a second inter-integrated circuit interface.

The invention belongs to the technical field of servers, and provides a digital diagnosis monitoring method and system for an optical module, and the method comprises the steps: starting a drive program of a CPLD (Complex Programmable Logic Device) through a BMC (Baseboard Management Controller) in response to a power-on signal, and establishing an SPI (Serial Peripheral Interface) communication link between the BMC and the CPLD; the BMC issues a register initialization command to the CPLD through the SPI communication link so as to configure digital diagnosis monitoring DDM parameters of a plurality of optical modules in the optical module group; the BMC issues a DDM parameter reading instruction to the CPLD through the SPI communication link, and receives DDM parameters, returned by the CPLD, of the multiple optical modules; the CPLD preprocesses the DDM parameters of the plurality of optical modules to determine whether to trigger an interrupt signal; and in response to an interrupt signal triggered by the CPLD, the BMC starts an interrupt processing flow to locate a faulty optical module in the plurality of optical modules, and performs fault processing on the faulty optical module based on a predetermined fault processing strategy.

This invention discloses a method and apparatus for performance testing of SPI NAND Flash chips. The method includes: using a complex programmable logic device (CPL) to control a level conversion module to generate several test signals for the chip under test (SUT), wherein the test signals include the access area, test voltage, and test frequency for reading / writing operations on the SUT, and the SUT is an SPI NAND Flash chip; performing read / write operations on the SUT using the test signals; and verifying the correctness of the read / write operation results. This invention can simulate numerous usage scenarios in a short time to quickly verify the various extreme performance limits of the SPI NAND Flash chip and whether it meets product usage requirements, thus greatly improving testing efficiency.

Embodiments of the present application disclose an information transmission method and a computing device, which are used to manage multiple VRs by a BMC chip through a complex programmable logic device (CPLD) and reduce the adaptation workload. The present application is applied to a computing device, which can include a BMC chip, a CPLD and multiple VRs. The BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs. When the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the multiple VRs. Then, the CPLD can determine a first CPLD defined address corresponding to the first BMC defined address, and send the information to the first VR based on the first CPLD defined address. Therefore, the first VR and the first BMC defined address need to be adapted only once on the BMC chip, and if the address of the first VR needs to be modified subsequently, the modification can be made in the CPLD, thereby reducing the adaptation workload and shortening the development cycle.

Systems and methods for secure modular hardware binding in a Data Center Modular Hardware System (DC-SCM) environment are described herein. According to one embodiment, an Information Handling System (IHS) includes multiple Complex Programmable Logic Devices (CPLDs), and computer-executable logic to, for each of the CPLDs: store an encrypted secret key in a platform Root-of-Trust (RoT) and the CPLD, and receive, by the platform RoT, a request to authenticate a firmware stack installed on the CPLD. The logic may then present, by the CPLD, an encrypted secret key to the platform RoT, authenticate, by the platform RoT, the firmware stack by comparing the encrypted secret key received from the CPLD with its stored version of the encrypted secret key, and allow operation of the CPLD based on the authentication.

The invention discloses an SGPIO (Serial General Purpose Input / Output) unified coding method, system and device, and the method is characterized in that the method comprises the steps: powering on a server host, and completing the initialization of a CPLD (Complex Programmable Logic Device) and an SATA / SAS controller; a register and a counter are established, and an SGPIO input Data buffer register, an output Data buffer register and a Clock counter of the SGPIO are established in the CPLD; data frame bit length calculation: the CPLD waits for receiving the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal; whether the bit length of a data frame is equal to 12 bits or not is judged, if the length of the data frame is 12 bits, Clock, Load and Data signals of input SGPIO are directly transmitted to an output IO pin in a transparent mode, and the SGPIO signals of an output interface are completely equal to the SGPIO signals input by the CPLD; and if the data frame length is greater than 12 bits, the signal is processed, so that the SGPIO data of the output port is unified into 12-bit data. By unifying the SGPIO data of the output port into 12 bits, the problem that the bit lengths of SGPIO signals of different devices or interfaces are inconsistent is effectively solved, and the compatibility and standardization degree of the system are remarkably improved.

The present application relates to the technical field of backplanes. Disclosed are a hard disk backplane structure, a control method therefor and a server. The hard disk backplane structure comprises: first connectors located on one side of a backplane and facing a system unit; second connectors located on the other side of the backplane and facing a hard disk drive, the second connectors being correspondingly connected to the first connectors; and a complex programmable logic device located inside the backplane and separately connected to the first connectors and the second connectors, wherein the complex programmable logic device is used for generating information about field replaceable units in a universal backplane management specification so as to determine backplane configuration information, and is further used for feeding back hard disk state information and controlling a lighting operation after receiving a universal backplane management protocol. Such a backplane structure is free of restrictions of architecture chip selection, and integrates functions of field replaceable units and functions of controllers in the original universal backplane management specification into a complex programmable logic device, thus improving the integration density of chips, increasing the structural opening ratio, improving heat dissipation efficiency, reducing layout and wiring difficulties, and decreasing chip costs.

The embodiments of the present application relate to the technical field of computers. Provided are a server control method and apparatus, a device, a medium and a computer program product. The method comprises: if a multiplexer receives a first control signal sent by a complex programmable logic device, sending a first reset signal to a high-speed serial bus endpoint module in a baseboard management controller by means of a target host; if the baseboard management controller detects the first reset signal, sending a second reset signal to a high-speed serial bus module of a field programmable gate array by means of the baseboard management controller; and if the multiplexer receives a second control signal sent by the complex programmable logic device, sending a third reset signal to the high-speed serial bus module of the field programmable gate array by means of the baseboard management controller. The embodiments of the present application ensure normal communication between the baseboard management controller and the field programmable gate array.