155 results about "Complex programmable logic device" patented technology

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

The invention provides a PCIe equipment fault monitoring and dynamic processing method based on intelligent prediction, and the method comprises the steps: obtaining operation parameters from a BMC (baseboard management controller), an operation system and a PCIe equipment register, carrying out the processing and time sequence feature extraction, and inputting a lightweight long short-term memory network LSTM model deployed in the BMC for fault probability prediction. And combining the prediction result and the operation parameters to calculate an equipment health score, and triggering an alarm, bandwidth degradation or hardware isolation operation according to the score. And the hardware isolation module sends a control instruction to the complex programmable logic device CPLD through the IC bus to realize non-interruption power-off isolation of the target equipment. And uploading real-time data to a cloud server through encryption communication, executing fine adjustment of the model, and returning an update weight to realize continuous optimization and version control of the model. The method can be widely applied to computing equipment such as a server, and the availability and the fault-tolerant capability of the system are improved.

The invention discloses a server, and relates to the field of computers, the server comprises a substrate management controller, a server interface and a plurality of server hardware, the substrate management controller comprises a link controller and a plurality of transmitters, the plurality of transmitters are connected with the plurality of server hardware in a one-to-one correspondence manner, and the server interface is connected with the link controller; the link controller is used for detecting current to-be-controlled target server hardware from a target control request currently received by the server interface and controlling a target transmitter in the plurality of transmitters to construct a communication link with the server interface; and the target transmitter in the plurality of transmitters is used for acquiring the target control request from the server interface through the communication link and transmitting the target control request to the target server hardware, thereby solving the technical problems of high dependency degree of the control process of the server hardware on the complex programmable logic device and the like.

The present application provides a complex programmable logic device (CPLD)-based data processing method and system, and a computing device. The CPLD is arranged on a hard disk backplane of a server, and the hard disk backplane supports a universal backplane management (UBM) protocol; the hard disk backplane comprises an HFC connector for connecting to a RAID controller and a DFC connector for connecting to a hard disk slot, and the CPLD is connected to the HFC connector and the DFC connector, respectively. The method comprises: when a hard disk is inserted into the hard disk slot, determining an interface type of the hard disk according to a signal level transmitted by the DFC; processing interaction data between the RAID controller and the hard disk according to the hard disk interface type, wherein the interaction data comprises data indicating the hard disk interface type, data indicating a hard disk state and read / write operation command data; and transmitting the processed data to the RAID controller or the hard disk so as to achieve hard disk management, wherein the hard disk comprises a hard disk of an SAS / SATA / NVME interface type. In this way, new logic functionality is added to an existing logic chip of the hard disk backplane to achieve the functionality of the UBM protocol.

The invention provides a system and a method for automatically identifying OCP network card bandwidth. According to the system for automatically identifying the bandwidth of the OCP network card, dynamic bandwidth allocation is achieved through cooperation of the multiple computing nodes, the CPLD and the OCP network card, each computing node is connected with a connector on the side of the OCP network card through a certain x8 MCIO connector in a set of x8 MCIO connectors, each computing node distinguishes the node identity through differential voltage configuration of a reserved detection pin, and therefore the bandwidth of the OCP network card can be automatically identified. And the CPLD acquires node identity detection signals to judge an access mode, determines a bandwidth allocation strategy by combining with the slot in-place detection signal group, generates a bandwidth configuration control signal group according to the bandwidth allocation strategy, and feeds back the bandwidth configuration control signal group to the OCP network card. According to the system, the OCP network card bandwidth identification and distribution are carried out by using hardware, and the application of OCP network cards with different bandwidths in various access modes can be dealt with only through a CPLD (Complex Programmable Logic Device) under the condition that firmware of each hardware is not frequently replaced.

The invention discloses a method for solving conflict between a baseboard management controller (BMC) and a central processing unit (CPU) accessing a real-time clock (RTC), which relates to the technical field of computer firmware, and comprises the following steps: before a central processing unit (CPU) of a server accesses the RTC, a first signal representing that the CPU accesses the RTC is transmitted to the BMC through a complex programmable logic device (CPLD); the information indicating that the RTC is occupied by the CPU is notified to the BMC; after the CPU transmits the first signal representing that the CPU accesses the RTC to the BMC, the CPU accesses the RTC through a hardware link between the CPU and the RTC, wherein the hardware link is controlled by the BMC and the CPLD to be communicated with the CPU and the RTC; and before accessing the RTC, the BMC determines that the CPU is accessing the RTC according to the first signal representing that the CPU accesses the RTC, and delays accessing the RTC when determining that the CPU accesses the RTC so as to eliminate access conflicts. In the invention, the BMC and the CPU do not access the RTC at the same time, and time abnormity caused by access conflicts can be eliminated.

A mainboard protection system and method are provided. A precision resistor is arranged between an overcurrent protection component and a voltage regulator, and the precision resistor is connected to a current monitoring circuit. The current monitoring circuit is connected to a complex programmable logic device, and transmits, w detecting that a voltage difference of the precision resistor is greater than a set threshold, an early-warning signal to the complex programmable logic device. The complex programmable logic device is connected to a processor and sends, when receiving the early-warning signal, an interrupt signal to the processor. in response to receiving the interrupt signal, the processor cuts off outputting of the overcurrent protection component.

The invention provides a communication system and a communication method used between multiple nodes and I2C equipment, and relates to the technical field of servers. The system is arranged in I2C equipment and comprises a CPLD (Complex Programmable Logic Device) module, a multiplexing switch module and a plurality of connectors, and the connectors are connected with a BMC (Baseboard Management Controller) and the CPLD module of a node to form a direct connection channel of the BMC and the CPLD; the multiplexing switch module is connected with the CPLD module, and the connector is also connected with I2C equipment through the multiplexing switch module; the CPLD module receives a permission request instruction of a multi-node BMC to an I2C bus through a direct connection channel, generates a channel selection instruction for indicating to gate a channel between a target BMC and I2C equipment, and sends the instruction to the multiplexing switch module; and the multiplexing switch module only gates the communication connection between the target BMC and the I2C equipment based on the instruction, so that the problem of I2C bus abnormity caused by communication arbitration of a plurality of BMCs is effectively avoided.

A liquid leakage detection circuit, comprising a sensing line anomaly detection trigger sub-circuit and a liquid leakage detection sub-circuit; are connected by a liquid leakage sensing line, wherein the sensing line anomaly detection trigger sub-circuit is configured to be conducted according to a liquid leakage simulation signal generated by a complex programmable logic device, so as to perform anomaly detection on the liquid leakage sensing line by the liquid leakage detection sub-circuit; and the liquid leakage detection sub-circuit is configured to perform anomaly detection on the liquid leakage sensing line according to a change condition of an input voltage when it is determined that the sensing line anomaly detection trigger sub-circuit is conducted, and to perform liquid leakage detection after it is determined that the liquid leakage sensing line has no anomaly condition.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The invention provides a method for modifying server hardware configuration, which relates to the technical field of computers, and comprises the following steps: reading a hardware configuration table from an EEPROM (Electrically Erasable Programmable Read-Only Memory) through a CPLD (Complex Programmable Logic Device) and The CPLD analyzes the hardware configuration table after passing the verification, and starts or disables the corresponding hardware module according to the hardware configuration information; receiving a configuration updating instruction through the BMC, switching an I2C channel to connect the BMC and the EEPROM after the target hardware configuration table passes the verification, and writing the target hardware configuration table into the EEPROM; and after writing is completed, the connection between the CPLD and the EEPROM is recovered, and hardware configuration updating is completed. The technical problems that in the prior art, hardware configuration management depends on manual operation and firmware adjustment, so that configuration updating is inconvenient, and hardware module control is limited are solved, and the technical effect of improving the flexibility and accuracy of server hardware configuration management and the overall stability is achieved.

The invention discloses a controller communication system and method, a computer product, equipment and a storage medium, and relates to the technical field of controller communication, and the controller communication system comprises a first controller which is provided with a first processor and a first complex programmable logic device; the second controller is provided with a second processor and a second complex programmable logic device; the first processor is connected with the first complex programmable logic device through a first connecting line, the first complex programmable logic device is connected with the second complex programmable logic device through a second connecting line, and the second complex programmable logic device is connected with the second processor through a third connecting line. A plurality of pins are arranged on the complex programmable logic device; and according to different target fault information types and a link formed by the plurality of pins and the plurality of connection lines corresponding to the different target fault information types, fault information transmission between the controllers is realized. The technical problem of low service switching efficiency between the controllers is solved, and the communication efficiency of the controllers can be improved.

The invention discloses a communication device, a communication control method, an electronic device, a medium and a program product, and relates to the technical field of communication, by adopting the technical scheme provided by the invention, a target physical layer device is directly connected to a first multiplexer instead of being directly connected to a complex programmable logic device serving as a control element, so that the communication efficiency is improved. Therefore, when a plurality of physical layer devices need to be managed, a large number of MDIO pins do not need to be arranged on the control element so as to support switching control of MDIO signals. Therefore, the technical problem of shortage of pin resources and logic unit resources faced by a complex programmable logic device can be solved, and the technical effects of remarkably reducing the system cost and facilitating commercial application of products are achieved.

The SGPIO multi-path expansion circuit provided by the embodiment of the utility model comprises a mainboard management controller BMC and at least two complex programmable logic devices CPLDs connected with the BMC in series, each CPLD comprises an SGPIO slave node Slave and a first multiplexer MUX connected with the SGPIO slave node Slave, an output interface of the BMC is connected with the SGPIO slave node Slave in each CPLD, and an output interface of the BMC is connected with the first multiplexer MUX. Different SGPIO Slaves are configured to analyze signals of preset storage space digits in first signals transmitted by the output interface of the BMC. According to the technical scheme, the SGPIO Slave in the CPLD receives the signals transmitted by the output interface of the BMC, then the SGPIO Slave only analyzes the signals with the preset storage space bits in the first signals, and then the unanalyzed signal data is transmitted to the next CPLD to be analyzed, so that logic resources consumed by the CPLD are reduced, and the real-time performance of data transmission is improved.

The invention relates to the technical field of servers, in particular to a hard disk alarm method and device of a server, the server and a medium, the method is applied to a substrate management controller in the server, and the server further comprises a backboard and a plurality of hard disks; a complex programmable logic device is arranged on the back plate; the complex programmable logic device and the backboard are connected with the substrate management controller. The method comprises the following steps: reading a target hard disk in-place signal of the complex programmable logic device, wherein the target hard disk is any one of a plurality of hard disks; reading the hard disk state of the target hard disk; determining whether the target hard disk is a fault hard disk according to the in-place signal and the hard disk state of the target hard disk; if the target hard disk is the fault hard disk, alarm information of the target hard disk is output, and the alarm information is used for fault alarm of the target hard disk; the problem that the substrate management controller can still give an alarm under the condition that the card end of the redundant array of independent disks of the hard disk is not recognized is solved, and the accuracy of determining the faulty hard disk is improved.

The present application provides a method for monitoring and dynamically handling PCIe device faults based on intelligent prediction. The method obtains operating parameters from the baseboard management controller BMC, the operating system, and the PCIe device registers, processes and extracts time series features, and then inputs the parameters into a lightweight long short-term memory network LSTM model deployed in the BMC to predict the probability of faults. The device health score is calculated based on the prediction results and the operating parameters, and alarms, bandwidth degradation, or hardware isolation operations are triggered based on the score. The hardware isolation module sends control instructions to the complex programmable logic device CPLD via the I²C bus to achieve uninterrupted power-off isolation of the target device. Real-time data is uploaded to the cloud server through encrypted communication, and the updated weights are transmitted back after model fine-tuning to achieve continuous optimization and version control of the model. The present invention can be widely used in computing devices such as servers to improve system availability and fault tolerance.

The invention relates to the technical field of CPLD upgrading, and discloses a CPLD remote online upgrading method and system based on SPI communication and electronic device.The method comprises the steps that binary format data of a CPLD upgrading file is transmitted to a main control chip through a CAN communication protocol, and upgrading data is obtained; and the master control chip transmits the upgrade data to the CPLD by using an SPI communication protocol, receives and writes the data, and completes remote online upgrade of the CPLD. The CPLD is upgraded based on the SPI communication protocol, dependence on a traditional programmer is eliminated, the system can be automatically upgraded during normal operation, manual intervention or shutdown is not needed, the efficiency and flexibility of system maintenance are improved, and the reliability and stability of the system are enhanced. Compared with a traditional JTAG interface, the SPI protocol supports full-duplex communication, and the transmission rate is higher, so that data transmission can be completed more quickly, and the system upgrading time is shortened.

Disclosed in the present application are a control method and apparatus for an indication apparatus, and a server and a medium. The method comprises: acquiring the current state to be set of an indication apparatus corresponding to a target device; acquiring the current refresh state of a complex programmable logic device of a target board and the previous refresh state of the current refresh state thereof, wherein refresh states comprise an unrefreshed state, a refreshing state and a refresh-completed state, the target board is a board connected to the indication apparatus, and the target device is a device provided on the target board; when it is detected that the current refresh state and the previous refresh state satisfy a preset requirement, determining that the update of the complex programmable logic device of the target board has been completed; and when a baseboard management controller operates, writing, into the complex programmable logic device of the target board, corresponding data representing the current state to be set, so as to control, by means of the complex programmable logic device of the target board, the state of the indication apparatus to be the current state to be set.

The invention discloses an upgrading method and device of a complex programmable logic device (CPLD), electronic equipment and a medium, and the method comprises the steps: controlling a fifth input / output pin to send a starting signal to a first input / output pin based on a first code if the CPLD has an upgrading demand, sending a starting signal to a second input / output pin through a sixth input / output pin so as to load a second code; and under the condition that the second code is loaded, loading upgrading data of the CPLD based on a baseboard management controller (BMC), sending the upgrading data to a third input / output pin and a fourth input / output pin, and upgrading the CPLD through the upgrading data. Therefore, the problems that in the application scene of the current server, the power-on loading or upgrading process of the CPLD is interrupted by I2C communication of the BMC, loading or upgrading of the CPLD fails, and finally running of the whole server is abnormal are solved, and safe starting and successful upgrading of the CPLD and stable running of the server are guaranteed.

The present application relates to the technical field of hanging debugging, and discloses a debugging method, device and equipment for a hanging management engine and a storage medium, which are applied to a baseboard management controller, wherein the baseboard management controller, a complex programmable logic device and a platform path controller are communicatively connected in pairs; the method comprises the following steps: when an abnormal state of the management engine is detected, obtaining state information of the platform path controller; the abnormal state information of the abnormal state is obtained by communication between the complex programmable logic device and the platform path controller and is sent to the baseboard management controller; based on the state information, the management engine is debugged to determine the abnormal source of the management engine. In this way, when the management engine is in an abnormal state, the state information of the platform path controller is obtained to debug the management engine and determine the abnormal source of the management engine, thereby improving the timeliness and completeness of the relevant debugging information obtained when the management engine is hanging, and thus the debugging efficiency of the hanging management engine is improved.

The application relates to the technical field of servers and discloses a method for acquiring network card information, a server board card, equipment and a medium, the method for acquiring network card information comprises the following steps: outputting a clock signal and a data loading enable signal to a network card through a complex programmable logic device, and reading a data signal sent by the network card by using the clock signal and the loading enable signal; processing the data signal sent by the network card through the complex programmable logic device, generating internal register data, and transmitting the internal register data to a baseboard management controller; and updating a log file based on the internal register data through the baseboard management controller; wherein the log file stores the data signal sent by the network card. The application enriches the read data signal sent by the network card, increases the flexibility and practicality of network card management, and reduces the difficulty of network card problem processing.

The invention relates to a hard disk control system and method. The hard disk control method is executed by a complex programmable logic device, and comprises the following steps: detecting a first voltage of a first data line connected with a first node and a second voltage of a second data line connected with a second node under the triggering of a management instruction, and judging at least one of the first node and the second node as a target node according to the first voltage and the second voltage, reading a pre-stored mapping table corresponding to the target node, judging a target hard disk address according to the pre-stored mapping table and the target logic address, and controlling a hard disk corresponding to the target hard disk address according to the target operation.

The invention relates to a current-limiting protection method and system for a controller, belongs to the technical field of controllers, and solves the problems of complex control, inflexibility, low efficiency and higher cost caused by the need of adding an additional CPLD (Complex Programmable Logic Device) chip or selecting a main control chip with a CBC mode function in the existing current-limiting method. Comprising the following steps: in the working process of a controller, continuously detecting a hardware overcurrent signal of the controller; if the hardware overcurrent signal is detected to be effective, triggering an interrupt service program; and the interrupt service program carries out overcurrent control on the controller and outputs an overcurrent fault signal, if the overcurrent fault signal is effective, the interrupt service program enters a fault mode, and otherwise, the interrupt service program continues to wait for triggering.

Efficient continuity testing for instruments connected to a mass interconnect. Digital input and output capabilities may be used on each pin of the mass interconnect to test a variety of input / output (I / O) types on a device under test. Each pin of the interconnect may connect to a respective corresponding digital input and digital output in the tester, with the digital input resistively coupled to the digital output. The connectivity of the pin to the digital input and the digital output, and the connectivity between the digital input and the digital output may be implemented with shift registers and a buffer stage, respectively. In some embodiments, the structure may be implemented through parallel I / O blocks, as in a complex programmable logic device (CPLD), field programmable gate array (FPGA), or microcontroller.

The invention provides an FPGA (Field Programmable Gate Array) configuration loading method, a chip circuit and routing equipment, and the method comprises the following steps: an FPGA obtains a mode instruction sent by a controller, when the mode instruction is identified as a first instruction, the FPGA loads configuration from a lower FLASH, or when the mode instruction is identified as a second instruction, the FPGA loads configuration from the lower FLASH; and the FPGA is loaded and configured from a complex programmable logic device (CPLD). Through the method, a dynamic switching mechanism of the AS (Active Serial) mode and the PS (Passive Serial) mode can be realized, the reliability of the AS and the flexibility of the PS are fused, and the self-adaption and fault-tolerant capabilities of the FPGA configuration system are realized.

A PCIe Gen5 interface test device and a method thereof are characterized in that a test mainboard is electrically connected with a to-be-tested machine board through N MCIO (Mini Cool Edge IO) connectors and corresponding connecting lines thereof, so that the test mainboard receives a PCIe Gen5 differential signal, a differential clock rate signal, an input / output signal and an I2C signal from the to-be-tested machine board; and testing is carried out through a test logic circuit of the complex programmable logic device and a test program of the substrate management controller, so that the technical effects of improving the test convenience and the coverage rate are achieved.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The invention relates to the technical field of server design, and discloses a GPIO (General Purpose Input / Output) resource operation method and system, a server and a computer readable storage medium, the method is applied to the server, and the method comprises the following steps: obtaining target pin information and operation information through a baseboard management controller, and searching a preset register mapping table on the GPIO subsystem according to the target pin information to obtain a target register address, and operating GPIO resources of the complex programmable logic device by the substrate management controller according to the target register address and the operation information. By means of the mode, GPIO resource operation on the server is more convenient, hardware and the application program can be decoupled, even if the pins change due to subsequent hardware updating, the application program does not need to be modified as long as the information of the pins achieving the same function is the same, and the user experience is improved. And the substrate management controller can find the corresponding target pin according to the target pin information and operate the target pin.

A mainboard protection system and method are provided. A precision resistor is arranged between an overcurrent protection component and a voltage regulator, and the precision resistor is connected to a current monitoring circuit. The current monitoring circuit is connected to a complex programmable logic device, and transmits, w detecting that a voltage difference of the precision resistor is greater than a set threshold, an early-warning signal to the complex programmable logic device. The complex programmable logic device is connected to a processor and sends, when receiving the early-warning signal, an interrupt signal to the processor. in response to receiving the interrupt signal, the processor cuts off outputting of the overcurrent protection component.

The invention relates to a general equipment switch cover control circuit device based on a CPLD (Complex Programmable Logic Device). The general equipment switch cover control circuit device comprises a logic control circuit taking a complex programmable logic device as a core, an input circuit for signal isolation conditioning, an output circuit for power driving isolation, a state indication circuit and a multi-path isolation power supply circuit. According to the invention, the hardware parallel processing capability of the CPLD is utilized to realize nanosecond-level real-time response and strict hardware interlocking of multiple paths of sensor signals; through the design of multi-stage optoelectronic isolation and independent power supply, the anti-interference capability and the system reliability in severe industrial environments such as oil wells and underwater are greatly improved; meanwhile, different devices can be adapted by updating CPLD logic, and high universality and reconfigurability are achieved. The device effectively solves the problems that a traditional PLC is slow in response and a relay system is poor in reliability.