51 results about "Complex programmable logic device" patented technology

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The present application relates to the technical field of hanging debugging, and discloses a debugging method, device and equipment for a hanging management engine and a storage medium, which are applied to a baseboard management controller, wherein the baseboard management controller, a complex programmable logic device and a platform path controller are communicatively connected in pairs; the method comprises the following steps: when an abnormal state of the management engine is detected, obtaining state information of the platform path controller; the abnormal state information of the abnormal state is obtained by communication between the complex programmable logic device and the platform path controller and is sent to the baseboard management controller; based on the state information, the management engine is debugged to determine the abnormal source of the management engine. In this way, when the management engine is in an abnormal state, the state information of the platform path controller is obtained to debug the management engine and determine the abnormal source of the management engine, thereby improving the timeliness and completeness of the relevant debugging information obtained when the management engine is hanging, and thus the debugging efficiency of the hanging management engine is improved.

The invention relates to a hard disk control system and method. The hard disk control method is executed by a complex programmable logic device, and comprises the following steps: detecting a first voltage of a first data line connected with a first node and a second voltage of a second data line connected with a second node under the triggering of a management instruction, and judging at least one of the first node and the second node as a target node according to the first voltage and the second voltage, reading a pre-stored mapping table corresponding to the target node, judging a target hard disk address according to the pre-stored mapping table and the target logic address, and controlling a hard disk corresponding to the target hard disk address according to the target operation.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The invention relates to the technical field of server design, and discloses a GPIO (General Purpose Input / Output) resource operation method and system, a server and a computer readable storage medium, the method is applied to the server, and the method comprises the following steps: obtaining target pin information and operation information through a baseboard management controller, and searching a preset register mapping table on the GPIO subsystem according to the target pin information to obtain a target register address, and operating GPIO resources of the complex programmable logic device by the substrate management controller according to the target register address and the operation information. By means of the mode, GPIO resource operation on the server is more convenient, hardware and the application program can be decoupled, even if the pins change due to subsequent hardware updating, the application program does not need to be modified as long as the information of the pins achieving the same function is the same, and the user experience is improved. And the substrate management controller can find the corresponding target pin according to the target pin information and operate the target pin.

The invention relates to a general equipment switch cover control circuit device based on a CPLD (Complex Programmable Logic Device). The general equipment switch cover control circuit device comprises a logic control circuit taking a complex programmable logic device as a core, an input circuit for signal isolation conditioning, an output circuit for power driving isolation, a state indication circuit and a multi-path isolation power supply circuit. According to the invention, the hardware parallel processing capability of the CPLD is utilized to realize nanosecond-level real-time response and strict hardware interlocking of multiple paths of sensor signals; through the design of multi-stage optoelectronic isolation and independent power supply, the anti-interference capability and the system reliability in severe industrial environments such as oil wells and underwater are greatly improved; meanwhile, different devices can be adapted by updating CPLD logic, and high universality and reconfigurability are achieved. The device effectively solves the problems that a traditional PLC is slow in response and a relay system is poor in reliability.

The invention provides a multi-phase power supply time sequence control circuit and an automatic testing device, and is applied to the technical field of integrated circuits. The multi-phase power supply time sequence control circuit comprises a mainboard circuit, a direct current power supply and an automatic test system, and compared with a complex programmable logic device and a multi-phase power supply which are included in a traditional PI test, the mainboard circuit further comprises a reserved circuit. Wherein the complex programmable logic device is used for providing a first enable signal for the multi-phase power supply when the mainboard circuit is electrified and the working scene state is an untested state; the reserved circuit is used for providing a second enable signal for the multi-phase power supply when the direct-current power supply provides the corresponding input voltage and the working scene state is the test state, so that the time sequence of the second enable signal obtained by the multi-phase power supply is later than the time sequence of the input voltage. Therefore, according to the multi-phase power supply time sequence control circuit provided by the invention, the time sequence of the enable signal is ensured to accord with various working scenes, and the efficiency and the accuracy of a multi-phase power supply PI test are improved.

The application discloses a substrate management controller repairing method and electronic equipment, and relates to the technical field of substrate management controller repairing, and comprises the following steps: when it is detected that the substrate management controller is in a universal bootloader stage, obtaining firmware information; detecting whether the current working state of the substrate management controller meets certain abnormal conditions according to the firmware information; when the condition is met, controlling the substrate management controller to enter a network boot mode, starting a diskless system, downloading an image file of abnormal firmware from a preset terminal, and executing the flashing of the abnormal firmware, so that after the repairing, the network boot mode is exited, the problems that hardware design is complex, upgrading is prone to failure and threatens safety due to the complex programmable logic device and the network module in remote refreshing, and the problem that the efficiency is low in manual firmware transmission in universal bootloader repairing are solved, the technical effect that external dependence is reduced, and the substrate management controller is repaired in batches automatically by scripts is achieved, and maintainability is improved.

This invention relates to the field of server technology, and discloses a flash memory information display method and a server. In response to a system switching command sent by a baseboard management controller (BMC), a complex programmable logic device (CLP) selects a target basic input / output system (BIOS) from the set of input / output systems and switches to the target BOS. The BMC records the switch from the current BOS to the target BOS and saves the flash memory information of the target BOS. The target BOS performs a power-on self-test and retrieves the flash memory information from the BMC. The flash memory information is displayed to characterize the model of the BOS connected to the server host. In this way, the flash memory information of the target BOS can be obtained, allowing users to understand the operating status of the BOS and determine the currently running BOS based on the flash memory information, ensuring the normal operation of the server.

This application provides a synchronization method, apparatus, and vehicle. The method includes determining a synchronization mode for a LiDAR and a camera device based on the resource status of a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA), wherein the synchronization mode for the LiDAR and camera device includes a first synchronization mode or a second synchronization mode; and synchronizing the LiDAR and camera device according to the synchronization mode. This method allows for the determination of the synchronization mode between the LiDAR and camera based on the resource status of the CPLD or FPGA, and enables time or spatiotemporal synchronization of the LiDAR and camera device according to the determined synchronization mode, thereby improving the accuracy and reliability of data fusion between the radar and camera devices.

The invention provides a serial port selection method, device and equipment and a readable storage medium, and is applied to a CPLD (Complex Programmable Logic Device) in UART (Universal Asynchronous Receiver / Transmitter). The method comprises the following steps: receiving a serial port selection instruction issued by an upper computer; the serial port selection instruction carries a baud rate corresponding to a target serial port, and a mapping relation between serial port numbers of optional serial ports and the baud rate is pre-stored in the CPLD; identifying a target serial port according to a serial port selection instruction issued by the upper computer, and connecting the target serial port with the UART path; and generating a corresponding sampling clock and sampling time according to the baud rate corresponding to the target serial port, and completing communication connection with the target serial port by using the sampling clock and the sampling time. According to the technical scheme, the flexibility of serial port switching and the debugging convenience are improved.

Embodiments of the present application provide a method and apparatus for monitoring a hardware partition of a server host system. The method includes: determining a target partition management system on a baseboard management controller, wherein the target partition management system is any partition management system among a plurality of partition management systems divided on the baseboard management controller; selecting, for the target partition management system, at least one target link unit among a plurality of link units divided on a complex programmable logic device, wherein the target link unit is configured to connect the target partition management system and a target hardware partition among a plurality of hardware partitions divided on the server host system; and monitoring the operation of the target hardware partition via the target partition management system and the target link unit. The present application improves the operation monitoring efficiency of a server. The present application relates to the field of computers.

The invention belongs to the technical field of servers, and provides a digital diagnosis monitoring method and system for an optical module, and the method comprises the steps: starting a drive program of a CPLD (Complex Programmable Logic Device) through a BMC (Baseboard Management Controller) in response to a power-on signal, and establishing an SPI (Serial Peripheral Interface) communication link between the BMC and the CPLD; the BMC issues a register initialization command to the CPLD through the SPI communication link so as to configure digital diagnosis monitoring DDM parameters of a plurality of optical modules in the optical module group; the BMC issues a DDM parameter reading instruction to the CPLD through the SPI communication link, and receives DDM parameters, returned by the CPLD, of the multiple optical modules; the CPLD preprocesses the DDM parameters of the plurality of optical modules to determine whether to trigger an interrupt signal; and in response to an interrupt signal triggered by the CPLD, the BMC starts an interrupt processing flow to locate a faulty optical module in the plurality of optical modules, and performs fault processing on the faulty optical module based on a predetermined fault processing strategy.

This invention discloses a method and apparatus for performance testing of SPI NAND Flash chips. The method includes: using a complex programmable logic device (CPL) to control a level conversion module to generate several test signals for the chip under test (SUT), wherein the test signals include the access area, test voltage, and test frequency for reading / writing operations on the SUT, and the SUT is an SPI NAND Flash chip; performing read / write operations on the SUT using the test signals; and verifying the correctness of the read / write operation results. This invention can simulate numerous usage scenarios in a short time to quickly verify the various extreme performance limits of the SPI NAND Flash chip and whether it meets product usage requirements, thus greatly improving testing efficiency.

Embodiments of the present application disclose an information transmission method and a computing device, which are used to manage multiple VRs by a BMC chip through a complex programmable logic device (CPLD) and reduce the adaptation workload. The present application is applied to a computing device, which can include a BMC chip, a CPLD and multiple VRs. The BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs. When the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the multiple VRs. Then, the CPLD can determine a first CPLD defined address corresponding to the first BMC defined address, and send the information to the first VR based on the first CPLD defined address. Therefore, the first VR and the first BMC defined address need to be adapted only once on the BMC chip, and if the address of the first VR needs to be modified subsequently, the modification can be made in the CPLD, thereby reducing the adaptation workload and shortening the development cycle.

Systems and methods for secure modular hardware binding in a Data Center Modular Hardware System (DC-SCM) environment are described herein. According to one embodiment, an Information Handling System (IHS) includes multiple Complex Programmable Logic Devices (CPLDs), and computer-executable logic to, for each of the CPLDs: store an encrypted secret key in a platform Root-of-Trust (RoT) and the CPLD, and receive, by the platform RoT, a request to authenticate a firmware stack installed on the CPLD. The logic may then present, by the CPLD, an encrypted secret key to the platform RoT, authenticate, by the platform RoT, the firmware stack by comparing the encrypted secret key received from the CPLD with its stored version of the encrypted secret key, and allow operation of the CPLD based on the authentication.

The present application relates to the technical field of backplanes. Disclosed are a hard disk backplane structure, a control method therefor and a server. The hard disk backplane structure comprises: first connectors located on one side of a backplane and facing a system unit; second connectors located on the other side of the backplane and facing a hard disk drive, the second connectors being correspondingly connected to the first connectors; and a complex programmable logic device located inside the backplane and separately connected to the first connectors and the second connectors, wherein the complex programmable logic device is used for generating information about field replaceable units in a universal backplane management specification so as to determine backplane configuration information, and is further used for feeding back hard disk state information and controlling a lighting operation after receiving a universal backplane management protocol. Such a backplane structure is free of restrictions of architecture chip selection, and integrates functions of field replaceable units and functions of controllers in the original universal backplane management specification into a complex programmable logic device, thus improving the integration density of chips, increasing the structural opening ratio, improving heat dissipation efficiency, reducing layout and wiring difficulties, and decreasing chip costs.

The embodiments of the present application relate to the technical field of computers. Provided are a server control method and apparatus, a device, a medium and a computer program product. The method comprises: if a multiplexer receives a first control signal sent by a complex programmable logic device, sending a first reset signal to a high-speed serial bus endpoint module in a baseboard management controller by means of a target host; if the baseboard management controller detects the first reset signal, sending a second reset signal to a high-speed serial bus module of a field programmable gate array by means of the baseboard management controller; and if the multiplexer receives a second control signal sent by the complex programmable logic device, sending a third reset signal to the high-speed serial bus module of the field programmable gate array by means of the baseboard management controller. The embodiments of the present application ensure normal communication between the baseboard management controller and the field programmable gate array.

The invention discloses a rail pressure control method and system based on CPLD hardware constant current control and electronic equipment, and relates to the technical field of oil pump electromagnetic valve control, and the method comprises the steps that a main control unit issues control parameters and time sequence synchronizing signals to a lower control unit; the lower control unit receives and analyzes the control parameters and feeds back a current detection value and fault state information to the main control unit; generating a driving signal based on the analyzed control parameter, specifically, obtaining processed current feedback data, and obtaining an effective duty ratio; generating a high-end driving signal according to the effective duty ratio in combination with the current modulation frequency, and outputting a low-end driving signal conforming to a preset conduction mode; the high-end driving signal controls the on-off of the first power switch device, and the low-end driving signal controls the on-off of the second power switch device; the effective duty cycle is dynamically adjusted based on a current feedback signal.

The utility model relates to the technical field of computer hardware, and discloses a mercuric chloride 310P-based wide-temperature computing power module. Comprising a processor, and the processor comprises a CPU and an AI processor; the computing power module further comprises an EMMC storage module, a first LPDDR storage module, a second LPDDR storage module, a Flash storage module and a complex programmable logic device (CPLD) which are connected with the processor. And a functional pin of the FMC connector is connected with the processor. The elements in the computing power module are all wide-temperature elements with strong environment temperature adaptability, so that the environment adaptability of the computing power module is greatly improved.

The application relates to a serial communication system and method, the serial communication system comprising a master device, a first slave device, at least one second slave device, a serial bus and a complex programmable logic device; the complex programmable logic device comprises a master pin, a first slave pin and at least one second slave pin; the master pin is connected with the master device through the serial bus, the first slave pin is connected with the first slave device through the serial bus, and the second slave pin is connected with the second slave device through the serial bus; and the complex programmable logic device is used for realizing line and logic based communication between the master device, the first slave device and the at least one second slave device. The serial communication system provided by the application is simple in logic and provides a physical basis for efficient communication, so that the communication efficiency of the serial communication system can be improved.

The application discloses a bandwidth transmission improving method and device between a BMC and a CMC, equipment and a storage medium, relates to the technical field of computers, and comprises the following steps: constructing preset codes for converting an I2C bus mode into a serial peripheral interface SPI bus mode in the BMC and the CMC respectively, so as to determine a first SPI bus corresponding to the BMC and a second SPI bus corresponding to the CMC; obtaining an in-situ signal of a complex programmable logic device of a server node through the first SPI bus and monitoring the state change thereof; based on the state change process of the in-situ signal, communicating with the complex programmable logic device on the server backboard by using a low-voltage differential signal, so that the complex programmable logic device on the server backboard transmits with the CMC through the second SPI bus. Through the technical scheme of the application, the design difficulty is reduced and the cost is saved without additional chip support for hot plug, and meanwhile, the transmission speed between the CMC and the BMC is improved without affecting the safety.

The application discloses a data transmission device and electronic equipment containing the same. The data transmission device comprises a master control unit, a complex programmable logic device and an I 2 C device, a single bus driving module, a FIFO storage module and an I 2 C bus driving module are arranged in the complex programmable logic device, the master control unit is connected to the single bus driving module through a single bus, the I 2 C device is connected to the I 2 C bus driving module through an I 2 C bus. The I 2 C bus driving module receives first data from the I 2 C device through the I 2 C bus, processes the first data into second data and writes the second data into the FIFO storage module; the single bus driving module reads the second data from the FIFO storage module, processes the second data into third data and sends the third data to the master control unit through the single bus. 2 In the application, one I 2 C device only occupies one I / O port of the master control unit, so that more I

The utility model provides a CPLD (Complex Programmable Logic Device)-based server mainboard and a server, which relate to the technical field of computers and comprise a processor, a BIOS (Basic Input Output System) chip, a CPLD module and a BMC (Baseboard Management The CPLD module is connected with the processor through a first SPI interface, a first LPC interface and a first UART interface; the CPLD module is connected with the BMC module through a second SPI interface, a second LPC interface and a second UART interface; and the CPLD module is connected with the BIOS chip through a third SPI (Serial Peripheral Interface). The server mainboard based on the CPLD is high in integration level, the fault response time of the mainboard is shortened, the maintenance workload of a domestic server is reduced, and the reliability and safety of the domestic server are improved.

This application discloses a high-performance computing module and data processing method, which adopts a standard 6U VPX architecture. The module includes: a Tengrui D3000 central processing unit (CPU), a DDR5 memory module, a complex programmable logic device (CLP) module, a baseboard management controller, at least one graphics processing unit (GPU) module, a storage module, multiple network controllers, a universal serial bus (USB) controller, at least one serial high-speed input / output (HSI) chip, and a peripheral component interconnect standard high-speed channel (PSC) bridge. The CPU serves as the core and is connected to each functional module via a high-speed bus. By integrating a high-performance processor, a GPU, and multiple high-speed data interfaces within a standardized VPX architecture, this application solves the technical problem in existing technologies where computing modules struggle to balance computing power density, interface bandwidth, and architectural flexibility, achieving high-density heterogeneous computing and high-throughput data exchange capabilities within a compact physical space.

The invention discloses a hard disk backboard, a circuit board and electronic equipment, and relates to the technical field of electronic circuits, and the hard disk backboard comprises at least one complex programmable logic device and a hard disk slot. The complex programmable logic device is configured to be connected with the controller through a first bus and is further configured to be connected with a hard disk slot through a second bus, and the hard disk slot is configured to be connected with a hard disk. The complex programmable logic device directly obtains the hard disk state information of the hard disk, the controller does not need to intervene in control of a hard disk bottom layer, the management burden of the controller is shared through the complex programmable logic device, and management and control resources of the controller are saved. Therefore, the technical problem of low management and control efficiency of the hard disk in related technologies can be solved, and the technical effects of improving the management and control efficiency of the hard disk and improving the response rate of the system are achieved.

The invention discloses a CPLD (Complex Programmable Logic Device)-based sine and cosine encoder decoding method and device and a medium, and the method comprises the steps: executing a signal conditioning action and a dynamic setting action for an original differential signal, and obtaining a standardized setting signal; for an absolute position signal in the setting signal, calculating a corresponding initial absolute position through a preset arc tangent table, and performing scale transformation on the initial absolute position to obtain a corresponding absolute position starting point; and for increment sine and cosine signals in the setting signals, calculating corresponding subdivision position values through a preset arc tangent table, and outputting absolute position information based on a difference value between the subdivision position values at different moments through position integration. According to the invention, the precision is improved, the real-time performance is improved, the dynamic adaptability is enhanced, the system architecture is simplified, the cost is reduced, the reliability and robustness are improved, and the full-band performance is excellent.

The application relates to an expansion card timing management device, method, computer equipment and storage medium. The device comprises an expansion chip module and a complex programmable logic device arranged on an expansion card module, the complex programmable logic device is connected with a mainboard through a bus, and a power supply module is further arranged on the expansion card module, the power supply module comprises a power supply output end, and the complex programmable logic device comprises a power supply input end, a reset signal output end, a debugging signal output end and a heartbeat signal input end; the expansion chip module comprises a heartbeat signal output end, a reset signal input end and a debugging signal input end. The method can reduce the use of hardware circuits, optimize layout space and complete logic timing control.

The invention relates to the field of power electronic converter devices and technologies, in particular to a CPLD (Complex Programmable Logic Device)-based power converter front-back stage time delay circuit and a control method, aims to realize front-back stage time sequence control of a two-stage switching power supply by adopting logic devices such as a CPLD and the like, and is particularly suitable for a Buck-LLC switching power supply topological structure. According to the invention, accurate and rapid delay setting and adjustment are realized by matching a logic gate in the CPLD device with an external RC circuit. By means of the method, the occupancy rate of macro cells in the CPLD can be greatly reduced (actually measured from 83% to 55%), the overall scheme is simple and easy to implement, the development period is short, the circuit is simple, and meanwhile the stability and safety of the switching power supply converter are effectively improved.

An output power control system for a RF power source in an NNBI is provided, including a dual-core control module, including an ARM microcontroller and a complex programmable logic device CPLD chip, w