37753results about "Pump installations" patented technology

A system for the metering and delivery of small discrete volumes of liquid is comprised of a small or minimal number of inexpensive components. One such component is a movable member, such as a miniature precision reciprocating displacement pump head, which is driven by an actuator that comprises a shape memory alloy material. The operating mechanism of the system is of little or minimal complexity. The system facilitates the precise metering and delivery of the small discrete volumes of liquid. Potential applications for the system include subcutaneous, long-term, automated drug delivery, for example, the delivery of insulin to a person with diabetes. In such an application, the small, simple and inexpensive nature of the invention would allow for its use as both a portable and a disposable system.

A blower for providing a supply of air at positive pressure in the range of approximately 2 cm H2O to 30 cm H2O includes a motor, at least one impeller, and a stationary component. The stationary component includes an inlet and an outlet. The motor, the impeller, the inlet and outlet are co-axial.

A blower includes a stationary portion including an inlet and an outlet, a rotating portion provided to the stationary portion, and a motor adapted to drive the rotating portion. The inlet and outlet are co-axially aligned. The stationary portion includes a housing, a stator component provided to the housing, and a tube providing an interior surface. The rotating portion includes one or more bearings that are provided along the interior surface of the tube to support a rotor within the tube. In an embodiment, the blower is structured to supply air at positive pressure.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.