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39285results about "Pump control" patented technology

Surgical Instrument Having A Multiple Rate Directional Switching Mechanism

A surgical instrument having a remotely controllable user interface, and a firing drive configured to generate a rotary firing motion upon a first actuation of the remotely controllable user interface and a rotary refraction motion upon an other actuation of remotely controllable user interface. The instrument includes a first drive member, wherein remotely controllable user interface is selectively engageable with the first drive member, and a second drive member, wherein the remotely controllable user interface is selectively engageable with the second drive member. The instrument also includes an elongate shaft assembly operably engaged with the first drive member and the second drive member. The instrument further includes an end effector coupled to the elongate shaft assembly. The end effector includes an elongate channel configured to operably support a staple cartridge therein, and an anvil movably coupled to the elongate channel. The end effector also includes a cutting member operably supported within the elongate channel, wherein the cutting member is operably engaged with the elongate shaft assembly. The instrument is such that when the remotely controllable user interface operates the first drive member, the first actuation advances the cutting member a first distance, wherein, when the remotely controllable user interface operates the second drive member, the other actuation retracts the cutting member a second distance, and wherein the second distance is greater than the first distance.
Owner:CILAG GMBH INT

Novel massively parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:INT BUSINESS MASCH CORP
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