1483 results about "Flash memory" patented technology

The invention relates to the technical field of cores, and discloses a method and a system for realizing USB flash disk equipment interaction based on a flash memory encryption technology, which comprises the following steps of: dividing an encryptable data block of a flash memory controller, and determining a dynamic entropy weight of the encryptable data block by utilizing an equipment interaction instruction and a random noise characteristic signal; generating a self-adaptive key generation sequence capable of encrypting data blocks through an address allocation mode and a dynamic entropy weight of a flash memory controller; calculating a side channel leakage risk index of the flash memory controller, and setting a security level label of an encryptable data block in combination with a self-adaptive key generation sequence; the method comprises the following steps: setting a differentiated security protection mechanism of an encipherable data block by constructing an access control matrix of the encipherable data block and an encryption risk area of a flash memory controller; and generating a secure interaction scheme of the USB flash disk equipment based on the self-adaptive key generation sequence in combination with the differential security protection mechanism and the access control matrix. According to the invention, the interaction safety and reliability of the USB flash disk equipment can be improved.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

The invention relates to the field of computer security, and discloses a data storage security protection method and system based on a solid-state hard disk, which comprises the following steps: identifying the inherent physical difference of a flash memory chip in the solid-state hard disk so as to calculate the read-write time sequence micro-deviation of the solid-state hard disk; performing hash operation on the device root key and the unique identifier of the controller corresponding to the solid state disk to obtain a bound master control key; generating a temporary encryption key of the write-in operation to encrypt plaintext data of the host system to obtain ciphertext data; writing the ciphertext data into a flash memory physical page corresponding to the physical page address to obtain a ciphertext physical page address; when the access mode is a hostile attack mode, secretly updating the ciphertext physical page address into a new physical page address, and deleting the ciphertext physical page address; and when the access mode is a secure access mode and the verification key is consistent with the bound master control key, normal loading and data access requests of the solid state disk are allowed. According to the invention, the security and integrity of data storage can be improved.

The application provides a cache manager and a control component. The cache manager comprises an interface, an allocation module and a memory. The interface receives a cache allocation request and sends the cache allocation request to the allocation module. The interface receives first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module allocates N idle memory blocks and generates the first cache index information. The memory blocks are located in a cache, N is a positive integer, and the first cache index information comprises indexes of the N memory blocks. The memory stores indexes of at least N memory blocks. The cache manager implemented by hardware replaces the software management cache in the prior art, thereby reducing the interaction times between software and hardware when allocating a cache in the control component, improving the information interaction speed inside the control component, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.

The present application relates to the technical field of storage, and provides a method and apparatus for determining an optimal read voltage parameter of a flash memory, and a flash memory device. The method comprises: on the basis of a linear relationship model between a read retry voltage offset value and a bit flip count, acquiring a new read retry voltage offset value corresponding to a minimized predicted bit flip count of the flash memory; determining whether data can be successfully read under the new read retry voltage offset value; if yes, adding the new read retry voltage offset value to the header of a read retry offset table to form a new read retry offset table; and on the basis of the new read retry offset table, updating the linear relationship model by means of an adaptive learning model. By means of the efficient and adaptive voltage parameter determination method, the present application can improve the success rate of data recovery and reduce performance loss.

The invention relates to the technical field of intelligent power grids, and provides a remote software upgrading method for an intelligent electric energy meter, which comprises the following steps: S1, a server generates an upgrading package containing a version identifier, and transmits the upgrading package to the intelligent electric energy meter in a fragmented manner through a TLS encryption channel; s2, the intelligent electric energy meter doubly verifies the integrity of the upgrade package and the legality of the source through an SHA-256 check code and a digital signature, the upgrade package and the source legality are written into a backup storage area of the Flash memory after verification is passed, and a CRC write-in check value is recorded; s3, performing secondary verification on the upgrade package of the backup storage area, triggering restarting after verification is passed, and writing data of the backup area into the main partition in the restarting process; s4, if the main partition system is not started or the core function is abnormal within the set time, returning to an old version and generating a fault log containing a timestamp; through a dynamic subpackage strategy, differential upgrading, SHA256 verification, a watchdog mechanism and a fault log record, the upgrading efficiency and safety of the intelligent electric energy meter are remarkably improved, and the dynamic subpackage strategy dynamically adjusts the size of a data packet according to the network condition.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention relates to the technical field of hard disks, in particular to a data protection method of a solid state disk and the solid state disk, the method comprises the steps that a flash memory medium is divided into a data block area, a log block area and a metadata area, and the metadata area comprises a mapping directory, a mapping block and a check point block; a block mapping table and a log page mapping table are established in a volatile memory, and dbMSN and lbMSN are stored. Adding write-in data to a log block page, updating a log page mapping table, and generating check points according to full writing of a log area. When no free page exists, the damaged log blocks are selected in a rotating mode to be combined, new data block migration pages are distributed, mapping is updated, the MSN is progressively increased, changes are written into the mapping blocks, and the mapping catalogue is updated when the mapping blocks are addressed. After restarting, positioning a mapping block by a mapping directory to recover block mapping, reading check points in a reverse order, and traversing an uncovered log area to reconstruct log page mapping; and comparing the dbMSN with the lbMSN, setting inconsistent log pages to be invalid, establishing consistent access and shielding invalid pages. According to the method and the device, the problems of data consistency and availability caused by metadata loss, uncertain merging state and low recovery efficiency of the hybrid mapping FTL in a crash scene can be solved.

The invention relates to the technical field of electric digital data processing security, and discloses a solid state disk data encryption method and a solid state disk. According to the method, a national cryptographic algorithm hardware encryption and decryption co-processing module is serially arranged on a data bus between a main control chip and a flash memory particle array, so that transparent encryption of write-in data and transparent decryption of read-out data are realized; the module performs encryption and decryption based on an SM4 algorithm and an XTS advanced encryption standard mode in combination with a logic address as an adjustment value, and securely injects a root key through an out-of-band interface to derive a data key. The system comprises a main control chip, a flash memory array and the co-processing module, wherein the co-processing module is integrated with a hardware encryption and decryption engine, a key management unit and data flow control logic. On the premise that a general main control chip is not changed, high-performance, high-compatibility and high-security national cryptographic hardware-level full-disk encryption is realized.

A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

The invention discloses a collaborative authentication method of a safety U disk, which comprises the following steps of: when the safety U disk is inserted into a host for the first time, executing a set read-write sequence on a flash memory storage array of the safety U disk, and acquiring a PUF (Physical Unclonable Function) site of the safety U disk; reading a power-on initial state image of an SRAM (Static Random Access Memory) of an internal controller of the safe USB flash disk when the safe USB flash disk is powered on, and carrying out Hash abstract processing to generate a controller fingerprint abstract of the safe USB flash disk; when the security USB flash disk is authenticated, the host randomly generates a random number, maps the random number into a PUF bit address index and generates a PUF response of the security USB flash disk; combining the controller fingerprint abstract and the PUF response of the secure USB flash disk to obtain a session key; and realizing cooperative authentication of the secure USB flash disk according to the session key. The invention also discloses a system for realizing the collaborative authentication method of the safety USB flash disk. According to the invention, cooperative authentication of the safe USB flash disk is realized, and the reliability is higher and the safety is better.

The application provides a CPU platform fault log recording method and device, comprising: receiving the running log data stream output by the CPU debugging serial port in real time; collecting the sampling value of the key power supply voltage and monitoring the hardware signal line to obtain the restart event signal and the shutdown event signal; packaging into a structured log recording unit; and writing the compressed log data block back to the flash memory; in response to the external reading instruction, reading the log data block from the specified log area of the flash memory and transmitting to the host end diagnostic tool; reorganizing and displaying in time sequence for fault analysis. The application can construct a log recording channel completely independent of the main CPU and operating system without increasing any additional hardware cost, ensuring that even in the most extreme system failure scenario, the complete context information at the fault moment can be reliably saved, thereby greatly improving the diagnosis efficiency and accuracy of the occasional fault.

The invention provides a brightness calibration coefficient storage method, a related device and a storage medium. The method comprises the following steps: acquiring an actually measured brightness value of each pixel in the display panel; dividing the display panel into a plurality of initial blocks, and calculating the variance of the actually measured brightness value of each initial block; recursively merging the adjacent initial blocks and / or merged blocks until the variance of the actually measured brightness values of the merged blocks is greater than a preset threshold value; according to a preset storage structure, the brightness calibration coefficient of each block is stored with the block as the unit, and the brightness calibration coefficient comprises the base value of the actually measured brightness value of each block and the difference matrix. According to the embodiment of the invention, the storage space required by the brightness calibration coefficient of the display panel is reduced, so that the space occupation of an external flash memory and an on-chip buffer is reduced, and the layout design difficulty in the display panel is reduced.

The invention discloses a satellite-borne equipment embedded system software on-orbit reconstruction method and a satellite-borne equipment embedded system. The method comprises the following steps: partitioning a FLASH memory of a microcontroller of satellite-borne equipment into a region, a BootLoader boot program region and an application program storage region; an independent BootLoader bootstrap program is solidified in the BootLoader bootstrap program area in advance; receiving a program file subpackage from a satellite service computer during on-orbit operation; a two-stage reliable transmission protocol including sequential receiving and packet supplementing receiving is adopted to receive a program file, wrong and missing packets are received and dynamically recorded in the sequential receiving stage, and only the wrong and missing packets are selectively retransmitted in the packet supplementing receiving stage; according to an instruction of the satellite service computer, the received complete program file is verified, the program file is written into the application program storage area after passing the verification, updating is completed, the BootLoader bootstrap program jumps to the updated application program, and on-orbit reconstruction is completed.

A method of forming a semiconductor includes bonding a first memory die to a first memory-controller die to form a first bonded assembly, bonding second memory die to a second memory-controller die to form a second bonded assembly, and bonding the first bonded assembly to the second bonded assembly to form a memory stack.

The invention belongs to the technical field of avionics system design, and particularly relates to an integrated task computer and a backup upgrading method thereof. The comprehensive task computer comprises a core processor and a FLASH memory, the FLASH memory is provided with a starting mirror image file and an application mirror image file from low to high according to addresses, the starting mirror image file is internally provided with a first boot loader, a first PL end bit stream and a system configuration program from low to high according to the addresses, and the application mirror image file is internally provided with a second boot loader, a second PL end bit stream and a system configuration program from low to high according to the addresses. The system configuration program is internally provided with a bootstrap program of the application mirror image file and an identification module for identifying whether the application software is upgraded or not; and the application mirror image file is provided with a second boot loader, a second PL end bit stream and an application software program from low address to high address. According to the invention, the online upgrading function of the equipment master control software and the underlying firmware thereof is realized, and the stability and convenience of the system are enhanced.

The embodiment of the invention provides a flash memory testing method, electronic equipment and a computer readable storage medium. The method comprises the following steps: acquiring particle type information of a to-be-detected flash memory product; determining at least one flash memory operation mode according to the particle type information; aiming at any flash memory operation mode, performing erasing operation on each flash memory block in the flash memory product to be detected under a preset temperature condition; under the condition that the flash memory blocks are successfully erased, performing read operation on the flash memory pages in the corresponding flash memory blocks to obtain the total number of error correction codes and the total number of code words; and comparing the error correction code average value with a corresponding preset test threshold value so as to carry out grading screening processing on the corresponding flash memory blocks. According to the scheme of the embodiment of the invention, the test of the flash memory product can be more refined and more accurate.

The invention relates to the technical field of digital storage, and provides a method and a system for recovering long-term storage failure of a mobile terminal, through the design of a built-in independent power supply, a startup disk can still supply power continuously when the mobile terminal is in a power-off state, and the limitation of traditional OTG (On-The-Go) equipment is broken through. The read-write state of the data block of the flash memory chip is automatically monitored through the storage controller, and a health report is generated in real time; and when the early warning data block is detected, a bidirectional communication protocol is triggered. In a data backup link, a boot disk adopts a hierarchical check mechanism to generate CRC codes for each data block for centralized storage, and meanwhile, an overall SHA-256 code is calculated and double-end synchronization is performed. And in the recovery stage, the backup integrity is ensured through SHA-256 code comparison, then the data accuracy is verified block by block through CRC codes, and finally, the backup file is automatically migrated to the nonvolatile partition. The seamless closed loop from fault detection to data recovery is realized aiming at the system guidance problem after long-term storage of the equipment.

The invention relates to the technical field of computer storage, and discloses a test strategy for improving the read-write performance stability of an SSD (Solid State Disk), and the strategy comprises the following steps: obtaining the current available capacity of an SLC cache of the SSD; based on the obtained current available capacity, setting a total data volume used by a performance stability test, so that the total data volume is smaller than the current available capacity; and executing the performance stability test on the solid state disk by adopting the set total data volume so as to obtain performance data capable of reflecting the hardware stability of the solid state disk. The real-time available capacity of the SLC cache is obtained through the standard interface before the test, and the test data volume is set by taking the real-time available capacity as the rigid basis. By means of the method, precise stripping and evaluation of the performance stability of the solid state disk hardware are achieved, and the test result can truly reflect performance fluctuation caused by hardware components such as a master control or flash memory particles.

A system includes a plurality of application processors (APs), a plurality of flash memory devices associated with the plurality of APs, and a plurality of multiplexers, each to selectively couple a flash memory device of the plurality of flash memory devices to an AP of the plurality of APs. A controller is operatively coupled to the plurality of multiplexers and provides a trusted execution environment to execute a virtual root of trust (vROT) application for each respective AP of the plurality of APs. Each vROT application accesses a corresponding one or more of the plurality of flash memory devices via a corresponding one or more of the plurality of multiplexers.

The invention relates to the technical field of memory test, and provides a test system for a parallel interface NOR FLASH memory, which comprises the following steps of: acquiring verification information of test data of a test data block in a storage area and verification operation in a test process of the NOR FLASH memory, and judging whether the test data block has an error or not; dividing the test data blocks with errors, and determining secondary to-be-analyzed test data blocks; the method comprises the following steps: marking target test data, identifying high-frequency error test data, dividing a secondary to-be-analyzed test data block needing to be adjusted into a tertiary to-be-analyzed test data block, and repeatedly judging and dividing until the data block cannot be continuously divided or the judgment result of the data block is that the data block is not divided, thereby realizing the setting of a block verification mode of a full-step method. And evaluating the durability of the NOR FLASH memory of the parallel interface by using a one-step method. According to the invention, a block verification mode can be adaptively set, and the accuracy of a durability test result is improved.

The embodiment of the invention provides a flash memory processing failure processing method and system, computer equipment and a storage medium, and relates to the technical field of flash memory process.The method comprises the steps that the write operation return state of first flash memory data written into a first physical block is obtained; when the write operation return state is a failure state, obtaining first flash memory data in the internal cache of the flash memory, storing the first flash memory data in the main control cache, and erasing the first flash memory data in the internal cache of the flash memory; and writing the first flash memory data stored in the main control cache into a second physical block, wherein the second physical block is a healthy physical block. According to the embodiment of the invention, the write failure of the flash memory can be processed, the data security of the flash memory is ensured, and a master control buffer does not need to be additionally occupied. And when writing failure occurs, reading buffer data cached in the flash memory, and re-writing the buffer data into the healthy flash memory physical block. According to the method, the flash memory writing failure can be effectively processed, the data security is ensured, the occupation of a main control memory buffer of the flash memory can be reduced, and the cost is reduced.

The invention discloses a mapping table storage method and device, computer equipment and a storage medium, and relates to the technical field of data storage, and the method comprises the following steps: determining a target logic block group corresponding to a target mapping entry and a preset attribute of the target logic block group; and if the preset attribute is a first preset value, writing the target mapping entry into a first preset cache space, screening the target mapping entry and other mapping entries according to the writing sequence of the target mapping entry and the writing sequence of other mapping entries, and storing the screened mapping entries into a flash memory. The problem that in the process of brushing an L2P mapping table to a flash memory, invalid mapping entries are written into the flash memory as well, and consequently bandwidth and storage resources are wasted can be solved. According to the method, the mapping entries are screened, only the screened mapping entries are stored in the flash memory, invalid mapping entries are successfully reduced, and in the process of storing the mapping table in the flash memory, bandwidth occupation is reduced, and the space occupied by the mapping table in the flash memory is reduced.

The embodiment of the invention provides a method for determining read reference voltage of a flash memory and a related device, when the offset degree value of the optimal value and the default value of the (i-1) th read reference voltage exceeds a first threshold value and the optimal value is smaller than the default value, in a threshold value distribution curve corresponding to the ith read reference voltage, the (i-1) th read reference voltage is determined to be the (i-1) th read reference voltage. Searching a wave trough on the left side of the default value of the i-th read reference voltage as an optimal value of the i-th read reference voltage; when the deviation degree value of the optimal value and the default value of the (i-1) th read reference voltage exceeds a first threshold value and the optimal value is greater than the default value, searching a trough on the right side of the default value of the ith read reference voltage as the optimal value of the ith read reference voltage; and when the deviation degree value of the optimal value of the (i-1) th read reference voltage relative to the default value does not exceed the first threshold value, searching the voltage of the trough closest to the default value of the i-th read reference voltage as the optimal value of the i-th read reference voltage. The accuracy of the determined optimal value of the read reference voltage can be improved.

The invention discloses a flash memory grade test method, device and equipment and a medium. The method comprises the following steps: acquiring real-time test values respectively corresponding to flash memory core parameters and test environment parameters of flash memory equipment; wherein the flash memory core parameters comprise erasing times, and the test environment parameters comprise temperature parameters; performing normalization operation based on the real-time test value to obtain a normalized weight coefficient; dividing a preset value interval to obtain a plurality of weight subintervals, and determining a target original bit error rate grading threshold list based on the normalized weight coefficient and the plurality of weight subintervals; and obtaining a real-time original bit error rate, and determining a target flash memory level of the flash memory device based on the real-time original bit error rate and the target original bit error rate grading threshold list. According to the technical scheme, the dynamic influences of the flash memory core parameters and the test environment parameters are integrated, a real-time dynamic grading mode is constructed, and accurate judgment of the flash memory grade of the flash memory equipment is achieved.

The invention discloses a hard disk data pre-reading method and device, equipment and a storage medium, and relates to the technical field of solid state disks. According to the method, the target moments, the read-write modes of the target moments, the sizes of the target data blocks and the logic initial addresses of the target data blocks are combined, so that the predicted initial addresses of the to-be-read data blocks corresponding to the prediction moments can be accurately determined; the problem of inaccurate initial address prediction caused by analysis of a single historical access mode is solved. Meanwhile, based on the predicted initial address corresponding to any target to-be-read data block in the to-be-read data blocks, the data block data corresponding to the predicted initial address is read from the flash memory of the hard disk and stored in the cache of the hard disk, the data reading speed can be increased, and the overall performance of the hard disk is improved.

The invention provides a firmware upgrading system and method supporting real-time state monitoring and resisting power failure, and relates to the technical field of industrial Internet of Things, the firmware upgrading system comprises a storage module, a power failure protection module and a processing module, the storage module comprises an on-chip FLASH memory and an off-chip NOR FLASH memory, the on-chip FLASH memory is used for being divided into a BOOT area, an APP area and an upgrading parameter storage area, and the processing module is used for processing the on-chip FLASH memory and the off-chip NOR FLASH memory. The off-chip NOR FLASH memory is used for dividing the off-chip NOR FLASH memory into a BANK1 region and a BANK2 region; according to the invention, a data redundancy guarantee is provided for firmware upgrading through a double-region backup mechanism of the storage module; the hardware power-off detection and super capacitor energy storage design of the power-off protection module avoids data loss and storage structure damage at the power-off moment from the hardware level; accurate data recording and recovery strategies of the processing module ensure accurate recovery and upgrading after power failure.

The invention discloses an ROM (Read Only Memory) patching method and system based on RAM (Random Access Memory) and hardware interruption. The method comprises the following steps of: defining and configuring a digital module register command, and integrating the command into a chip ROM (Read Only Memory) code; the external main control equipment writes the patch program into a specified address of a chip RAM through a write-in RAM command, and configures a digital module register parameter; configuring a digital module register enable bit, and starting the digital module to work; the digital module monitors that the PC value of the CPU is matched with the PC value triggered by the patch in real time, and the PC value is triggered to jump to the RAM address where the patch program is located; the CPU executes the patch program in the RAM; skipping to an end address of the original ROM program before the patch program is executed; and recovering the program to execute the ROM code. Through the combination of the digital module and the RAM, the cost limitation of a traditional flash memory patch and the complexity of a software strategy are broken through, and the method has remarkable advantages in the aspects of low cost, high real-time performance and flexible adaptability.

The invention discloses a server startup fault maintenance method and system, a storage medium and a computer program product, and relates to the technical field of servers, the method comprises the following steps: setting a backup system address request flag bit under the condition that a main basic input / output system of a server is interrupted by trigger software; the backup system address request flag bit is transmitted to a main control core, the main control core obtains backup system address information from a pre-stored backup system firmware program according to the backup system address request flag bit, and the backup system firmware program and a substrate management controller firmware program are stored in the same flash memory chip in a partition mode; reading backup system firmware resources pointed by the backup system address information; the backup system firmware resources are mapped to the control chip set, the control chip set reads the backup system firmware resources to conduct hardware initialization, and the server is guided to be started. Server startup failure maintenance which is highly reliable and is not affected by in-band server failures is achieved at low cost.