365 results about "Serial Peripheral Interface Bus" patented technology

The invention relates to the technical field of computers, and discloses a server asset information reporting method, device and equipment and a medium, the method is used for a server, and a basic input / output system in the server is connected with a baseboard management controller through an enhanced serial peripheral interface; the method comprises the following steps: obtaining each piece of asset information of a server and the priority of each piece of asset information; applying for a shared memory from the baseboard management controller to obtain a target position corresponding to each piece of asset information of the server in the shared memory; and according to a corresponding relationship between the starting stages of the server and the priorities of the asset information, reporting the asset information to a target position in the shared memory in each starting stage of the server. According to the invention, the efficiency of reporting the asset information of the server can be improved.

An information handling system includes a hardware processor, a memory device operatively coupled to a serial peripheral interface (SPI) chip and the hardware processor. The SPI chip interfaces the hardware processor executing plural stages of boot modules during a boot process of the information handling system with allocated, reserved portions of the memory device for each stage of boot module executed in pre-boot, boot, and runtime via a virtual memory interface generated by execution of an original equipment manufacturer (OEM)-defined agnostic memory allocation module. The hardware processor executes the OEM defined agnostic memory allocation firmware to redefine the virtual memory interface for each allocated reserved portion of the memory device at each of the plural stages of the boot modules that are executed from pre-boot, through boot, and to runtime to provide adjustments to allocated, reserved portions of memory for later stages of executed plural stages of the boot modules.

The invention discloses a distributed photovoltaic power quality monitoring method. The method comprises the following steps: acquiring original waveform data of the Internet of Things in real time through a serial peripheral interface; calculating cyclic wave voltage amplitude, cyclic wave harmonic voltage and / or current amplitude, inter-harmonic voltage and / or current amplitude, harmonic active power, positive sequence, negative sequence and zero sequence components of voltage and / or current and unbalance degree according to the original waveform data; and calculating an instantaneous flicker value through a filter according to the original waveform data, and carrying out transient rise, transient drop and interruption event monitoring according to the original waveform data. According to the invention, the technical problems of how to monitor the electric energy quality quickly in real time and how to calculate the frequency deviation in real time are solved.

The present invention relates to an ultra-wideband (UWB) radar sensor chip system architecture. The chip system architecture at least comprises N receiving channels and N transmitting channels, wherein N is a positive integer greater than 1, the N receiving channels form receiving links by means of connecting to a receiver multiplexer, the N transmitting channels form transmitting links by means of connecting to a transmitter multiplexer, and the receiving links and the transmitting links jointly form N groups of transceiving systems. The chip system architecture further comprises a serial peripheral interface, and is adjacent to an external main control chip by means of the serial peripheral interface, so as to drive, by means of a control command, the N groups of transceiving systems to operate on the basis of time division or to operate independently. The present invention introduces the concepts of time division multiplexing and multi-channel synthesis into a radar system, and provides a universal UWB radar sensor chip system architecture with a high integration level, a high performance and a low cost, thereby effectively solving the problems of a radar chip in terms of the sensitivity and transmitting power, improving the detection precision and increasing the detection distance.

The invention discloses a liquid crystal display brightness adjusting system and method based on ambient light perception, and the system comprises a high-precision ambient light sensor which obtains the ambient light illuminance and color temperature data in real time; the analog-to-digital converter is used for converting the analog optical signal into a digital signal; an embedded microcontroller; the temperature sensor is tightly attached to the liquid crystal panel backlight unit; and the control input end of the liquid crystal driving chip is connected with the driving signal output end of the embedded microcontroller through a serial peripheral interface bus. The technical normal form of a liquid crystal display dimming system is fundamentally reconstructed: in a physical layer, photoelectric signals and human eye spectral response offset are corrected through a spectral separation mechanism, a carrier recombination effect is inhibited based on a thermodynamic equation, and the physical authenticity of brightness output is ensured; in a control layer, a motion state compensation model and a spatial topology perception algorithm are constructed, and brightness space-time consistency control in a dynamic scene is realized.

The invention provides a data transmission method and device, equipment and a storage medium. The data transmission method is applied to the controller, at least two buffer areas are arranged in the controller, and the data transmission method comprises the steps that in response to starting of a first timer, CAN data sent by external equipment through a CAN controller local area network bus is stored in the buffer area in an idle state in the at least two buffer areas; in the process of storing the CAN data through the buffer area in the idle state, forwarding the CAN data stored in the buffer area in the occupied state in the at least two buffer areas through a serial peripheral interface (SPI) bus; wherein the data transmission rate of the CAN bus is smaller than that of the SPI bus.

The invention relates to the technical field of electronics, in particular to a system for reading an external chip based on an SPI (Serial Peripheral Interface), which comprises a parameter configuration module, an external clock input module, an external parameter input module and an SPI signal generation module which are integrated on an FPGA (Field Programmable Gate Array), wherein the parameter configuration module, the external clock input module and the external parameter input module determine the state of a signal line in the SPI signal generation module according to the state of an external chip and the address of to-be-read data in the external chip, further read the to-be-read data from the external chip and transmit the to-be-read data to other external data receiving modules; according to the SPI signal generation module, the receiving and transmitting sequence of high and low levels on each signal line in the SPI signal generation module is flexibly customized, the SPI signal generation module adapts to different address bit widths and receives different data bit widths, and the SPI parameter reading requirements of different external chips can be more widely met.

The invention relates to the field of hardware control, and provides a device and method for outputting a running log of a basic input / output system based on a virtual serial port, and the device comprises a substrate management controller which is provided with a first virtual serial port control module, the receiving module is used for receiving serial port data sent by a host through an enhanced serial peripheral interface bus; a first virtual serial port driving module and a second virtual serial port control module are arranged on a south bridge chip of the host, and the first virtual serial port driving module is used for sending operation log information to the first virtual serial port control module through an enhanced serial peripheral interface bus; the second virtual serial port control module is used for outputting the running log information to a text file under the universal serial bus flash disk when the existence of the universal serial bus flash disk is detected; and the enhanced serial peripheral interface bus is connected between the first virtual serial port control module and the first virtual serial port driving module and is used for mutually transmitting data between the first virtual serial port control module and the first virtual serial port driving module.

The automatic parameter adjusting method of the SPI controller comprises the steps that pulse excitation is conducted on an SPI bus, waveform response data are collected, and a bus characteristic mapping table is generated; sending a self-checking instruction sequence to different batches of target devices, and generating a device characteristic mapping table; intermediate configuration parameters are determined and verified, and transition configuration data are generated; obtaining interference event data and voltage monitoring data, and performing waveform adjustment on the clock signal to generate interference suppression data; performing statistics on the bit error rate data and the delay data of the target device to generate device aging trend data; and grouping the target devices based on the device characteristic similarity, and executing parallel access control. According to the invention, in industrial-grade edge computing equipment, environmental factors such as temperature fluctuation, power supply peak and electromagnetic interference can be handled, the problem of real-time data interaction of devices with different batches and process levels is solved, the aging phenomenon of the devices along with time lapse is handled, and intermittent errors or large-scale communication faults occurring during high-load access are avoided.

The invention provides a development board based on a secure real-time bus SRB chip, and relates to the technical field of power electronics. The development board comprises any one or more of an SRB real-time single-twisted pair 100M Ethernet interface, an SRB real-time standard gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration universal asynchronous receiver / transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface and a power supply interface. According to the method, not only is the security bus characteristic test of the SRB chip concerned, but also other key function modules (such as an Ethernet interface, a memory interface, a serial peripheral interface and the like) are covered, so that a developer can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the security bus part.

The invention relates to the technical field of coherent optical communication, in particular to a Dither signal generation and feedback acquisition circuit and method and a coherent optical module, and the circuit comprises an MCU and a DAC chip. The MCU comprises a disturbance generator, an SPI (Serial Peripheral Interface), an on-chip ADC (Analog to Digital Converter), an automatic bias controller and two DMA channels; the first DMA channel, the SPI interface and the DAC chip are connected in sequence, the disturbance generator is connected with the SPI interface, and the DAC chip is connected to a laser and used for sending Dither signals to the laser; the on-chip ADC is connected with the second DMA channel and the laser and used for collecting feedback signals under driving of the second DMA channel, and the on-chip ADC is sequentially connected with the automatic bias controller and the disturbance generator and used for sending optimized and adjusted Dither signal parameters to the disturbance generator. The running efficiency of the MCU can be improved, and the internal resource utilization rate of the MCU is also improved.

The invention discloses an FPGA (Field Programmable Gate Array) board card upgrading method and system, the method is applied to a system in which an FPGA board card and a CPU (Central Processing Unit) are interconnected through PCIE (Peripheral Component Interface Express), and the method comprises the following steps: in the running process of a CPU operating system, loading an SPI (Serial Peripheral Interface) driver and an MTD (Multimedia Transfer Device) driver through a preset command; calling a preset registration code by the PCIE equipment driver, and registering an SPI controller to call the SPI driver; the SPI drive calls the MTD drive and is connected with an SPI flash memory; the MTD driver generates a corresponding MTD block device under a specified directory; and the CPU operating system sends an FPGA board card upgrading program to the MTD block device, and the MTD block device programs the FPGA board card upgrading program into the SPI flash memory so as to complete FPGA board card upgrading. According to the FPGA board card upgrading scheme provided by the invention, remote upgrading of the FPGA board card can be realized.

The invention relates to an operation log recording method, device and equipment based on an SPI mechanism. The method comprises the steps that a loading operation log package is started, and log variable parameters are read; starting a log component to form log information, and determining a log dropping mode according to the number of logs to be processed; scanning, loading and defining an SPI function, and dropping the to-be-processed log into a disk according to the log dropping mode; a monitor is initialized, and whether the system runs normally or not is judged through the monitor. At least code readability and maintainability can be improved, memory consumption is reduced, performance is improved, and compatibility is improved.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention relates to the field of storage, in particular to an automatic configuration method and system for RAID (redundant array of independent disks) cards. The problems that in the prior art, an RAID card cannot be pre-configured, misoperation is prone to occurring in the manual configuration process, and the labor cost is high are solved. The method comprises the following steps of: storing default automatic virtual disk creation and configuration data of an RAID (Redundant Array of Independent Disks) card in a serial peripheral interface flash memory; two M.2 SSD system disks with the same model and the same capacity and a microprocessor MCU are arranged in the RAID card; the configuration management module is responsible for executing an automatic configuration process, and automatic configuration is set and triggered under the condition that the hardware requirement and the triggering time are met; the automatic configuration of the RAID card is realized; the complex operation of manual creation of a user is greatly reduced, consideration of human-caused faults is reduced, the requirement for automatically configuring the RAID is provided, the process is achieved through automatic configuration, and the purpose of instant use after power-on is achieved.

The invention discloses a serial-parallel conversion method and a folding screen terminal. In order to reduce the number of cross-screen signal lines, the invention provides a serial-parallel conversion method which comprises the following steps: a processor sends parallel multi-path protocol signals to a first chip; the first chip is used for converting parallel multi-path protocol signals into serial SPI (Serial Peripheral Interface) signals; the serial SPI signals are sent to a second chip through a cross-screen signal line; the second chip converts the serial SPI signals into parallel multi-path protocol signals; the parallel multi-path protocol signals comprise an SPI signal, an I2C signal, an I2S signal and a GPIO signal; the first chip is located below the first screen, and the second chip is located below the second screen. The number of the cross-screen signal lines is small, cross-screen communication can be achieved through the same chip, and the comprehensive cost is reduced. The method is suitable for the communication field.

A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

The embodiment of the invention provides a system-on-chip for communication between an AUTBUS and an SPI slave module. The system-on-chip comprises a system bus, wherein an AUTBUS module and the SPI slave module are hung on the system bus; wherein an AUTBUS cache and an AUTBUS arbitration module are arranged in the AUTBUS module, and an SPI write cache and an SPI read cache are arranged in the SPI slave module; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from an AUTBUS cache and sends the cache data to an SPI slave module in a direct memory access (DMA) mode, and the SPI slave module receives the cache data from a system bus and writes the cache data into an SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to an SPI slave module, the first read request comprises a target data length, and the SPI slave module reads cached data of the target data length from an SPI read cache and sends the cached data to the AUTBUS; therefore, the communication between the AUTBUS module and the SPI slave module can be realized, and the communication efficiency between the AUTBUS module and the SPI slave module is improved.

The embodiment of the invention relates to the technical field of communication, in particular to a FLASH extended space read-write access method based on a domestic Feiteng E2000Q processor, which comprises the following steps of: in the aspect of hardware, respectively hanging a plurality of FLASH chips in different chip selection spaces of a QSPI (Query Serial Peripheral Interface) controller of the domestic Feiteng E2000Q processor, providing clock signals for each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed; in the aspect of software, when FLASH erasing, reading or programming operation needs to be carried out, selection of different FLASH chips is achieved in the mode that FLASH chip selection parameters are transmitted to a chip selection register of the QSPI controller, and read-write access operation is achieved in the mode that FLASH addresses are transmitted to an address register of the QSPI controller. Read-write operation of the high-order data and the low-order data in the same address space is achieved in a data splicing and analyzing mode. According to the method, the flexibility of the domestic Feiteng E2000Q processor in the aspects of application program solidification and FLASH address space allocation is well improved.

The invention relates to a configuration method and device compatible with a multi-topological structure GPU server and a storage medium, and the method comprises the steps: controlling a first programmable logic chip of a GPU node to obtain topological structure information of the GPU server, setting the gating of a total multiplexer based on the topological structure information of the GPU server and a gating truth table, and according to the gating of the total multiplexer, carrying out the configuration of the GPU server. And determining the gating type of the total nonvolatile memory, and loading the corresponding firmware file from the corresponding total nonvolatile memory through the serial peripheral interface of the switching chip according to the gating type of the total nonvolatile memory so as to configure the PCIe port of the switching chip, thereby configuring the GPU server, and a serial peripheral interface of the switching chip is connected with a plurality of total nonvolatile memories. According to the scheme provided by the invention, the firmware file required by an actual topological structure can be adaptively switched to start and complete configuration in the whole process from server assembly completion, power-on to startup, so that the production efficiency is improved, and the development cost is saved.

The invention relates to a broadband 1GHz-8GHz 8 * 8 full-switching matrix board card, which belongs to the technical field of satellite communication, and comprises power division unit groups, switch unit groups and an MCU (Microprogrammed Control Unit), the two power division unit groups are arranged above the switch unit groups, the signal input end of the switching board card is connected with the signal input ends of the power division unit groups through radio frequency cables, and the signal input end of the switching board card is connected with the signal input ends of the switch unit groups through radio frequency cables. The signal output of the power division unit group is connected with the signal input end of the switch unit group through a BMA blind plugging connector, and the output end of the switch unit group is connected with the signal output end of the switching board card through a radio frequency cable; wherein the power division unit group is used for uniformly distributing the input radio frequency signal power to the input ports of the plurality of switch units, and the power division unit group adopts a GaAs power division chip to realize the power distribution of the broadband from 1GHz to 8GHz; the switch unit group is used for selecting an input signal for output according to a control signal, and the switch unit group is controlled through an SPI signal; and the MCU control unit is used for converting an external serial port control signal into an SPI (Serial Peripheral Interface) signal so as to control the signal path selection of the switch unit group.

The embodiment of the invention discloses a closestool and an ink display screen display control method and device. The closestool comprises a base, a cover plate, at least one sensor, a wireless communication module, a control module and an ink display screen, the sensor is used for acquiring data and sending the acquired data acquired by the sensor to the control module; the control module is used for receiving the sensor acquisition data sent by the sensor and the function setting data sent by the wireless communication module, and controlling the ink display screen to display information according to the sensor acquisition data and the function setting data; and the ink display screen is connected with the control module through a serial peripheral interface and is used for displaying information under the control of the control module. According to the technical scheme, the problems that an existing closestool display screen is high in display power consumption and hurts eyes are solved, the sensor and function setting information of the closestool can be displayed through the ink display screen, the visibility of the ink display screen under strong light is good, and the display effect is improved.

Systems and methods for flash arbitration in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices, and a flash memory external to the heterogeneous computing platform and coupled to the plurality of devices via a Serial Peripheral Interface (SPI) controller, where the heterogeneous computing platform comprises a flash arbitration circuit coupled between the SPI controller and the plurality of devices, and where the flash arbitration circuit is configured to arbitrate access to the flash memory among the plurality of devices.

The invention provides a system, method and device for updating FPGA firmware online. The method comprises the steps that a processor module outputs a control signal of a first level state to a switching control module through a universal input and output interface; the switching control module responds to the control signal of the first level state and establishes a first communication path between the serial peripheral interface of the processor and the storage module; writing the update data stream into the storage module through the first communication path; after the update data stream is written, establishing a second communication path between the FPGA module and the storage module; and the processor module sends a start loading command to a configuration register of the FPGA module, and triggers the FPGA module to read and load the update data stream from the storage module through the second communication path so as to complete online update of firmware. According to the method, the equipment maintainability in a scene with high reliability requirements is improved, the operation and maintenance cost and the time overhead are remarkably reduced, and meanwhile, the continuity and the availability of key system services are ensured.

The invention discloses a method for simultaneously realizing TBOX and IVI functions in an SOC (system on chip), which comprises the following steps: at least running a TBOX partition and an IVI partition on the SOC, and binding different kernel resources to the TBOX partition and the IVI partition; in the TBOX partition, TBOX software communicates with the wireless module through an interface, and meanwhile, a UART interface is adopted to perform connection and data interaction with the microprocessor; in the IVI partition, each piece of IVI software is in connection and data interaction with the microprocessor through an SPI (Serial Peripheral Interface); and the microprocessor carries out isolation processing on services of the TBOX partition and the IVI partition. The invention further discloses a corresponding system, device and vehicle. By implementing the method, the TBOX and IVI functions can be realized in the SOC, and the TBOX and the IVI are isolated from each other and do not influence each other during operation, so that the cost can be saved and the safety can be improved.

Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.

The invention relates to the technical field of CPLD upgrading, and discloses a CPLD remote online upgrading method and system based on SPI communication and electronic device.The method comprises the steps that binary format data of a CPLD upgrading file is transmitted to a main control chip through a CAN communication protocol, and upgrading data is obtained; and the master control chip transmits the upgrade data to the CPLD by using an SPI communication protocol, receives and writes the data, and completes remote online upgrade of the CPLD. The CPLD is upgraded based on the SPI communication protocol, dependence on a traditional programmer is eliminated, the system can be automatically upgraded during normal operation, manual intervention or shutdown is not needed, the efficiency and flexibility of system maintenance are improved, and the reliability and stability of the system are enhanced. Compared with a traditional JTAG interface, the SPI protocol supports full-duplex communication, and the transmission rate is higher, so that data transmission can be completed more quickly, and the system upgrading time is shortened.

A disclosed method monitors boot path driver events to identify faulty boot path drivers in a UEFI-compliant boot path. Upon identifying a faulty boot path driver, the faulty driver is isolated and a corresponding remediation driver is fetched. An override driver dispatch list is created by modifying an original driver dispatch list to replace the faulty driver with the remediation driver, wherein the remediation driver occupies the same place in the execution order of the override driver dispatch list as the faulty driver occupies in the original driver dispatch list. Following a warm reset, a boot path load is performed in accordance with the override driver dispatch list, thereby remediating the boot path without performing a firmware update on a serial peripheral interface (SPI) flash device or the like. In this manner, a faulty driver is detected, isolated, and remediated in a single boot path.

The invention relates to the technical field of sonar emission signal source systems, in particular to a sonar emission signal source system based on a DDS and a working method. Comprising an ARM end, a main control circuit and a transmitting circuit, the ARM end is connected with the main control circuit, the main control circuit is connected with the transmitting circuit, the ARM end issues a working parameter instruction to the main control circuit, the main control circuit generates a corresponding waveform signal after receiving and analyzing the instruction, and the waveform signal is filtered through the transmitting circuit; the working parameters sent by the ARM end comprise center frequency, bandwidth and pulse width; the main control circuit uses an FPGA (Field Programmable Gate Array) as a main controller, the FPGA main control circuit adopts an XC6SLX16 / 25-2FTG256 chip, and the FPGA main control circuit is also connected with a 50MHz clock crystal oscillator, a serial SPI (Serial Peripheral Interface) configuration chip, a low-dropout voltage-stabilizing chip and a JTAG (Joint Test Action Group) interface; and the low-dropout voltage-stabilizing chip provides voltage for the system. A direct digital frequency synthesizer (DDS) technology is used, corresponding single-frequency signals or LFM signals can be generated according to received instructions of parameters such as frequency, bandwidth and pulse width of a working center, and application requirements of special occasions are met.

The application provides a circuit based on a beamforming chip serial peripheral interface, a beamforming chip and a radio frequency front end, comprising a shift register and a data output unit; an input end of the shift register is connected with a first device, and an output end of the shift register is connected with the data output unit, which is used for receiving a command field and / or input data from the first device and performing data output; the shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; in the first mode, the first device is a master device, and the shift register outputs the input data from the first device to a target static register corresponding to the command field; in the second mode, the first device is an upstream device, and the shift register outputs the input data from the first device to a downstream device. In the above-mentioned circuit, the shift register can be switched between the first mode and the second mode, and the flexibility is improved.