191 results about "Serial Peripheral Interface Bus" patented technology

The invention provides a data transmission method and device, equipment and a storage medium. The data transmission method is applied to the controller, at least two buffer areas are arranged in the controller, and the data transmission method comprises the steps that in response to starting of a first timer, CAN data sent by external equipment through a CAN controller local area network bus is stored in the buffer area in an idle state in the at least two buffer areas; in the process of storing the CAN data through the buffer area in the idle state, forwarding the CAN data stored in the buffer area in the occupied state in the at least two buffer areas through a serial peripheral interface (SPI) bus; wherein the data transmission rate of the CAN bus is smaller than that of the SPI bus.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention relates to the field of storage, in particular to an automatic configuration method and system for RAID (redundant array of independent disks) cards. The problems that in the prior art, an RAID card cannot be pre-configured, misoperation is prone to occurring in the manual configuration process, and the labor cost is high are solved. The method comprises the following steps of: storing default automatic virtual disk creation and configuration data of an RAID (Redundant Array of Independent Disks) card in a serial peripheral interface flash memory; two M.2 SSD system disks with the same model and the same capacity and a microprocessor MCU are arranged in the RAID card; the configuration management module is responsible for executing an automatic configuration process, and automatic configuration is set and triggered under the condition that the hardware requirement and the triggering time are met; the automatic configuration of the RAID card is realized; the complex operation of manual creation of a user is greatly reduced, consideration of human-caused faults is reduced, the requirement for automatically configuring the RAID is provided, the process is achieved through automatic configuration, and the purpose of instant use after power-on is achieved.

The invention relates to a configuration method and device compatible with a multi-topological structure GPU server and a storage medium, and the method comprises the steps: controlling a first programmable logic chip of a GPU node to obtain topological structure information of the GPU server, setting the gating of a total multiplexer based on the topological structure information of the GPU server and a gating truth table, and according to the gating of the total multiplexer, carrying out the configuration of the GPU server. And determining the gating type of the total nonvolatile memory, and loading the corresponding firmware file from the corresponding total nonvolatile memory through the serial peripheral interface of the switching chip according to the gating type of the total nonvolatile memory so as to configure the PCIe port of the switching chip, thereby configuring the GPU server, and a serial peripheral interface of the switching chip is connected with a plurality of total nonvolatile memories. According to the scheme provided by the invention, the firmware file required by an actual topological structure can be adaptively switched to start and complete configuration in the whole process from server assembly completion, power-on to startup, so that the production efficiency is improved, and the development cost is saved.

The invention provides a system, method and device for updating FPGA firmware online. The method comprises the steps that a processor module outputs a control signal of a first level state to a switching control module through a universal input and output interface; the switching control module responds to the control signal of the first level state and establishes a first communication path between the serial peripheral interface of the processor and the storage module; writing the update data stream into the storage module through the first communication path; after the update data stream is written, establishing a second communication path between the FPGA module and the storage module; and the processor module sends a start loading command to a configuration register of the FPGA module, and triggers the FPGA module to read and load the update data stream from the storage module through the second communication path so as to complete online update of firmware. According to the method, the equipment maintainability in a scene with high reliability requirements is improved, the operation and maintenance cost and the time overhead are remarkably reduced, and meanwhile, the continuity and the availability of key system services are ensured.

A disclosed method monitors boot path driver events to identify faulty boot path drivers in a UEFI-compliant boot path. Upon identifying a faulty boot path driver, the faulty driver is isolated and a corresponding remediation driver is fetched. An override driver dispatch list is created by modifying an original driver dispatch list to replace the faulty driver with the remediation driver, wherein the remediation driver occupies the same place in the execution order of the override driver dispatch list as the faulty driver occupies in the original driver dispatch list. Following a warm reset, a boot path load is performed in accordance with the override driver dispatch list, thereby remediating the boot path without performing a firmware update on a serial peripheral interface (SPI) flash device or the like. In this manner, a faulty driver is detected, isolated, and remediated in a single boot path.

The application provides a circuit based on a beamforming chip serial peripheral interface, a beamforming chip and a radio frequency front end, comprising a shift register and a data output unit; an input end of the shift register is connected with a first device, and an output end of the shift register is connected with the data output unit, which is used for receiving a command field and / or input data from the first device and performing data output; the shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; in the first mode, the first device is a master device, and the shift register outputs the input data from the first device to a target static register corresponding to the command field; in the second mode, the first device is an upstream device, and the shift register outputs the input data from the first device to a downstream device. In the above-mentioned circuit, the shift register can be switched between the first mode and the second mode, and the flexibility is improved.

The invention discloses an AR glasses interactive bracelet, and relates to the technical field of smart bracelets, a control processing module is electrically connected with a touch screen, a power management module, a wireless communication module, an inertia measurement module and a non-inductive authentication module; the wireless communication module is in wireless connection with external AR glasses equipment, and performs wireless protocol transmission and reverse control with the AR glasses equipment; the touch screen comprises a display unit and a touch control unit, the display unit and the touch control unit are respectively connected with the control processing module through an SPI (Serial Peripheral Interface) and an IIC (Inter-Integrated Circuit) interface, and the touch control unit receives a touch input signal of a user and sends information to the control processing module and the like. The control function is transferred to the bracelet from the glasses body, the AR glasses equipment interface is controlled to move by touching and sliding the touch screen, the vibration feedback module is arranged, tactile feedback is provided according to the touch operation of a user, the user does not need to raise the hand to do large-amplitude gestures or depend on voice, and the operation is rapid, accurate and private.

The invention provides a high-speed voltage acquisition device and method, and relates to the technical field of industrial automatic testing. The device comprises a lower computer, an ADC (Analog to Digital Converter), an upper computer, an Ethernet module and a female header connector, the ADC is connected with the pressure sensor interface through the female header connector and is used for acquiring voltage data; the lower computer comprises an MCU (Microprogrammed Control Unit), the MCU is electrically connected with the ADC, and the MCU sends data to the ADC and receives the data sent by the ADC in a mode of simulating an SPI (Serial Peripheral Interface); the receiving module is used for receiving voltage data, compressing the received voltage data and then sending the compressed data to the upper computer through the Ethernet module; and the upper computer performs data analysis on the compressed data and converts the compressed data into an actual voltage value. Through the high-speed voltage acquisition device, high-speed and reliable acquisition and transmission of pressure sensor signals at a sampling rate of 10 kHz under a communication distance of 100 meters are realized, data transmission efficiency and signal restoration precision are significantly improved, and MCU resource consumption is reduced at the same time.

Embodiments herein relate to a computing device in which an embedded controller (EC) detects an anomalous low-power state. When a processor in a chip package enters a low power state, such as a deep idle state, the EC obtains information to verify whether the activity of the processor is consistent with the low power state. The EC may communicate with the chip package via a serial peripheral interface to obtain counter data indicating idle state residence of subsystems of the chip package and internal temperature data. The EC may also access data from an external temperature sensor and a battery voltameter. The EC determines whether the counter data, the temperature, and the battery discharge rate are inconsistent with the processor entering the low power state. If there is an inconsistency, the EC may turn off or restart the computing device.

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. The embedded controller may be bridged to the ARM based architecture SoC using a bridging agent that bridges enhanced serial peripheral interface (eSPI) format communication to system power management interface (SPMI) format communication.

A light emitting display apparatus includes a display panel having pixels arranged therein and each of the pixels including a light emitting diode, a timing control portion including a degradation data calculation portion configured to calculate degradation data representing a degradation amount of the pixel based on input image data, and a first serial peripheral interface (SPI) communication portion configured to transmit and receive the degradation data through an SPI communication, a memory including a second SPI communication portion configured to perform the SPI communication with the first SPI communication portion, and storing the degradation data, and a driving power selection portion configured to selectively provide a first driving power and a second driving power lower than the first driving power to the first SPI communication portion. When the SPI communication is on, the second driving power is provided to the first SPI communication portion.

The application relates to the storage field and relates to an automatic configuration method of a RAID array card and a configuration system thereof. The application solves the problems that the RAID array card cannot be preconfigured in the prior art, and the manual configuration process is prone to misoperation and high in labor cost. The application comprises the following steps: saving the default automatic creation virtual disk and configuration data of the RAID array card in a serial peripheral interface flash memory; setting two M.2 SSD system disks of the same model and capacity and a microprocessor MCU in the RAID array card; setting a trigger automatic configuration under the condition that hardware requirements and trigger time are met through a configuration management module responsible for executing an automatic configuration process; realizing the automatic configuration of the RAID array card; greatly reducing the complex operation of manual creation of the user, reducing the consideration of human error, and putting forward the demand for automatic configuration of the RAID, which is realized through the automatic configuration, so as to achieve the purpose of being used as soon as powered on.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface and executes the one or more layers.

The utility model relates to the technical field of industrial control, in particular to an IO-Link-based multichannel communication slave station system, which comprises an IO-Link interface and an IO-Link communication chip which are connected with each other, and a main control chip is connected with the IO-Link communication chip through an SPI (Serial Peripheral Interface); and the main control chip is connected with at least one isolation high-side switch module through an SPI (Serial Peripheral Interface) bus. The system can effectively solve the problems that in the prior art, due to the fact that sensors are connected together in a daisy chain (series connection) mode, a communication link is certainly long when a large number of sensors are installed, bus type communication has high requirements for a communication chip, and resource waste and unnecessary cost are caused by the fact that the sensors are connected together in a daisy chain (series connection) mode.

A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

A multi-user remote firmware development and debugging system includes multiple computing systems under test (“SUTs”) that include a serial data communication interface and a serial peripheral interface (“SPI”) flash emulator. The system also includes a host computer coupled to the SPI flash emulators and the serial data communication interfaces. The host can receive firmware debugging messages from an SUT and transmit the firmware debugging messages to a remote computing device operated by a developer. The host can also update the firmware of an SUT in response to a command from the remote computing device. Additionally, the host can power SUTs on or off using a network power switch and provide the ability to view video generated by the SUTs on the remote computing device and to remotely control the SUTs from the remote computing device using a network keyboard / video / mouse switch or a host-controlled automated testing adapter in an SUT.

The invention discloses an edge gateway hardware design system, which relates to the technical field of communication and industrial control, and comprises a core board, a bottom board, an FSU expansion board and a communication board, the core board is connected with the bottom board through a golden finger interface and is used for processing first data, second data and / or third data sent by the bottom board and sending the processed first data, second data and / or third data to the bottom board; the communication board is connected with the bottom board through a USB interface and is used for receiving the first data processed by the core board through the bottom board; and the FSU expansion board is connected with the bottom board through a serial peripheral interface and is used for receiving the third data processed by the core board through the bottom board. According to the invention, the technical problems of complex structure, poor expansibility, insufficient compatibility and difficulty in meeting diversified sensor access and efficient data transmission requirements of base station power and environment monitoring equipment in the prior art are solved.

The invention discloses an SPI (Serial Peripheral Interface) bus communication method and equipment for a measuring instrument and an SPI interface, and the method comprises a transmission frequency setting process which is used for dynamically adjusting the data transmission frequency of communication between master equipment and slave equipment. The method comprises the following steps: firstly, acquiring a transmission data response result in a data communication process between a master device and a slave device on the SPI bus, setting a data transmission frequency of communication between the master device and the slave device according to the transmission data response result, and reducing the data transmission frequency of communication between the master device and the slave device when the transmission data response result is failure. Due to the fact that the data transmission frequency of the SPI bus is set in a dynamic switching mode, it can be guaranteed that the measuring instrument can still keep the reliability and stability of SPI communication in different use environments or under the condition that devices are aged.

The present disclosure relates to an optical system and a signal processing method, the optical system comprising: an optical detection module, the optical detection module comprising an optical image sensor chip and a serial peripheral interface, the optical image sensor chip being configured to acquire an image of a surface of a pattern disc and output displacement data and raw image data; a mounting bracket, the mounting bracket being configured to fix the optical detection module above the pattern disc; the pattern disc, the pattern disc being located below the optical detection module, a surface pattern of the pattern disc being a radial pseudo-random pattern; a bearing seat, the bearing seat being configured to fix a rotation shaft of the pattern disc and a measured object; and a main control board, the main control board comprising a microcontroller, the microcontroller being configured to communicate with the optical detection module through the serial peripheral interface, the main control board being configured to perform a signal processing operation based on the displacement data, so that miniaturization and high precision of a rotary encoder can be achieved.

The invention discloses a method and system for flashing an SOC program of a cockpit domain controller through a steering wheel key, and relates to the field of program flashing, and the method comprises the steps that a domain controller host comprises an SOC chip and an MCU chip, and the SOC chip runs a QNX system and an Android virtual machine; the MCU chip runs an FREE RTOS / autosar os system, the MCU chip is responsible for power-on and power-off management of the SOC chip and a system dormancy awakening process, and the MCU chip communicates with the SOC chip through an SPI (Serial Peripheral Interface); wherein the signal comprises preset pressing times and interval time as encryption verification conditions; after the verification signal of the MCU chip meets the verification condition, the level of an FORCEUSBBOOT pin of the SOC chip is increased through a hardware circuit, then the SOC chip is powered off and then powered on again, and the SOC chip enters an EDL emergency downloading mode based on a QFIL tool; an SOC chip and equipment for installing a QFIL tool are connected through a USB interface, and firmware data transmission and flashing are completed based on a Firehose protocol, a Sahara protocol and a QCID driver.

The invention belongs to the technical field of communication, and relates to an SPI-based communication system, communication method and communication device.The communication system comprises a master device and a plurality of slave devices, the master device and the slave devices are connected through clock signal lines and data transmission lines, the master device is provided with an address output pin, and the slave devices are provided with address input pins; the address input pins of all the slave devices are connected with the address output pin of the master device through the same address transmission line; a processor and an address memory are further arranged in each slave device, a preset address is stored in the address memory, the preset address stored in each address memory uniquely corresponds to the slave device where the address memory is located, and the processor of each slave device is in communication connection with the address memory of the slave device. And the processor of each slave device is in communication connection with the address input pin of the slave device. According to the technical scheme adopted by the invention, the master device can be connected in parallel with a large number of slave devices under the condition of limited GPIO resources and limited wiring space.

The utility model belongs to the field of electrical technology, and particularly relates to a communication system of SPI (Serial Peripheral Interface) master equipment and a plurality of different slave equipment. Comprising a master device MCU, n slave devices, n three-state gates, n NOT gates and an enable signal generation module, and an SPICLK clock port of the master device MCU is connected with clock ports of the slave devices; the SPISIMO output port of the MCU of the master device is respectively connected with the input port of each slave device; an I / O port of the MCU of the master device is connected with an input port of the enable signal generation module for generating enable signals of the slave devices; the enabling port of each slave device is connected with the input end of the corresponding NOT gate, the output end of the NOT gate is connected with the enabling end of the corresponding three-state gate, and the output end of the slave device is connected with the input end of the three-state gate; and the output end of each three-state gate is connected with the SPISOMI input end of the main equipment MCU.

The invention relates to a safety air bag ignition method, system and equipment and a storage medium, and relates to the field of safety air bag ignition. The method is based on an MCU (Microprogrammed Control Unit), an airbag ignition chip and an SPI (Serial Peripheral Interface) bus, and comprises the following steps: acquiring acceleration data by utilizing an acceleration sensor control module in the airbag ignition chip; the acceleration data are sent to an acceleration abnormity judgment module in an air bag ignition chip, and the acceleration data are packaged into SPI data and uploaded to an SPI bus; a newly added communication channel is added between the MCU and the air bag ignition chip; when the acceleration anomaly judgment module detects an anomaly, an anomaly confirmation request is sent to the MCU through the newly added communication path and the SPI bus; obtaining SPI data on the SPI bus through the MCU according to the abnormity confirmation request, and analyzing the SPI data through the MCU to obtain an abnormity confirmation result; and according to the abnormity confirmation result, sending a command of whether to ignite or not to the air bag ignition chip through the newly added communication path and the SPI bus. The technical effect of the invention is that timely explosion of the air bag restraint system is guaranteed.

This application relates to secure serial peripheral interface (SPI) flash memory. A secure memory device is disclosed. In one embodiment, the memory device includes a controller configured to decode and execute commands issued by a host device, a cryptographic engine configured to authenticate a subset of the commands, the subset of the commands each including a digital signature, and a first monotonic counter that is incremented after execution of at least some of the subset of the commands, wherein a value of the first monotonic counter is used to generate the digital signature.

The embodiment of the application provides a system-level chip for communication between an AUTBUS and an SPI slave module, a system bus, and the system bus is connected with an AUTBUS module and a serial peripheral interface (SPI) slave module; wherein, the AUTBUS module is provided with an AUTBUS cache and an AUTBUS arbitration module, and the SPI slave module is provided with an SPI write cache and an SPI read cache; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from the AUTBUS cache and sends the cache data to the SPI slave module through a direct memory access (DMA) mode, and the SPI slave module receives the cache data from the system bus and writes the cache data into the SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to the SPI slave module, the first read request comprising: target data length, the SPI slave module reads cache data of the target data length from the SPI read cache and sends the cache data to the AUTBUS; thereby, the communication between the AUTBUS module and the SPI slave module can be realized, and the efficiency of the communication between the AUTBUS module and the SPI slave module is improved.

Embodiments of the present application disclose a control method, device and equipment of a vehicle body controller and a medium. The method comprises: if a serial peripheral interface instruction for controlling the vehicle body controller to enter an idle state is received, determining whether a current operation mode is a factory mode; the factory mode reflecting that a vehicle where the vehicle body controller is located is in a production process; if yes, controlling the vehicle body controller to enter a low-power consumption mode to reduce a voltage generated by static electricity accumulation of the vehicle body controller; otherwise, controlling the vehicle body controller to enter the idle state; and the power consumption of the vehicle body controller in the low-power consumption mode is less than the power consumption of the vehicle body controller in the idle state. The technical solution sets the factory mode, so that the vehicle body controller can maintain the low-power consumption mode for a longer time, thereby reducing high voltage generated by static electricity.

The invention discloses a multi-power-supply pre-drive control circuit device and method. The multi-power-supply pre-drive control circuit device comprises a power supply module, a pre-drive driving module, a switch control output module, a current sampling module and a micro-control processor module, the power supply module is connected with the pre-drive module; the pre-driving module is connected with the switch control output module; the switch control output module is connected with the current sampling module; and the current sampling module is connected with the micro-control processor module. The system has the advantages that dynamic adjustment can be carried out according to actual load requirements through double-circuit power supply, the system is suitable for small-current loads and can also cope with large-current peak values, and flexibility and expansibility are achieved; a pre-driving chip is adopted, driving and protection functions are integrated, serial peripheral interface (SPI) communication is supported, and system configuration and state monitoring are facilitated; through the multi-protection design of an anti-reverse connection circuit, a transient voltage suppressor (TVS) tube, a filter circuit and the like, the stability and the electromagnetic compatibility (EMC) performance in a complex automobile electronic environment are improved.

The invention discloses an intelligent decorative lighting control circuit and an intelligent lamp. The intelligent decorative lighting control circuit comprises a main control chip, a storage chip, a power amplifier chip, a key circuit, an infrared receiving circuit, an audio input circuit, an MOS tube driving circuit and a step-down conversion circuit, the main control chip is connected with the storage chip through an SPI (Serial Peripheral Interface), is connected with the input end of the power amplifier chip through a DAC (Digital-to-Analog Converter) output pin, and is respectively connected with the key circuit, the infrared receiving circuit, the audio input circuit and the MOS tube driving circuit through GPIO (General Purpose Input / Output) pins; the input end of the step-down conversion circuit is connected with an external direct-current power supply, and the output end is respectively connected with power supply pins of the main control chip, the storage chip and the power amplifier chip; and the main control chip reads audio data in the storage chip according to an input signal of the key circuit or the infrared receiving circuit and outputs the audio data to the power amplifier chip, or generates a PWM control signal and outputs the PWM control signal to the MOS tube driving circuit so as to perform intelligent cooperative control on the lamp. According to the invention, the system hardware complexity and cost are reduced.

The invention provides a branching terminal, a control method, equipment and a medium, the branching terminal control method is applied to a control unit of the branching terminal, and comprises the following steps: controlling an input port of a serial peripheral interface to receive a control signal output by external equipment, controlling the serial peripheral interface to acquire a corresponding digital signal from the control signal at a preset bit period; generating return-to-zero coded data based on the digital signal, wherein the return-to-zero coded data comprises a plurality of return-to-zero codes arranged in sequence; and based on the return-to-zero coded data, controlling data conduction of an output port corresponding to the return-to-zero coded data in a plurality of output ports of the serial peripheral interface. The method can be implemented on the basis of a control unit with relatively low dominant frequency, and the cost of the branching terminal can be effectively reduced in this way, so that popularization and application of the branching terminal in a large-scale scene are facilitated.