108 results about "Serial Peripheral Interface Bus" patented technology

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

A disclosed method monitors boot path driver events to identify faulty boot path drivers in a UEFI-compliant boot path. Upon identifying a faulty boot path driver, the faulty driver is isolated and a corresponding remediation driver is fetched. An override driver dispatch list is created by modifying an original driver dispatch list to replace the faulty driver with the remediation driver, wherein the remediation driver occupies the same place in the execution order of the override driver dispatch list as the faulty driver occupies in the original driver dispatch list. Following a warm reset, a boot path load is performed in accordance with the override driver dispatch list, thereby remediating the boot path without performing a firmware update on a serial peripheral interface (SPI) flash device or the like. In this manner, a faulty driver is detected, isolated, and remediated in a single boot path.

The application provides a circuit based on a beamforming chip serial peripheral interface, a beamforming chip and a radio frequency front end, comprising a shift register and a data output unit; an input end of the shift register is connected with a first device, and an output end of the shift register is connected with the data output unit, which is used for receiving a command field and / or input data from the first device and performing data output; the shift register is controlled by a mode selection input signal to switch between a first mode and a second mode; in the first mode, the first device is a master device, and the shift register outputs the input data from the first device to a target static register corresponding to the command field; in the second mode, the first device is an upstream device, and the shift register outputs the input data from the first device to a downstream device. In the above-mentioned circuit, the shift register can be switched between the first mode and the second mode, and the flexibility is improved.

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. The embedded controller may be bridged to the ARM based architecture SoC using a bridging agent that bridges enhanced serial peripheral interface (eSPI) format communication to system power management interface (SPMI) format communication.

A light emitting display apparatus includes a display panel having pixels arranged therein and each of the pixels including a light emitting diode, a timing control portion including a degradation data calculation portion configured to calculate degradation data representing a degradation amount of the pixel based on input image data, and a first serial peripheral interface (SPI) communication portion configured to transmit and receive the degradation data through an SPI communication, a memory including a second SPI communication portion configured to perform the SPI communication with the first SPI communication portion, and storing the degradation data, and a driving power selection portion configured to selectively provide a first driving power and a second driving power lower than the first driving power to the first SPI communication portion. When the SPI communication is on, the second driving power is provided to the first SPI communication portion.

The application relates to the storage field and relates to an automatic configuration method of a RAID array card and a configuration system thereof. The application solves the problems that the RAID array card cannot be preconfigured in the prior art, and the manual configuration process is prone to misoperation and high in labor cost. The application comprises the following steps: saving the default automatic creation virtual disk and configuration data of the RAID array card in a serial peripheral interface flash memory; setting two M.2 SSD system disks of the same model and capacity and a microprocessor MCU in the RAID array card; setting a trigger automatic configuration under the condition that hardware requirements and trigger time are met through a configuration management module responsible for executing an automatic configuration process; realizing the automatic configuration of the RAID array card; greatly reducing the complex operation of manual creation of the user, reducing the consideration of human error, and putting forward the demand for automatic configuration of the RAID, which is realized through the automatic configuration, so as to achieve the purpose of being used as soon as powered on.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface and executes the one or more layers.

The utility model relates to the technical field of industrial control, in particular to an IO-Link-based multichannel communication slave station system, which comprises an IO-Link interface and an IO-Link communication chip which are connected with each other, and a main control chip is connected with the IO-Link communication chip through an SPI (Serial Peripheral Interface); and the main control chip is connected with at least one isolation high-side switch module through an SPI (Serial Peripheral Interface) bus. The system can effectively solve the problems that in the prior art, due to the fact that sensors are connected together in a daisy chain (series connection) mode, a communication link is certainly long when a large number of sensors are installed, bus type communication has high requirements for a communication chip, and resource waste and unnecessary cost are caused by the fact that the sensors are connected together in a daisy chain (series connection) mode.

A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

A multi-user remote firmware development and debugging system includes multiple computing systems under test (“SUTs”) that include a serial data communication interface and a serial peripheral interface (“SPI”) flash emulator. The system also includes a host computer coupled to the SPI flash emulators and the serial data communication interfaces. The host can receive firmware debugging messages from an SUT and transmit the firmware debugging messages to a remote computing device operated by a developer. The host can also update the firmware of an SUT in response to a command from the remote computing device. Additionally, the host can power SUTs on or off using a network power switch and provide the ability to view video generated by the SUTs on the remote computing device and to remotely control the SUTs from the remote computing device using a network keyboard / video / mouse switch or a host-controlled automated testing adapter in an SUT.

The present disclosure relates to an optical system and a signal processing method, the optical system comprising: an optical detection module, the optical detection module comprising an optical image sensor chip and a serial peripheral interface, the optical image sensor chip being configured to acquire an image of a surface of a pattern disc and output displacement data and raw image data; a mounting bracket, the mounting bracket being configured to fix the optical detection module above the pattern disc; the pattern disc, the pattern disc being located below the optical detection module, a surface pattern of the pattern disc being a radial pseudo-random pattern; a bearing seat, the bearing seat being configured to fix a rotation shaft of the pattern disc and a measured object; and a main control board, the main control board comprising a microcontroller, the microcontroller being configured to communicate with the optical detection module through the serial peripheral interface, the main control board being configured to perform a signal processing operation based on the displacement data, so that miniaturization and high precision of a rotary encoder can be achieved.

The invention discloses a method and system for flashing an SOC program of a cockpit domain controller through a steering wheel key, and relates to the field of program flashing, and the method comprises the steps that a domain controller host comprises an SOC chip and an MCU chip, and the SOC chip runs a QNX system and an Android virtual machine; the MCU chip runs an FREE RTOS / autosar os system, the MCU chip is responsible for power-on and power-off management of the SOC chip and a system dormancy awakening process, and the MCU chip communicates with the SOC chip through an SPI (Serial Peripheral Interface); wherein the signal comprises preset pressing times and interval time as encryption verification conditions; after the verification signal of the MCU chip meets the verification condition, the level of an FORCEUSBBOOT pin of the SOC chip is increased through a hardware circuit, then the SOC chip is powered off and then powered on again, and the SOC chip enters an EDL emergency downloading mode based on a QFIL tool; an SOC chip and equipment for installing a QFIL tool are connected through a USB interface, and firmware data transmission and flashing are completed based on a Firehose protocol, a Sahara protocol and a QCID driver.

The utility model belongs to the field of electrical technology, and particularly relates to a communication system of SPI (Serial Peripheral Interface) master equipment and a plurality of different slave equipment. Comprising a master device MCU, n slave devices, n three-state gates, n NOT gates and an enable signal generation module, and an SPICLK clock port of the master device MCU is connected with clock ports of the slave devices; the SPISIMO output port of the MCU of the master device is respectively connected with the input port of each slave device; an I / O port of the MCU of the master device is connected with an input port of the enable signal generation module for generating enable signals of the slave devices; the enabling port of each slave device is connected with the input end of the corresponding NOT gate, the output end of the NOT gate is connected with the enabling end of the corresponding three-state gate, and the output end of the slave device is connected with the input end of the three-state gate; and the output end of each three-state gate is connected with the SPISOMI input end of the main equipment MCU.

The invention relates to a safety air bag ignition method, system and equipment and a storage medium, and relates to the field of safety air bag ignition. The method is based on an MCU (Microprogrammed Control Unit), an airbag ignition chip and an SPI (Serial Peripheral Interface) bus, and comprises the following steps: acquiring acceleration data by utilizing an acceleration sensor control module in the airbag ignition chip; the acceleration data are sent to an acceleration abnormity judgment module in an air bag ignition chip, and the acceleration data are packaged into SPI data and uploaded to an SPI bus; a newly added communication channel is added between the MCU and the air bag ignition chip; when the acceleration anomaly judgment module detects an anomaly, an anomaly confirmation request is sent to the MCU through the newly added communication path and the SPI bus; obtaining SPI data on the SPI bus through the MCU according to the abnormity confirmation request, and analyzing the SPI data through the MCU to obtain an abnormity confirmation result; and according to the abnormity confirmation result, sending a command of whether to ignite or not to the air bag ignition chip through the newly added communication path and the SPI bus. The technical effect of the invention is that timely explosion of the air bag restraint system is guaranteed.

This application relates to secure serial peripheral interface (SPI) flash memory. A secure memory device is disclosed. In one embodiment, the memory device includes a controller configured to decode and execute commands issued by a host device, a cryptographic engine configured to authenticate a subset of the commands, the subset of the commands each including a digital signature, and a first monotonic counter that is incremented after execution of at least some of the subset of the commands, wherein a value of the first monotonic counter is used to generate the digital signature.

The embodiment of the application provides a system-level chip for communication between an AUTBUS and an SPI slave module, a system bus, and the system bus is connected with an AUTBUS module and a serial peripheral interface (SPI) slave module; wherein, the AUTBUS module is provided with an AUTBUS cache and an AUTBUS arbitration module, and the SPI slave module is provided with an SPI write cache and an SPI read cache; when the AUTBUS arbitration module controls the transmission direction to be a first transmission direction, the AUTBUS module reads cache data from the AUTBUS cache and sends the cache data to the SPI slave module through a direct memory access (DMA) mode, and the SPI slave module receives the cache data from the system bus and writes the cache data into the SPI write cache; when the AUTBUS arbitration module controls the transmission direction to be a second transmission direction, the AUTBUS module sends a first read request to the SPI slave module, the first read request comprising: target data length, the SPI slave module reads cache data of the target data length from the SPI read cache and sends the cache data to the AUTBUS; thereby, the communication between the AUTBUS module and the SPI slave module can be realized, and the efficiency of the communication between the AUTBUS module and the SPI slave module is improved.

Embodiments of the present application disclose a control method, device and equipment of a vehicle body controller and a medium. The method comprises: if a serial peripheral interface instruction for controlling the vehicle body controller to enter an idle state is received, determining whether a current operation mode is a factory mode; the factory mode reflecting that a vehicle where the vehicle body controller is located is in a production process; if yes, controlling the vehicle body controller to enter a low-power consumption mode to reduce a voltage generated by static electricity accumulation of the vehicle body controller; otherwise, controlling the vehicle body controller to enter the idle state; and the power consumption of the vehicle body controller in the low-power consumption mode is less than the power consumption of the vehicle body controller in the idle state. The technical solution sets the factory mode, so that the vehicle body controller can maintain the low-power consumption mode for a longer time, thereby reducing high voltage generated by static electricity.

The invention discloses a multi-power-supply pre-drive control circuit device and method. The multi-power-supply pre-drive control circuit device comprises a power supply module, a pre-drive driving module, a switch control output module, a current sampling module and a micro-control processor module, the power supply module is connected with the pre-drive module; the pre-driving module is connected with the switch control output module; the switch control output module is connected with the current sampling module; and the current sampling module is connected with the micro-control processor module. The system has the advantages that dynamic adjustment can be carried out according to actual load requirements through double-circuit power supply, the system is suitable for small-current loads and can also cope with large-current peak values, and flexibility and expansibility are achieved; a pre-driving chip is adopted, driving and protection functions are integrated, serial peripheral interface (SPI) communication is supported, and system configuration and state monitoring are facilitated; through the multi-protection design of an anti-reverse connection circuit, a transient voltage suppressor (TVS) tube, a filter circuit and the like, the stability and the electromagnetic compatibility (EMC) performance in a complex automobile electronic environment are improved.

The invention discloses an intelligent decorative lighting control circuit and an intelligent lamp. The intelligent decorative lighting control circuit comprises a main control chip, a storage chip, a power amplifier chip, a key circuit, an infrared receiving circuit, an audio input circuit, an MOS tube driving circuit and a step-down conversion circuit, the main control chip is connected with the storage chip through an SPI (Serial Peripheral Interface), is connected with the input end of the power amplifier chip through a DAC (Digital-to-Analog Converter) output pin, and is respectively connected with the key circuit, the infrared receiving circuit, the audio input circuit and the MOS tube driving circuit through GPIO (General Purpose Input / Output) pins; the input end of the step-down conversion circuit is connected with an external direct-current power supply, and the output end is respectively connected with power supply pins of the main control chip, the storage chip and the power amplifier chip; and the main control chip reads audio data in the storage chip according to an input signal of the key circuit or the infrared receiving circuit and outputs the audio data to the power amplifier chip, or generates a PWM control signal and outputs the PWM control signal to the MOS tube driving circuit so as to perform intelligent cooperative control on the lamp. According to the invention, the system hardware complexity and cost are reduced.

The invention relates to a multi-port IO linked master transceiver and adaptive DIO design. A system includes a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy chain arrangement via a serial peripheral interface (SPI) protocol. Each reconfigurable device includes control circuitry configured to operate in a digital input / output (DIO) mode and an IO link mode, digital logic for switching the DIO control circuitry between the DIO mode and the IO link mode, an output driver connected between an output of the control circuitry and a respective output pin of a plurality of pin sets, the input filter is connected between the input of the control circuit arrangement and the corresponding input pin of the plurality of pin sets, and the SPI interface is used for communicating with the MCU and other reconfigurable devices in the daisy chain, and the digital control facilitates communication between the SPI interface and the control circuit arrangement.

This application discloses a multi-channel bioelectric signal transmission method, device, and storage medium. The device includes: an analog front-end module comprising multiple analog front-end units, each analog front-end unit including multiple acquisition channels for acquiring bioelectric signals and performing analog-to-digital conversion, transmitting the converted data stream to a data transmission module; and a data transmission module connected to the analog front-end module via a four-data-line serial peripheral interface for receiving the data stream and transmitting the received data stream to a remote host via a wireless ultra-wideband module; wherein the data transmission module has multiple switchable operating modes. This application provides a bioelectric signal transmission device that integrates multiple operating modes suitable for various scenarios, reduces system power consumption, and realizes multi-channel acquisition and wireless transmission of bioelectric signals.

Disclosed herein is a system, including a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy chain arrangement via a Serial Peripheral Interface (SPI) protocol. Each reconfigurable device includes control circuitry configured for operating in both a Digital Input / Output (DIO) mode and an IO-Link mode, a digital logic for switching the DIO control circuitry between the DIO mode and the IO-Link mode, output drivers connected between outputs of the control circuitry and respective output pins of a plurality of pin sets, input filters connected between inputs of the control circuitry and respective inputs pins of the plurality of pin sets, and an SPI interface for communication with the MCU and other reconfigurable devices in the daisy chain, with the digital control facilitating communication between the SPI interface and the control circuitry.

The embodiment of the invention discloses a data transmission method, relates to the technical field of computers, and is used for improving the data programming efficiency of a display module. The method comprises the following steps: a display driving chip receives a programming command sent by signal generator equipment; the display driving chip receives programming data sent by the signal generator equipment through the image transmission interface; and the display driving chip transmits the programming data to a flash memory of the display module under the indication of the programming command. In the scheme provided by the embodiment of the invention, the signal generator equipment transmits the programming data by using the image transmission interface, and the image transmission interface has higher transmission speed and stronger anti-interference capability and error correction capability compared with an SPI (Serial Peripheral Interface), so that compared with the signal generator equipment which transmits the programming data by using the SPI, the signal generator equipment transmits the programming data by using the SPI; the signal generator equipment transmits the programming data by using the image transmission interface, so that the transmission speed and the transmission accuracy of the programming data can be improved, and the data programming efficiency of the display module is improved.

The embodiment of the invention provides a data transmission method and a related device, and the method comprises the steps: writing first configuration information into a configuration register of a 1553B protocol controller based on a serial peripheral interface through a 1553B module in response to request information sent by a client, and obtaining the configured 1553B protocol controller; the 1553B module is connected with the client side through the Ethernet; the 1553B module reads data corresponding to the request information on the basis of the configured 1553B protocol controller; and the 1553B module sends the data to the client based on a remote calling channel of the Ethernet. According to the embodiment of the invention, PCIE physical connection is replaced by the configured 1553B protocol controller and the remote calling channel of the Ethernet, and on the basis, communication can be realized by using a standardized network protocol without customizing a driving program, so that the compatibility is effectively improved.

The invention provides an image data display system and method, electronic equipment and a storage medium. Wherein the display system transmits data through a serial peripheral interface (SPI) bus, the display system comprises a master device and a slave device, the master device comprises a data input circuit, a data output circuit and a serial clock circuit, the serial clock circuit comprises a phase-locked loop circuit, the slave device comprises a display device, and the master device acquires image data to be transmitted; the phase-locked loop circuit is used for increasing the original main clock frequency of the serial clock circuit; the main device carries out coding and signal enhancement processing on the image data and transmits the processed image data; the master device dynamically performs signal shaping on a master clock signal output by the serial clock circuit; and the display device performs decoding and time sequence matching on the received image data and then displays the image data. According to the method, the display effect of the image data can be improved on the basis that an existing SPI display screen is not changed or changed at low cost.

A control panel for a fire alarm system includes a microprocessor operable to send and receive data. The microprocessor has a serial peripheral interface with a master port and a slave port. A computing device has a Differential Manchester encoder configured to encode data received from the master port and a Differential Manchester decoder configured to decode frames and send the decoded data to the slave port. A method of sending and receiving data is also disclosed.

The FPGA online upgrading method based on the MicroBlaze and the PCIE bus comprises the steps that a CPU divides a configured file into a plurality of data packages in sequence, each data package comprises a current data package code, a current data package byte length and data package content, and except the data package which is finally divided, the byte lengths of the other data packages are all configured to be bytes with preset sizes; the FPGA receives an online upgrading instruction at the BRAM matching address based on the MicroBlaze; the method comprises the following steps of: writing a data packet into a CPU (Central Processing Unit), erasing an update area of the FLASH, sequentially writing the data packet into a preset storage area of the FLASH through an SPI (Serial Peripheral Interface) protocol, comparing a checksum with a checksum sent by the CPU, feeding back state parameters of online upgrading completion to the CPU by an FPGA end, and quitting online upgrading operation after receiving a quit command sent by the CPU, so that the upgrading efficiency is improved.

The invention discloses a communication system, a communication method and an air conditioner, relates to the technical field of communication, and is used for improving communication quality when signal distortion is caused by load change on a bus. The method comprises the steps that an SPI driving signal is sent to a driving chip through a serial peripheral interface, so that the driving chip converts the received SPI driving signal into a communication signal and sends the communication signal to a bus, the driving chip collects the communication signal on the bus, converts the communication signal into a UART signal and sends the UART signal to a single chip microcomputer, and the single chip microcomputer sends the communication signal to the single chip microcomputer; when the first data represented by the SPI driving signal is inconsistent with the second data represented by the UART signal, the SPI driving signal is adjusted, the adjusted SPI driving signal is resent to the driving chip, when a preset stop condition is met, prompt information is output, and the prompt information is used for indicating that a communication fault exists between the single-chip microcomputer and the driving chip.

An information handling system, comprising a memory and a processor to communicate with the memory. The processor is configured to determine whether a current boot process of the information handling system is a first boot process. If the current boot process is the first boot process, then determine whether a record in an SPI image is to be updated based on a lookup table. The processor is also configured to update the record in the SPI image based on data included in the lookup table. Subsequent to the update of the record, the processor is configured to proceed with execution of the current boot process of the information handling system.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.