Dual-processor communication method based on SPI (serial peripheral interface) bus

Abstract

The invention relates to a dual-processor communication method based on an SPI (serial peripheral interface) bus, which is used for high-speed two-way communication between double processors by the aid of the SPI bus. The method includes: adding a handshaking wire based on a four-wire system of a physical layer of the SPI bus to form a five-wire SPI bus capable of being used for two-way communication; completing mechanism synchronization of the five-wire SPI bus on a data link layer by using the '0-bit interpolation method' and combining CS (chip select) signals, handshaking signals and feedback information; controlling flow of the five-wire SPI bus by using 'receiving buffer zone residual capacity' in the feedback information; and using CRC (cyclic redundancy check) and confirm character'0x7F' in the feedback information to complete error processing of the five-wire SPI bus. The method has the advantages of simplicity in expansion, convenience in application and compatibility to other buses, and meanwhile, extremely high communication rate can be obtained to meet requirements of high-speed communication between the double processors, and the method is widely applicable to designof multi-processor systems.

Description

technical field [0001] The invention relates to a dual-processor communication method based on an SPI bus, which realizes high-speed bidirectional communication between the dual processors using the SPI bus. Background technique [0002] There are many ways to communicate between system-level processors. Serial communication buses such as RS-232 and I2C have become one of the more common choices. However, for high-speed processing, the speed of serial communication buses such as RS-232 and I2C Both are relatively low, the communication rate of RS-232 serial communication is generally below 115.2kHz, and the communication rate of I2C is up to 100kHz. Relatively speaking, SPI is a high-speed, full-duplex, synchronous communication bus, and its communication rate can basically be set according to the processing speed of the processors on both sides of the communication, which can meet the communication requirements of high-speed processors. [0003] The SPI bus system is a syn...

AI Technical Summary

Problems solved by technology

[0004] 1. There is no framing mechanism, and there is no provision for the data frame structure;

[0005] 2. There is no specified data flow in the communication process, lack of response mechanism and confirmation of whether the data is received;

[0006] 3. Without any verification, there is no mechanism to control transmission errors;

[0007] 4. Lack of control over data flow, lack of matching mechanism between sender and receiver;

[0008] 5. Lack of maintenance mechanism for data links, no management of establishment, maintenance, release, etc.

[0009] From the perspective of the OSI seven-layer model, SPI communication itself only specifies the physical layer protocol of communication, but lacks the protocol of the data link layer.

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