Dual-processor communication method based on SPI (serial peripheral interface) bus

A technology of SPI bus and communication method, which is applied in the direction of electrical digital data processing, instruments, computers, etc., can solve the problem of no establishment, maintenance, release management, lack of response mechanism and confirmation of whether data is received, and data frame structure does not make any Regulations and other issues, to achieve the effect of convenient application, simple expansion, and high communication rate

Inactive Publication Date: 2012-06-20
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. There is no framing mechanism, and there is no provision for the data frame structure;
[0005] 2. There is no specified data flow in the communication process, lack of response mechanism and confirmation of whether the data is received;
[0006] 3. Without any verification, there is no mechanism to control transmission errors;
[0007] 4. Lack of control over data flow, lack of matching mechanism between sender and receiver;
[0008] 5. Lack of maintenance mechanism for data links, no management of establishment, maintenance, release, etc.
[0009] From the perspective of the OSI seven-layer model, SPI communication itself only specifies the physical layer protocol of communication, but lacks the protocol of the data link layer.

Method used

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  • Dual-processor communication method based on SPI (serial peripheral interface) bus
  • Dual-processor communication method based on SPI (serial peripheral interface) bus
  • Dual-processor communication method based on SPI (serial peripheral interface) bus

Examples

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Effect test

Embodiment 1

[0070] Embodiment one: see figure 1 , this dual-processor communication method based on SPI bus is characterized in that the specific operation steps are:

[0071] a. Extended SPI physical layer. On the basis of the four-wire system of SPI, add a handshake signal line connected with a pull-up resistor - HandShaking;

[0072] b. Establish a frame format based on SPI bus two-way communication;

[0073] c. Based on the CS signal line already stipulated by the SPI bus and our newly established HandShaking handshake signal line, a synchronization mechanism based on the two-way communication of the SPI bus is established;

[0074] d. On the basis of sending frame and receiving frame format, establish a flow control mechanism;

[0075] e. Based on the CRC checksum and frame checksum confirmation, an error handling mechanism is established.

Embodiment 2

[0077] see Figure 1 to Figure 6 , the present embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0078] The method of the extended SPI physical layer of described step a is:

[0079] On the basis of SPI four-wire communication, establish a five-wire system for two-way communication SPI bus, that is, add a handshake signal line connected with a pull-up resistor on the basis of SPI four-wire system-HandShaking, which is a slave to The host is a one-way signal line. The function of the HandShaking signal is to inform the host that the slave has data to send.

[0080] Described step b sets up the method based on SPI bus two-way communication frame format as:

[0081] On the basis of the five-wire SPI bus, adopt the "0-bit insertion method", and use (0x7f) as a sign of flow control; as the master-slave communication mode, the frame format mainly includes the sender's frame format and the receiver's frame format Two kinds:

[0082] ①, s...

Embodiment 3

[0105] Figure 7 Shown is a system architecture diagram of a body network control device. There are two processors ARM9 and S12 in the system, of which ARM9 is the host and S12 is the slave.

[0106] The communication method described in this patent is used as the communication interface between the ARM9 module and the S12 processor. The S12 processor is responsible for the communication of KWP2000 bus, CAN bus and LIN bus, and the ARM9 module is responsible for the display and touch operation of the touch screen. The function IDs used in this application include:

[0107] Table 1 Body bus network controller communication ID

[0108] Function ID number Functional description 0x00 Slave processor control operation sent by ARM 0x01 CAN bus data information sent by ARM 0x02 LIN bus data information sent by ARM 0x03 KWP2000 bus data information sent by ARM 0x10 Slave status information sent by S12 0x11 CAN bus data information sent...

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Abstract

The invention relates to a dual-processor communication method based on an SPI (serial peripheral interface) bus, which is used for high-speed two-way communication between double processors by the aid of the SPI bus. The method includes: adding a handshaking wire based on a four-wire system of a physical layer of the SPI bus to form a five-wire SPI bus capable of being used for two-way communication; completing mechanism synchronization of the five-wire SPI bus on a data link layer by using the '0-bit interpolation method' and combining CS (chip select) signals, handshaking signals and feedback information; controlling flow of the five-wire SPI bus by using 'receiving buffer zone residual capacity' in the feedback information; and using CRC (cyclic redundancy check) and confirm character'0x7F' in the feedback information to complete error processing of the five-wire SPI bus. The method has the advantages of simplicity in expansion, convenience in application and compatibility to other buses, and meanwhile, extremely high communication rate can be obtained to meet requirements of high-speed communication between the double processors, and the method is widely applicable to designof multi-processor systems.

Description

technical field [0001] The invention relates to a dual-processor communication method based on an SPI bus, which realizes high-speed bidirectional communication between the dual processors using the SPI bus. Background technique [0002] There are many ways to communicate between system-level processors. Serial communication buses such as RS-232 and I2C have become one of the more common choices. However, for high-speed processing, the speed of serial communication buses such as RS-232 and I2C Both are relatively low, the communication rate of RS-232 serial communication is generally below 115.2kHz, and the communication rate of I2C is up to 100kHz. Relatively speaking, SPI is a high-speed, full-duplex, synchronous communication bus, and its communication rate can basically be set according to the processing speed of the processors on both sides of the communication, which can meet the communication requirements of high-speed processors. [0003] The SPI bus system is a syn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163G06F13/20
Inventor 胡越黎孙斌王昆徐磊刘廷尧王龙杰虞超
Owner SHANGHAI UNIV
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