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8112 results about "Physical layer" patented technology

In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer. This layer may be implemented by a PHY chip. The physical layer consists of the electronic circuit transmission technologies of a network. It is a fundamental layer underlying the higher level functions in a network, and can be implemented through a great number of different hardware technologies with widely varying characteristics.

Communication system architecture and operating methodology providing a virtual neighborhood network

InactiveUS7142503B1Overcome bandwidth limitationIncreased peak bandwidth capacityError preventionFrequency-division multiplex detailsEnd-to-end encryptionTransceiver
A communication system (10) supports the provision of a plurality of dedicated communication resources (50–64), such as copper drops, RF links and optical fibers, to dedicated home-gateway devices (44–48) or distribution points (124). The communication resources (50–64) support broadband interconnection (104) between the dedicated home-gateway devices (44–48) or distribution points (124) and an access multiplexor (30) in a network (12). Each gateway device (44–48) or distribution point (124) generally includes a local RF transceiver (84) and associated control logic (80–82) that allows local communication (86) between gateway devices (44–48) and hence statistically multiplexed access (60–64, 89) to multiple communication resources, thereby providing increased bandwidth in uplink and/or downlink directions. With the control logic (80) operable to provide a routing and prioritisation/arbitration function, each gateway (44–48) is able to selectively engage use of supplemental, non-reserved communication resources usually associated with a dedicated ono-to-one connection between the access network (12) and at least one secondary gateway. Physical layer access to information routed via a secondary gateway within a virtual neighborhood network (90–92) comprising several gateways is restricted through an end-to-end encryption algorithm between an originating gateway and, at least, the access multilpexor (30).
Owner:RPX CLEARINGHOUSE

Method and system for managing design corrections for optical and process effects based on feature tolerances

A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and / or processing effects for example photoresist response and etching effects. The method comprises determining a correction for the repeating pattern based on a first set of tolerances for features of the repeating pattern. Then, the suitability of the corrections is evaluated for instances of the repeating pattern in the integrated circuit design based on a second set of tolerances, which is different from the first set of tolerances. This can be used to preserve much of the hierarchy of the layout data in the corrected, or lithography, data. This can be achieved during the OPC process, thus avoiding the post OPC compaction. It can further take advantage of the fact that, for a given physical layer of a chip for example, different portions of the representing design polygons typically have different requirements on pattern fidelity on the wafer while perturbations may vary as a function of field position. By applying knowledge of the feature tolerances, and allowing design corrections only when tolerances are not met, the data explosion that occurs when moving from layout to lithography data can be contained without sacrificing accuracy.
Owner:CADENCE DESIGN SYST INC
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