69 results about "Digitally controlled oscillator" patented technology

The invention relates to the technical field of radio frequency signal processing, and discloses a self-adaptive digital phase calibration method and device, a radio frequency system-on-chip board card, a multi-channel radio frequency receiving system and electronic equipment. Comprising the following steps: under the condition that a synchronous acquisition instruction is received, synchronously acquiring radio frequency signals of each antenna channel at the same moment by using a signal acquisition unit; performing digital domain signal processing on the radio frequency signal by using a digital processing unit to obtain respective baseband signal data of each antenna channel; performing phase calculation on the baseband signal data, and determining respective relative phase data of each antenna channel; and dynamically configuring a digitally controlled oscillator corresponding to each antenna channel based on the relative phase data so as to perform adaptive phase calibration on each antenna channel. The phase difference between the channels can be dynamically corrected without depending on additional hardware devices such as a phase shifter or a delayer, the application requirement of a large-scale multi-channel radio frequency receiving system is met, and the phase synchronization requirement between the channels is effectively met.

An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.

A communication system includes a master communication device and a slave communication device. The master communication device includes a first signal generator, a second signal generator, a signal combiner, and a transmitting HBC (Human Body Communication) electrode. The signal combiner combines a first signal with a second signal, so as to generate a third signal. The transmitting HBC electrode transmits the third signal through a human body. The slave communication device includes a receiving HBC electrode, a signal splitter, a processor, and an injection-locked DCO (Digital Control Oscillator). The receiving HBC electrode receives a mix signal from the human body. The signal splitter divides the mix signal into a data signal and a synchronization signal. The injection-locked DCO performs a time synchronization process according to the synchronization signal.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

The application discloses a kind of digital frequency tracking and synchronous sampling control system for resonant gyro, including self-excitation oscillation and automatic gain control device, preamplifier circuit and digital signal processor, digital signal processor includes first A / D conversion unit, second A / D conversion unit, frequency error detection unit FD, phase error detection unit PD, digital control oscillator NCO, sampling frequency generator and quadrature demodulation unit, the vibration signal of drive channel is handled after device output to first A / D conversion unit, conversion obtains the vibration signal after conversion, FD obtains frequency difference by frequency error detection, PD obtains phase difference by phase error detection, NCO is adjusted the frequency and phase of sampling frequency generator according to frequency difference and phase difference in real time, until the resonant frequency and phase of drive channel are tracked;The vibration signal of detection channel is handled after circuit output to second A / D conversion unit, obtains the vibration signal after conversion, and quadrature demodulation unit carries out quadrature demodulation and obtains speed signal.

This application discloses a receiver positioning method, apparatus, communication system, storage medium, and electronic device, relating to the field of satellite navigation technology. The method includes: determining second information after signal recovery based on first information before signal loss of the satellite; tracking the signal based on a carrier digitally controlled oscillator frequency control word, a code digitally controlled oscillator frequency control word, and a code start point to determine the frequency error; during signal tracking, detecting whether the second code phase is aligned by code phase sliding; and, in response to the frequency error being within a preset range, the second code phase being aligned, and carrier synchronization, performing navigation calculations based on code epoch values ​​and the tracked third code phase to position the receiver. This application solves the technical problems in related technologies where repositioning of lost-lock signals cannot be achieved in weak signal scenarios, and the repositioning time is slow.

A communication system comprises a master control communication device and a slave communication device. The master control type communication device comprises a first signal generator, a second signal generator, a signal combiner and an emission type human body communication electrode. The signal combiner may combine the first signal with the second signal to generate a third signal. The emission type human body communication electrode can transmit a third signal through the human body. The slave communication device comprises a receiving type human body communication electrode, a signal distributor, a processor and an injection locking digital control oscillator. The receiving type human body communication electrode can receive a mixed signal from a human body. The signal distributor can divide the mixed signal into a data signal and a synchronization signal. The injection-locked digitally controlled oscillator may execute a time synchronization procedure according to the synchronization signal.

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.

The invention provides a frequency control method and system for a digital control oscillator, and relates to the technical field of frequency control of the digital control oscillator, and the method comprises the steps: obtaining a current gate period length value of the digital control oscillator, carrying out the gate control counting of an output clock of the digital control oscillator based on the current gate period length value, and obtaining an in-gate counting sequence, calculating a noise estimator based on the in-gate counting sequence, determining a target gate period length value based on the noise estimator, determining an instantaneous frequency ratio based on the target gate period length value, calculating a smoothing factor based on the noise estimator and the target gate period length value, and smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smooth frequency ratio; the target frequency tuning word is determined based on the smooth frequency ratio, the output frequency of the digital control oscillator is adjusted based on the target frequency tuning word, and the method has the effects of improving the dynamic performance, the steady-state precision and the environment adaptive capacity of frequency control of the digital control oscillator.

In an embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to divide the output clock signal to generate a divided clock signal, a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to generate a gain error signal, and modify the bias control word based on the gain error signal to generate a modified bias control word.

The invention relates to a circuit and a method for generating an oscillator signal. The present disclosure relates to an oscillator circuit comprising: a controller configured to generate a frequency control signal, the frequency control signal comprising a first frequency control value; a digitally controlled oscillator (DCO) configured to generate an oscillator output signal based on the frequency control signal, where the output signal is generated at a first frequency in response to a first frequency control value of the frequency control signal; and a digital feedback circuit configured to receive the output signal and output a first feedback signal, where the oscillator circuit is configured such that the first frequency depends on or is at least partially based on a value of the first feedback signal, and the controller is configured to provide a first control instruction to instruct the digital feedback circuit to update the first feedback signal, the digital feedback circuit is configured to, in response to the first control instruction: measure a first frequency of the output signal; and adjusting a value of the first feedback signal to reduce an error between the first frequency and the first target frequency.

The invention relates to quantization error and spurious suppression in digital phase-locked loops. A digital phase locked loop (DPLL) may include a dither source to provide a dither signal at an order to reach an integer bit over a set of fractional bits of a modulated signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include: a main delta-sigma modulator (DSM) for driving a main capacitor bank of the DCO based on a dither signal and a modulation signal; a first auxiliary DSM, associated with eliminating the influence of the dither signal on the DPLL output signal, for driving a first auxiliary capacitor bank of the DCO based on the dither signal; and a second auxiliary DSM for driving a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, associated with eliminating the effects of the quantization error of the main DSM.

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

This application provides a phase-locked loop (PLL), a control method, and a frequency source. It includes a controller, a time-to-digital converter (TD-to-digital converter), an arithmetic logic unit (ALU), a digitally controlled oscillator (DCO), and a frequency divider. The DCO outputs a linearly swept frequency signal based on a frequency control signal from the ALU. The frequency divider generates a divided frequency signal based on the output frequency of the DCO. The TD-to-digital converter outputs the phase difference between the divided frequency signal and a reference signal. The ALU outputs a frequency control signal based on the phase difference and a control code to adjust the output frequency of the DCO. The controller acquires the output signal of the TD-to-digital converter after a step point in the division ratio, and adjusts the control code until the output signal of the TD-to-digital converter after the step point is zero when the output signal is not zero. This method improves the linearity of the sawtooth waveform generated by the PLL at the step point.

The present invention discloses a quantum measurement and control system based on RFSOC, specifically relating to the field of RFSOC control. The system includes an RFSOC chip, which integrates: a digital-to-analog conversion module, including eight 6.5GS / s digital-to-analog converters; an analog-to-digital conversion module, including eight 4GS / s analog-to-digital converters; an RF input module, connected to the digital-to-analog conversion module, including an RF input channel and a first signal conditioning circuit; and an RF output module, connected to the analog-to-digital conversion module, including an RF output channel and a second signal conditioning circuit. The digital-to-analog converter and the analog-to-digital converter are respectively connected to configurable IQ digital up / down conversion, a digitally controlled oscillator, a gain matrix, and decimation / interpolation filters. This invention fully leverages the advantages of the highly integrated RFSOC FPGA. It can be easily integrated into logic via an AXI interface. Furthermore, the present invention adds signal conditioning circuits to the DAC output and ADC output to achieve fine power adjustment.

In one embodiment, a frequency synthesizer comprises a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to produce a gain error signal.and to modify the bias control word based on the gain error signal to create a modified bias control word.

A method comprises generating an output clock in a digitally controlled oscillator, splitting the output clock to generate a split clock, generating a feedback clock based on the split clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock involves connecting a first current source to a capacitor according to a fixed delay with respect to the split clock, and connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.This involves connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and generating the feedback clock based on a voltage of the capacitor after connecting the first, second and third current sources to the capacitor.

A fractional divider, a digitally controlled oscillator, a phase-locked loop circuit are provided. The fractional divider includes a multi-modulus divider configured to generate a first divided clock based on an input clock and a sequence of division coefficients; a first flip-flop configured to generate a second divided clock based on the first divided clock; a second flip-flop configured to generate a third divided clock based on the first divided clock; a first multiplexer configured to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer configured to select one of the second divided clock and the third divided clock as a second output divided clock.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

The application relates to the field of satellite positioning technology and discloses a satellite signal receiving control method, device and equipment and a storage medium, the method comprising the following steps: receiving a frequency configuration instruction; determining a frequency configuration module to be switched according to a to-be-switched frequency in the frequency configuration instruction; adjusting the frequency of a local oscillator frequency signal of a transceiver through a digital control oscillator according to a target frequency in the frequency configuration instruction; controlling the local oscillator frequency signal to be input into a mixer of the frequency configuration module to be switched, so that the input signal of the frequency configuration module to be switched sequentially passes through the mixer, an analog-to-digital converter and a filtering and decimation module of the frequency configuration module to be switched, and then is matched with the target frequency, frequency configuration operation of the transceiver is completed, and the input signal is mixed with the local oscillator frequency signal in the mixer. The technical scheme of the application can adaptively configure the working frequency of the transceiver, and improve the detection precision and resolution of satellite signals.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

This invention relates to a fractional-number frequency division fully digital phase-locked loop (PLL) based on DTC and edge-time compensation algorithms, belonging to the field of radio frequency integrated circuit design. The overall circuit structure includes a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a programmable divider (MMD), a Sigma-delta modulator, and a digital time converter (DTC). The fractional-number frequency division function is implemented by the MMD, the Sigma-delta modulator, and the DTC. A time-domain compensation method is primarily used to design a quantization noise optimization circuit. By combining the DTC, low fractional-number spurious signals are achieved, and the fractional-number spurious signal output is then integrated into the PLL. Within the PLL, the Sigma-delta modulator output signal is integrated with the divided signal. The DTC then performs time-domain compensation based on the Sigma-delta modulator output signal and transmits it to the TDC for phase comparison with a reference signal to control the DCO's frequency output, thus achieving a high-performance fully digital PLL circuit with low fractional-number spurious signals.

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

A method includes generating an output clock in a digitally controlled oscillator, dividing the output clock to generate a divided clock, generating a feedback clock based on the divided clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock includes connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock, connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter, connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter, and generating the feedback clock based on a voltage of the capacitor after connecting the first, second, and third current sources to the capacitor.

A hardware apparatus includes a frequency locked loop (FLL) including a phase loop filter and a phase locked loop (PLL), such as an all-digital PLL (ADPLL), including a frequency loop filter. When the apparatus operates a controller, the controller provides a first control signal to the FLL and a second control signal to the PLL. The apparatus can also include a digitally controlled oscillator (DCO) and a portion of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a frequency divider receive input from the DCO. The controller forms a first loop with the first filter, the TDC, and the frequency divider, and the controller forms a second loop with the second filter, the TDC, and the frequency divider.

To make it possible to reduce jitter while suppressing an increase in circuit size of a phase-locked circuit. A phase-locked circuit includes a sample hold circuit configured to sub-sample an input signal, on the basis of a reference signal, a voltage-to-time converter configured to convert a voltage of the input signal sub-sampled by the sample hold circuit into a time difference, and a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter. The sample hold circuit, the voltage-to-time converter, and the time-to-digital converter may constitute a time domain ADC. The phase-locked circuit may further include a digitally-controlled oscillator configured to generate the input signal.

A digital phase-locked loop (DPLL) can include a dither source to provide a dither signal of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL can include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL can include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dither signal and the modulation signal; a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dither signal, thereby canceling any effect of the dither signal on the DPLL output signal; and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, thereby canceling any effect of a quantization error in the primary DSM.