49 results about "Digitally controlled oscillator" patented technology

An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.

A communication system includes a master communication device and a slave communication device. The master communication device includes a first signal generator, a second signal generator, a signal combiner, and a transmitting HBC (Human Body Communication) electrode. The signal combiner combines a first signal with a second signal, so as to generate a third signal. The transmitting HBC electrode transmits the third signal through a human body. The slave communication device includes a receiving HBC electrode, a signal splitter, a processor, and an injection-locked DCO (Digital Control Oscillator). The receiving HBC electrode receives a mix signal from the human body. The signal splitter divides the mix signal into a data signal and a synchronization signal. The injection-locked DCO performs a time synchronization process according to the synchronization signal.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

A communication system comprises a master control communication device and a slave communication device. The master control type communication device comprises a first signal generator, a second signal generator, a signal combiner and an emission type human body communication electrode. The signal combiner may combine the first signal with the second signal to generate a third signal. The emission type human body communication electrode can transmit a third signal through the human body. The slave communication device comprises a receiving type human body communication electrode, a signal distributor, a processor and an injection locking digital control oscillator. The receiving type human body communication electrode can receive a mixed signal from a human body. The signal distributor can divide the mixed signal into a data signal and a synchronization signal. The injection-locked digitally controlled oscillator may execute a time synchronization procedure according to the synchronization signal.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.

The invention provides a frequency control method and system for a digital control oscillator, and relates to the technical field of frequency control of the digital control oscillator, and the method comprises the steps: obtaining a current gate period length value of the digital control oscillator, carrying out the gate control counting of an output clock of the digital control oscillator based on the current gate period length value, and obtaining an in-gate counting sequence, calculating a noise estimator based on the in-gate counting sequence, determining a target gate period length value based on the noise estimator, determining an instantaneous frequency ratio based on the target gate period length value, calculating a smoothing factor based on the noise estimator and the target gate period length value, and smoothing the instantaneous frequency ratio based on the smoothing factor to obtain a smooth frequency ratio; the target frequency tuning word is determined based on the smooth frequency ratio, the output frequency of the digital control oscillator is adjusted based on the target frequency tuning word, and the method has the effects of improving the dynamic performance, the steady-state precision and the environment adaptive capacity of frequency control of the digital control oscillator.

In an embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to divide the output clock signal to generate a divided clock signal, a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to generate a gain error signal, and modify the bias control word based on the gain error signal to generate a modified bias control word.

The invention relates to quantization error and spurious suppression in digital phase-locked loops. A digital phase locked loop (DPLL) may include a dither source to provide a dither signal at an order to reach an integer bit over a set of fractional bits of a modulated signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include: a main delta-sigma modulator (DSM) for driving a main capacitor bank of the DCO based on a dither signal and a modulation signal; a first auxiliary DSM, associated with eliminating the influence of the dither signal on the DPLL output signal, for driving a first auxiliary capacitor bank of the DCO based on the dither signal; and a second auxiliary DSM for driving a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, associated with eliminating the effects of the quantization error of the main DSM.

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

This application provides a phase-locked loop (PLL), a control method, and a frequency source. It includes a controller, a time-to-digital converter (TD-to-digital converter), an arithmetic logic unit (ALU), a digitally controlled oscillator (DCO), and a frequency divider. The DCO outputs a linearly swept frequency signal based on a frequency control signal from the ALU. The frequency divider generates a divided frequency signal based on the output frequency of the DCO. The TD-to-digital converter outputs the phase difference between the divided frequency signal and a reference signal. The ALU outputs a frequency control signal based on the phase difference and a control code to adjust the output frequency of the DCO. The controller acquires the output signal of the TD-to-digital converter after a step point in the division ratio, and adjusts the control code until the output signal of the TD-to-digital converter after the step point is zero when the output signal is not zero. This method improves the linearity of the sawtooth waveform generated by the PLL at the step point.

In one embodiment, a frequency synthesizer comprises a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to produce a gain error signal.and to modify the bias control word based on the gain error signal to create a modified bias control word.

A method comprises generating an output clock in a digitally controlled oscillator, splitting the output clock to generate a split clock, generating a feedback clock based on the split clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock involves connecting a first current source to a capacitor according to a fixed delay with respect to the split clock, and connecting a second current source to the capacitor before the fixed delay according to a first programmable selection parameter.This involves connecting a third current source to the capacitor before the fixed delay according to a second programmable selection parameter and generating the feedback clock based on a voltage of the capacitor after connecting the first, second and third current sources to the capacitor.

A fractional divider, a digitally controlled oscillator, a phase-locked loop circuit are provided. The fractional divider includes a multi-modulus divider configured to generate a first divided clock based on an input clock and a sequence of division coefficients; a first flip-flop configured to generate a second divided clock based on the first divided clock; a second flip-flop configured to generate a third divided clock based on the first divided clock; a first multiplexer configured to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer configured to select one of the second divided clock and the third divided clock as a second output divided clock.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

The application relates to the field of satellite positioning technology and discloses a satellite signal receiving control method, device and equipment and a storage medium, the method comprising the following steps: receiving a frequency configuration instruction; determining a frequency configuration module to be switched according to a to-be-switched frequency in the frequency configuration instruction; adjusting the frequency of a local oscillator frequency signal of a transceiver through a digital control oscillator according to a target frequency in the frequency configuration instruction; controlling the local oscillator frequency signal to be input into a mixer of the frequency configuration module to be switched, so that the input signal of the frequency configuration module to be switched sequentially passes through the mixer, an analog-to-digital converter and a filtering and decimation module of the frequency configuration module to be switched, and then is matched with the target frequency, frequency configuration operation of the transceiver is completed, and the input signal is mixed with the local oscillator frequency signal in the mixer. The technical scheme of the application can adaptively configure the working frequency of the transceiver, and improve the detection precision and resolution of satellite signals.

A method includes generating an output clock in a digitally controlled oscillator, dividing the output clock to generate a divided clock, generating a feedback clock based on the divided clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock includes connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock, connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter, connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter, and generating the feedback clock based on a voltage of the capacitor after connecting the first, second, and third current sources to the capacitor.

To make it possible to reduce jitter while suppressing an increase in circuit size of a phase-locked circuit. A phase-locked circuit includes a sample hold circuit configured to sub-sample an input signal, on the basis of a reference signal, a voltage-to-time converter configured to convert a voltage of the input signal sub-sampled by the sample hold circuit into a time difference, and a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter. The sample hold circuit, the voltage-to-time converter, and the time-to-digital converter may constitute a time domain ADC. The phase-locked circuit may further include a digitally-controlled oscillator configured to generate the input signal.

A digital phase-locked loop (DPLL) can include a dither source to provide a dither signal of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL can include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL can include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dither signal and the modulation signal; a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dither signal, thereby canceling any effect of the dither signal on the DPLL output signal; and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, thereby canceling any effect of a quantization error in the primary DSM.

The present disclosure relates to an all-digital phase-locked loop and a correction method thereof. The present invention provides an all-digital phase-locked loop and a correction method thereof, wherein the all-digital phase-locked loop can include a digitally controlled oscillator, a time-to-digital converter coupled to the digitally controlled oscillator, and a normalization circuit coupled to the time-to-digital converter. The digitally controlled oscillator can be used to generate a clock signal according to a frequency control signal, the time-to-digital converter can be used to generate a digital output signal according to a phase difference between the clock signal and a reference signal, and the normalization circuit can be used to convert the digital output signal into a clock phase value according to a gain parameter. In particular, the normalization circuit can adjust the gain parameter according to a phase difference value between the clock phase value and a reference phase value.

The invention discloses a digital phase-locked loop system and a PLL output frequency modulation range real-time adjusting method thereof. The digital phase-locked loop system digitally controls an oscillator. The digital control oscillator comprises a plurality of groups of macro cells, and each group of macro cells comprises at least one macro cell; and each group of macro units is used for being switched on or switched off according to a configurable control signal input by a user, so that the switched-on macro units determine a PLL output frequency modulation range, and the PLL output frequency modulation range is adjusted according to an adjusting instruction input by the user. The effective frequency modulation range of the digital phase-locked loop system can be changed on the premise that a hardware circuit is not changed, so that the digital phase-locked loop system can flexibly adapt to various application scenes with huge differences, and the maximum application flexibility is obtained while the advantages of a single hardware design are kept.

The invention relates to an all-digital phase-locked loop phase tracking technique. The ADPLL circuit includes a phase comparator to compare a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCOCLK) signal output from the DCO. The phase comparator includes a first ADC connected to receive a REFP signal corresponding to a phase of the REFCLK signal via the first switch and output an ADC0 signal, and a second ADC connected to receive the signal REFP via the second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCOCLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control an operating frequency of the DCO based on the phase difference.

Interfaces between clock domains of an integrated circuit (IC) depend on synchronization of phase-locked loops (PLLs) that generate clocks in the different domains and on how each PLL responds to jitter in a shared reference clock. The well-controlled same bandwidth (and loop dynamic) for those PLLs renders the same and, therefore, ignorable reference jitter contribution. As a key component that determines a digital PLL bandwidth, digitally controlled oscillator (DCO) may have its gain vary with process, temperature, and supply IR drop from chip to chip or even module to module. A calibration circuit provides a gain correction factor to achieve a nominal gain in DCO as well as a desired / target PLL loop bandwidth. In some examples, the calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response and stores the gain correction factors in the calibration circuits.

A digital phase-locked loop (DPLL) may include a dithering source to provide a dithering signal that is on an order of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal, a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dithering signal in association with cancelling an effect of the dithering signal on the DPLL output signal, and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association with cancelling an effect of a quantization error of the primary DSM.

The application provides a digital control oscillator for a reconfigurable computing array, comprising a configuration module connected with a Cordic operation array, an output control module and an output cache module, and used for setting configuration information of the Cordic operation array, configuration information of the output control module and configuration information of the output cache module; the Cordic operation array is connected with the output control module, and used for generating a down-converted signal according to the configuration information of the Cordic operation array, and sending the down-converted signal to the output control module; the output control module is connected with the output cache module, and used for outputting the down-converted signal to the output cache module according to the configuration information of the output control module; and the output cache module is used for outputting a quadrature signal based on the down-converted signal according to the configuration information of the output cache module. The application further provides a signal generation method and electronic equipment, which can improve the NCO performance and reduce the NCO energy consumption.

A method includes causing a digital controlled oscillator to oscillate in a phase locked loop having a first closed loop transfer function, and changing the phase locked loop having the first closed loop transfer function to a phase locked loop having a second closed loop transfer function. The method also includes starting a charge-sharing locking process to correct phase errors in the digital controlled oscillator while the digital controlled oscillator oscillates in the phase locked loop having the second closed loop transfer function.

This invention relates to a multi-band finely tunable, wide-tuning-range numerically controlled oscillator, phase-locked loop, and chip. The numerically controlled oscillator includes n differential operational amplifier delay units, 2n array tuning circuits, and one digital-to-analog converter; the n differential operational amplifier delay units are cascaded, and the output V at the end of the cascade is... out +、V out - and the input V at the cascade start end in +、V in The positive and negative terminals of the circuit are reversed to form a ring structure; any one differential operational amplifier delay unit is connected to two array tuning circuits; a digital-to-analog converter is used to provide control voltage to the array tuning circuits. This invention significantly reduces oscillator phase noise through the combination of a tail current source and capacitor filtering, while simultaneously enabling a wide tuning range by adjusting the operating state of the array tuning circuits. The digital-to-analog converter achieves 256-bit fine-level voltage control, allowing for significantly precise operation of the output frequency, thus meeting the higher resolution requirements of a fully digital phase-locked loop.

The application provides a quartz gyro digital circuit phase compensation method and system, the method comprising: generating a co-directional signal and a quadrature signal through a digital control oscillator in a microprocessor; co-directionally demodulating a driving displacement signal output by an ADC in the microprocessor by taking the co-directional signal as a reference signal, and quadrature demodulating the driving displacement signal by taking the quadrature signal as a reference signal; and performing angle rotation on the driving displacement signal after co-directional demodulation and quadrature demodulation according to the time delay of a driving loop in a digital circuit of a quartz gyro, to obtain a new co-directional signal and a new quadrature signal. The application realizes phase compensation, guarantees the phase stability of the driving loop, accurately, reliably and efficiently controls the driving frequency of a digital quartz gyro, improves the performance of the quartz gyro, and is simple in design, saves devices and reduces costs.

The present disclosure relates to an oscillator, such as a Digitally Controlled Oscillator (DCO), having first capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and second capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second capacitor banks including at least one modulation capacitor bank

Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.