42 results about "Retiming" patented technology

Linear unretimed interfaces lack clock and data recovery and retiming circuits implemented on a sophisticated digital signal processor. When the interface is not a retimed interface, it can be especially useful to extract some information about the link to allow for debugging and optimization of system deployment. An efficient solution can be implemented in unretimed interfaces to compute metrics such as the impulse response and signal histogram. Having the metrics allows for the solution to check and monitor the quality and the status of the link. Based on the link quality and status information, it is possible to address non-idealities and optimize performance of the unretimed interfaces and the link.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

The application discloses an expansion board and a server, and relates to the technical field of servers, and comprises a logic controller, at least one power supply domain and at least one memory on the expansion board. The power supply domain and the memory are in one-to-one correspondence, the power supply domain can comprise a plurality of re-timers and a plurality of level converters, the level converters can be connected with the re-timers in one-to-one correspondence, and correspondingly, the re-timers belonging to one power supply domain can share one memory. In this way, the plurality of re-timers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. Moreover, in the process of upgrading or modifying firmware, the number of memories that need to be programmed and verified is greatly reduced, the operation and maintenance complexity is reduced, and then, the time cost is also reduced. In summary, through the plurality of re-timers sharing one memory, the cost can be reduced.

The invention discloses an expansion board and a server, and relates to the technical field of servers, and the expansion board can comprise a logic controller, at least one power domain and at least one memory. Wherein the power domains and the memories are in one-to-one correspondence, the power domains can comprise a plurality of retimers and a plurality of level translators, the level translators can be connected with the retimers in one-to-one correspondence, and correspondingly, the retimers belonging to one power domain can share one memory. Thus, a plurality of retimers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. In addition, in the firmware upgrading or modifying process, the number of memories needing to be burnt and verified is greatly reduced, the operation and maintenance complexity is reduced, and then the time cost is also reduced. In conclusion, a plurality of re-timers share one memory, so that the cost can be reduced.

The invention discloses an intelligent media synthesis method and system based on AI cross-modal conversion, and relates to the technical field of artificial intelligence, and the system comprises the following modules: a multi-modal data specification access module, which is used for receiving multi-source heterogeneous media input data, which comprises text data, voice data, image data and video data, and performing format analysis, sampling rate identification, frame rate identification and timestamp extraction processing on the multi-source heterogeneous media input data. According to the method, the features of different modes are mapped to a unified semantic representation space, a semantic gap between the modes is effectively bridged, a system can more accurately understand and process cross-modal semantic information, the accuracy of cross-modal conversion is improved, and by constructing a unified time axis model and carrying out time alignment, resampling and fragment retiming, the accuracy of cross-modal conversion is improved. The problems of synchronization and alignment of the multi-modal data in the time dimension are solved, and accurate time sequence synchronization of the synthetic content is ensured.

In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a ratio between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame of the packet.

A retimer device is provided that includes an elastic buffer, a receiver, and a controller. The elastic buffer adds or subtracts data in the elastic buffer to compensate for different bit rates of two devices to be connected by a link, where the retimer is located between the two devices on the link. The receiver receives a data stream to be transmitted between the two devices on the link. The controller determines a modification to one or more characteristics of the link based on the data stream, and causes a size of the elastic buffer to change from a first size to a second size based on the modification.

A retimer path control method includes: receiving a first bitstream, where the first bitstream includes a first field, the first field includes capability information of a retimer, and the capability information indicates whether the retimer supports a low latency path; and sending a second bitstream to the retimer, where the second bitstream includes a second field, the second field includes first enter control information, the first enter control information indicates whether the retimer enters the low latency path, and the low latency path is a path with lowest latency in data transmission paths of the retimer. The path of the retimer can be effectively controlled.

Aspects of a re-timer-based isolator provide galvanic isolation between a first side of a system including a high voltage source and a second side of the system that may contact a person. An equalizer arranged with a physical layer on a first substrate is isolated from re-timer components arranged on a second substrate.

Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

A technique of min-cut based retiming of a netlist includes forming a min-cut based retiming graph based on a netlist of a circuit design. Forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph. The technique further includes computing a min-cut of the circuit design based on the min-cut based retiming graph, where the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph. Based on the min-cut, a behaviorally equivalent retimed netlist is then formed, including in the particular region.

The embodiment of the utility model discloses a wafer level chip integrated structure. The wafer-level chip integrated structure comprises a plurality of functional components; the plurality of functional components are arranged in an array; the functional component comprises a first functional chip, a second functional chip and a retiming unit; the second functional chips are arranged around the first functional chip in an array manner; the retiming unit is arranged between the second functional chips arranged in the array; the first functional chips are connected through a retiming unit; the retiming unit is used for regenerating and retiming the signal. According to the technical scheme provided by the embodiment of the utility model, the second functional chips are arranged around the first functional chip in the array manner, the re-timing units are arranged among the second functional chips arranged in the array manner to form the functional components, and the plurality of functional components are arranged in the array manner to form the wafer-level chip integrated structure, so that the chip performance is improved, the integration level is improved, and the production cost is reduced. And stable transmission of signals between the chips is ensured.

The invention discloses a communication method of a processor and a retimer, an electronic device and a readable storage medium, and relates to the technical field of communication, and the method comprises the steps: disassembling a bidirectional link establishment process of a processor receiving end and the retimer into two independent stages: the retimer sends a first signal, and the processor sends a second signal, each stage has a clear transmission direction and a detection main body, the signal receiving state can be detected in real time, and an abnormal link can be accurately positioned. Respectively designing repair measures for the two-stage abnormity: resetting and re-initializing the signal if the signal receiving end of the processor cannot receive the first signal; and if the retimer cannot receive the second signal, the substrate management controller restarts the system side receiving end of the substrate management controller. Therefore, interference to normal components is reduced, the problems of rough exception handling and high recovery cost of related methods are solved, and the link establishment efficiency and the system resource utilization rate are improved.

Provided are a storage device group, a storage system, and an operating method of a storage device. The storage device group includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device, and an operation circuit configured to perform an operation function. The storage device includes a first port connected to the retimer, a second port connected to the operation circuit, and a controller configured to control data transmission and reception via the first port and the second port.

A technique of min-cut based retiming of a netlist includes forming a min-cut based retiming graph based on a netlist of a circuit design. Forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph. The technique further includes computing a min-cut of the circuit design based on the min-cut based retiming graph, where the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph. Based on the min-cut, a behaviorally equivalent retimed netlist is then formed, including in the particular region.

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.

An H-bridge integrated laser driver optimizes power consumption, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and direct modulated laser diode (DML) applications, VCSEL / silicon photonics, and other applications requiring high-swing drivers or control of impedance. The laser driver includes a retimer for converting low-speed parallel data into a high-speed serial bit stream and an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protection device is coupled between the M-bit DAC and the N-bit DAC. A first DC level shift pre-driver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level shift pre-driver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protection device. The laser driver can be integrated on a CMOS communication chip.

The invention discloses a data path switching method and a retiming chip, and the method comprises the steps: detecting whether a root device at the upstream of a retiming controller and a terminal device at the downstream of the retiming controller are in a receiving end locking state or not under the condition that a data path is a normal mode path, the normal mode path comprises a forwarding mode path and an execution mode path; if both the root device and the terminal device are in the receiving end locking state, starting an error injection function for an ordered training set, so that both the root device and the terminal device are maintained in the receiving end locking state; and switching the data path into a path in a low-delay mode, and closing the error injection function. In this way, it can be guaranteed that switching of the low-delay access is reliably completed, the complexity of switching of the low-delay access is reduced, and the use scene is expanded.

The application discloses a clock data recovery circuit for half-rate data re-timing, comprising a switched capacitor module, a filter capacitor, a two-stage differential ring oscillator, a clock buffer, a four same OR gate module and a re-timer module, wherein the switched capacitor module controls a sampling period and a sampling frequency by using input binary random data, samples a clock signal and outputs a sampling voltage signal; the filter capacitor filters the sampling voltage signal and outputs a control voltage; the two-stage differential ring oscillator generates four clock signals according to the control voltage; the clock buffer obtains the four square wave clock signals; the four same OR gate module outputs a double frequency clock signal and feeds back to the switched capacitor module; and the re-timer module samples binary random data according to two square wave clock signals. The application can significantly reduce power consumption, reduce area, save cost, and has good jitter performance of recovered clock and jitter tolerance performance of recovered data.

The present disclosure provides a wiring method and system, a device, a storage medium, and a chip. The wiring method comprises: cross-connecting a storage medium to at least two control nodes so that dual ports of the storage medium are respectively connected to different processor ports of different control nodes; merging long distance lines between the at least two control nodes and the storage medium using re-timers; and dynamically configuring a physical address corresponding to each line of the control node so that a physical address of the storage medium remains consistent when connected to different control nodes. The wiring method can solve the problem of the count of re-timers under the premise of consistent physical addresses, thereby optimizing the wiring layout, reducing redundant architecture, and improving the operation efficiency of the entire machine.

This invention discloses a two-stage fractional-number coordinated Asia-Pacific Hertz frequency synthesizer, comprising: a first-stage fractional-number phase-locked loop (PLL) that improves the resolution of the reference signal through low-precision fractional-number division to meet the condition of no blind zone, and uses a digital time converter to eliminate quantization noise caused by fractional-number division to generate a local oscillator signal; and a second-stage fractional-harmonic mixing PLL that improves the resolution of the local oscillator signal through high-precision fractional-number division to achieve arbitrary frequency point generation, and uses multi-path retiming to cancel quantization noise technology to eliminate quantization noise caused by fractional-number division, mixes and filters the high-frequency fundamental signal and the local oscillator signal to generate an intermediate frequency (IF) signal, performs frequency and phase discrimination and weighted summation on the IF signal and the multi-path retiming processed signal respectively to generate a quantization noise-compensated current signal, controls the harmonic extension VCO after low-pass filtering to generate a high-frequency fundamental signal, and generates an Asia-Pacific Hertz band output signal based on the high-frequency fundamental signal.

This invention discloses an avalanche signal dejitter circuit, comprising a second phase shifter, a second discriminator, and a D flip-flop connected in sequence. The input terminal of the second phase shifter receives a coincidence signal with the same frequency and origin as the gate signal. The output terminal of the second discriminator is connected to the clock input terminal CLK of the D flip-flop. The data input terminal D of the D flip-flop receives the extracted detector pulse signal. Under the action of the coincidence signal, the leading edge of the detector pulse signal is retied to the leading edge of the coincidence signal by the high-speed D flip-flop. This invention also discloses an avalanche signal dejitter method and a single-photon detector using this avalanche signal dejitter circuit. Through the technical solution of this invention, the leading edge of the avalanche signal at different times within each sinusoidal gate cycle can be retied to a position with a relatively fixed positional relationship with the gate signal. Real-time retiming of the input avalanche signal can effectively reduce factors affecting avalanche signal jitter.

The application discloses a re-timer configuration method and electronic equipment, relates to the technical field of signal transmission, and comprises the following steps: determining the current configuration state of a re-timer; in response to the current configuration state indicating that the re-timer is not powered on, waiting for a first time interval and then re-acquiring the configuration state of the re-timer; in response to the current configuration state indicating that the re-timer is powered on, acquiring the configuration progress of the re-timer; in the case that the configuration progress is not configured, performing initialization configuration on the re-timer; in the case that the configuration progress is the initialization configuration completed, performing a configuration operation of a channel side receiving link on the re-timer; and in the case that the configuration progress is the configuration operation of the channel side receiving link completed and the system driver is loaded, performing a configuration operation of a system side receiving link on the re-timer. The application solves the problem of low re-timer configuration efficiency in the prior art.

A test and measurement device including a first input structured to acquire data from a sideband data communication channel that carries data related to one or more high speed data channels between a host and a device, a second input structured to acquire data signals carried on the related high speed data channel, and one or more processors structured to send a command to provoke the host to send a retiming message that includes one or more scrambling codes that were used to encode data signals on the coupled high speed data channel, extract the one or more scrambling codes from the retiming message, convert the data signals received on the coupled high speed data channel to coded data, descramble the coded data using the one or more scrambling codes extracted from the retiming message, and search the descrambled data for a predetermined code sequence. Methods are also described.

Various adaptive retiming methods and apparatus. An illustrative retimer device takes the form of an integrated circuit having: at least one input contact configured to receive an input PCIe signal; a retimer module configured to convert the input PCIe signal to a stream of digital symbols, and further configured to convert the stream of digital symbols to a retimed PCIe signal; a multiplexer, the multiplexer having a first selectable input, the first selectable input configured to be used for receiving the PCIe signal which is retimed; a bypass path configured to provide an analog PCIe signal to a second selectable input of the multiplexer; and at least one output contact coupled to an output of the multiplexer to provide an output PCIe signal.

A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

Techniques and apparatuses are described for implementing a power-efficient synchronous-source data network. In an example aspect, a data network (112) provides a communication interface between a data source (110) and multiple subsystems (108) on a system-on-chip (106). The data network (112) includes pipeline circuits that can propagate multiple clock enable signals upstream from the multiple subsystems (108) towards the data source (110). The upstream propagation of these clock enable signals through the pipeline circuits enables the data network (112) to identify paths along which a data signal and a clock signal are to propagate downstream from the data source (110) towards the multiple subsystems (108). The clock enable signals can be asynchronous signals, which obviates the need for a synchronizer within the pipeline circuits. With the described techniques, dynamic power of the data network (112) can be reduced by at least 50% compared to other networks with "always-on" retimer circuits.

Methods and systems are described herein for exchanging retimer training status and state machine (RTSSM) status information between a plurality of circuit dies of a multi-chip module utilizing a ring bus configured to carry a multi-bit lane status signal using a plurality of time slots, the ring bus interconnecting the plurality of circuit dies into a ring of circuit dies, wherein each circuit die outputs stored aggregate RTSSM status information onto the ring bus to the next circuit die in the ring and stores the aggregate RTSSM status information from the preceding circuit die in the ring until each circuit die accrues the complete multi-die RTSSM status information for all of the circuit dies. Based on the complete multi-die RTSSM status information, each circuit die may synchronously execute state changes in the upstream and / or downstream RTSSMs on the circuit die.