158 results about "Retiming" patented technology

A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.

A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.

A novel method for retiming a portion of a media content (e.g., audio data, video data, audio and video data, etc.) in a media-editing application is provided. The media editing application includes a user interface for defining a range in order to select a portion of the media content. The media editing application performs retiming by applying a speed effect to the portion of the media content selected by the defined range. For a faster speed effect, the media editing application retimes the selected portion of the media content by sampling the media content at a faster rate. For a slower speed effect, the media editing application retimes the selected portion of the media content by sampling the content at a slower rate.

A system and method of selecting and viewing communication traffic transmitted over an optical channel selected from among a plurality of possible channels without disrupting the communication traffic occurring over the selected channel or other channels is presented. The system and method includes an optical channel analyzing switch which taps each of the possible plurality of channels and selects a specific channel for routing to a network analyzer. The signal on the selected channel, prior to being analyzed by the network analyzer, undergoes clock and data recovery and retiming/recombination to mitigate contamination from routing and switching the selected original signal between the signal source and the network analyzer. The retimed and recombined channel signal results in a signal, as presented to the network analyzer, which is representative of the original channel signal.

An integrated circuit. The integrated circuit is usable in a transceiver module. The integrated circuit includes an input port that is configured to receive a data stream. A clock port on the integrated circuit is configured to receive a reference clock diplexed with another signal or voltage used by the integrated circuit. An eye opening circuit is connected to the input port and clock. The eye opening circuit is configured to retime the data stream received at the input port. An output port is connected to the eye opening circuits The output port is configured to transmit a retimed signal from the eye opening circuit to a device external to the integrated circuit. A bypass circuit is connected to the input port and the output port. The bypass circuit may selectively bypass the eye opening circuit.

A method for derivation and abstraction of test models for validation of industrial designs using guided simulation is described. The method employs automatic abstractions for the test model which reduce its complexity while preserving the class of errors that can be detected by a transition tour. A method for design validation comprising generating a state-based test model of the design. The test model is abstracted by retiming and latch removal. Finally, a validation technique is applied on the abstracted test model. First, the number of internal (non-peripheral) latches in a design is minimized via retiming using a method of Maximal Peripheral Retiming (MPR). According to the MPR method, internal latches are retimed to the periphery of the circuit. Subsequently, all latches that can be retimed to the periphery are automatically abstracted in the test model. The validation technique may comprise of model checking, invariant checking or simulation using test sequences generated from the abstracted test model.

The invention relates to a heating control method for electrical cooking equipment. The heating control method includes: continuously heating food, stopping heating til the food reaches to a first preset temperature; judging whether the heating stopping time reaches a first preset time or not; if yes, acquiring capacity of the food according to a current temperature value of the food and a preset capacity judging temperature value; heating the food and retiming after the capacity of the food is acquired, and in a preset periodic time, judging whether the food is boiling or not according to the current temperature value of the food, a periodic bottom temperature and a preset boiling judging temperature value. The electrical cooking equipment is provided with a fuzzy reasoning functional program capable of accurately controlling heating thermal power.

In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.

A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used to instantiate logic described therein, and to define one or more black boxes as being functionally inverse of the logic. Each instantiated logic and its functionally inverse black box are thereafter added to the reference IC design to obtain a transformed reference IC design. A transformed retimed IC design is also obtained by addition of the instantiated logic(s) and functionally inverse black box(es) to the retimed IC design. These two transformed IC designs are then supplied to an equivalence checker, for formal verification.

A bit synchronization circuit comprising an initial phase determining unit for rapidly determining, during a period of receiving a preamble of burst data, a clock with a phase synchronized with received burst data from among multi-phase clocks having the same frequency as an internal reference clock and a phase tracking unit for modifying the synchronized phase clock responsive to phase variation of received data during a period of receiving a payload of burst data by taking the synchronized phase clock determined by the initial phase determining unit as an initial phase. The bit synchronization circuit retimes burst data with a data retiming clock having a predetermined phase relation with the synchronized phase clock and outputs the burst data in synchronization with the internal reference clock.

An active cable that is configured to communicate over much of its length using one or more optical fibers, and that includes an integrated electrical connector at at least one end. The active cable includes an integrated retiming mechanism. Thus, multiple links of cable may be used while reducing the chance that the jitter will exceed allowable limits. The cable may be an electrical to optical cable, and electrical to electrical cable, or one of many other potential configurations.

A three dimensional (3D) stacked integrated circuit (IC) design-for-Testing (DfT) die-level wrapper boundary register having a bypass mode and design-level DfT delay recovery techniques are provided. Die wrappers that contain boundary registers at the interface between dies can be inserted into 3D ICs where the boundary registers include a gated scan flop with a bypass line passing the functional input to a through-silicon-via (TSV) in a manner avoiding the clocked stages of the gated scan flop during functional operation. A retiming process can be applied during design layout using a simulation/routing tool or standalone program to recover the additional delay added to the TSV paths by the DfT insertion. Retiming can be performed at both die and stack level, and in further embodiments, logic redistribution across adjacent dies of the stack can be performed for further delay optimization.

A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.

Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.

The present invention refers to a memory system with a controller and a memory device with a communication channel with a data path and a timing path coupling the controller with the memory device. The communication channel has different propagation times for the data path and the timing path exchanging a information signal and a timing signal between the controller and the memory device. The timing signals are used for determining the value of the information signal, and a retiming circuit that is connected with the communication channel compensates, depending on a compensation signal on an input, the delay between the data path and the timing path for exchanging a information signal and a timing signal between the controller and the memory device.

An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

A network diagnostic device or component such as a network analyzer or a jammer that is placed in-line between two nodes in a network to perform a flow control operation transparently without the requirement of a separate link layer implementation. The network diagnostic device may include a diagnostic module configured to perform network analyzer operations, a memory a first flow control module a second flow control module. In some embodiments, when performing the flow control operation, various modules and/or components may cause the network diagnostic device to enter a first pass-through mode and to then enter into a first flow control handshaking mode from the first pass-through mode. The various modules and/or components may also cause the network diagnostic device to enter a second pass-through mode from the first flow control handshaking mode and to then enter into a second flow control handshaking mode from the first pass-through mode.