76 results about "Retiming" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention provides a retimer and an electronic device, when the retimer enters an error code detection mode, the retimer is switched to a loopback mode, so that the output end and the input end of a second physical layer module are conducted; when a first-order test is carried out, a code stream generation module generates a pseudo-random digital stream according to first source data information in a first source register, and transmits the pseudo-random digital stream to a first data coding module; and the first code stream detection module verifies an output code stream of the second data decoding module according to the first source data information to confirm whether an error code exists or not. By generating and transmitting the pseudo-random digital stream, whether an error code occurs in a link transmission process among the first data coding module, the second physical layer module and the second data decoding module in the retimer is determined, so that when the error code exists, a module which may have a fault can be determined, and error code fault positioning is realized. And a worker can repair the device conveniently.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

An illustrative retimer includes: an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream; a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream; core circuitry having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to convey the downlink symbol stream from the upstream receiver to the downstream transmitter via a receive clock domain component, a core clock domain component, and a transmit clock domain component. The downstream bypass path is configurable to convey the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components. The controller is configured to disable a clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

Linear unretimed interfaces lack clock and data recovery and retiming circuits implemented on a sophisticated digital signal processor. When the interface is not a retimed interface, it can be especially useful to extract some information about the link to allow for debugging and optimization of system deployment. An efficient solution can be implemented in unretimed interfaces to compute metrics such as the impulse response and signal histogram. Having the metrics allows for the solution to check and monitor the quality and the status of the link. Based on the link quality and status information, it is possible to address non-idealities and optimize performance of the unretimed interfaces and the link.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The invention discloses a fault processing method and a related device, and relates to the field of information processing, and the method comprises the steps: monitoring the state of a link connected with a retimer, and the retimer can carry out the retiming of a connected storage structure through the link; and representing the link fault based on the state of the link, and controlling the retimer to reestablish the link with the storage structure.

The invention provides a control word digital adjustment circuit and a retimer based on a decimal N frequency division phase-locked loop. The control word digital adjustment circuit comprises a digital low-pass filtering module and a control word adjustment module, wherein the digital low-pass filtering module is used for filtering high-frequency jitter and part of low-frequency jitter in an initial control word so as to generate a filtering control word; the control word adjusting module is used for adjusting the filtering control word based on a writing pointer and a reading pointer of a first-in first-out buffer in the retimer so as to generate an adjusting control word; the adjustment control word is used for replacing the initial control word to serve as input of a transmitter fractional N frequency division phase-locked loop in the re-timer. According to the invention, the problem of frequency deviation jitter of RX Clock and TX Clock easily caused by wrong reading numerical value of an asynchronous interface of the FCW in the existing scheme can be effectively solved.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

This invention provides a phase code digital low-pass filter circuit and a re-timer based on a PI-based architecture. The phase code digital low-pass filter circuit includes a first accumulation unit and a downsampling decimation module. The first accumulation unit accumulates the initial frequency control information generated by the clock data recovery module of the re-timer to generate a phase signal. The downsampling decimation module downsamples the phase signal to generate a filtered phase code. The filtered phase code is used to generate the transmit channel clock. This invention effectively solves the problems of high implementation cost, large footprint, and easy introduction of additional analog non-ideal factors in existing digital filtering solutions.

A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a control logic configured to generate a control signal based at least in part on the second clock signal; and two or more analog-to-digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, where the multiplexer is configured to select a set of the second number of inputs to be output, where the selected set of the second number of inputs is based at least in part on the control signal. The apparatus includes one or more unit ADCs, wherein respective outputs of the one or more unit ADCs are coupled as inputs to the multiplexer.

The application discloses an expansion board and a server, and relates to the technical field of servers, and comprises a logic controller, at least one power supply domain and at least one memory on the expansion board. The power supply domain and the memory are in one-to-one correspondence, the power supply domain can comprise a plurality of re-timers and a plurality of level converters, the level converters can be connected with the re-timers in one-to-one correspondence, and correspondingly, the re-timers belonging to one power supply domain can share one memory. In this way, the plurality of re-timers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. Moreover, in the process of upgrading or modifying firmware, the number of memories that need to be programmed and verified is greatly reduced, the operation and maintenance complexity is reduced, and then, the time cost is also reduced. In summary, through the plurality of re-timers sharing one memory, the cost can be reduced.

The invention discloses an expansion board and a server, and relates to the technical field of servers, and the expansion board can comprise a logic controller, at least one power domain and at least one memory. Wherein the power domains and the memories are in one-to-one correspondence, the power domains can comprise a plurality of retimers and a plurality of level translators, the level translators can be connected with the retimers in one-to-one correspondence, and correspondingly, the retimers belonging to one power domain can share one memory. Thus, a plurality of retimers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. In addition, in the firmware upgrading or modifying process, the number of memories needing to be burnt and verified is greatly reduced, the operation and maintenance complexity is reduced, and then the time cost is also reduced. In conclusion, a plurality of re-timers share one memory, so that the cost can be reduced.

A phase interpolator may include a decoding logic circuit. The decoding logic circuit may take as input an input control code and an update clock. The decoding logic circuit may generate one or more outputs which may be input to a retiming circuit. The retiming circuit may generate retimed outputs which may be input to a delay modulation circuit. The delay modulation circuit may generate a delayed clock select control signal and a delayed phase select control signal. The delayed clock select control signal and delayed phase select control signal may be input to a phase interpolator circuit and may generate an output clock based on two or more multi-phase input clocks. The delayed clock select control signal and delayed phase select control signal may eliminate overshoot and undershoot events in the output clock.

The invention discloses an intelligent media synthesis method and system based on AI cross-modal conversion, and relates to the technical field of artificial intelligence, and the system comprises the following modules: a multi-modal data specification access module, which is used for receiving multi-source heterogeneous media input data, which comprises text data, voice data, image data and video data, and performing format analysis, sampling rate identification, frame rate identification and timestamp extraction processing on the multi-source heterogeneous media input data. According to the method, the features of different modes are mapped to a unified semantic representation space, a semantic gap between the modes is effectively bridged, a system can more accurately understand and process cross-modal semantic information, the accuracy of cross-modal conversion is improved, and by constructing a unified time axis model and carrying out time alignment, resampling and fragment retiming, the accuracy of cross-modal conversion is improved. The problems of synchronization and alignment of the multi-modal data in the time dimension are solved, and accurate time sequence synchronization of the synthetic content is ensured.

In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.

A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a ratio between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame of the packet.

The application relates to a re-timer, comprising an analog signal front-end processing module, a clock data recovery module, a clock trigger driving module, and further comprising: a phase control decision device, which is used for fixed-point sampling and decision of the processed analog signal based on an optimal sampling clock phase to obtain a digital signal, and scoring the reliability of each bit of the digital signal; a forward error correction decoding module, which is used for error correction and repair of the digital signal according to the score of the reliability of each bit of the digital signal to obtain a repaired digital signal; and the repaired digital signal is sent into the clock trigger driving module to be converted into an analog differential signal. The application integrates the forward error correction function in the re-timer, corrects the error code of the received code stream, avoids the uniform transmission of the error code to the receiving end, can efficiently process the error code, reduces the link delay, prolongs the transmission distance, and further improves the stability and reliability of the system.

A retimer device is provided that includes an elastic buffer, a receiver, and a controller. The elastic buffer adds or subtracts data in the elastic buffer to compensate for different bit rates of two devices to be connected by a link, where the retimer is located between the two devices on the link. The receiver receives a data stream to be transmitted between the two devices on the link. The controller determines a modification to one or more characteristics of the link based on the data stream, and causes a size of the elastic buffer to change from a first size to a second size based on the modification.

A retimer path control method includes: receiving a first bitstream, where the first bitstream includes a first field, the first field includes capability information of a retimer, and the capability information indicates whether the retimer supports a low latency path; and sending a second bitstream to the retimer, where the second bitstream includes a second field, the second field includes first enter control information, the first enter control information indicates whether the retimer enters the low latency path, and the low latency path is a path with lowest latency in data transmission paths of the retimer. The path of the retimer can be effectively controlled.

Aspects of a re-timer-based isolator provide galvanic isolation between a first side of a system including a high voltage source and a second side of the system that may contact a person. An equalizer arranged with a physical layer on a first substrate is isolated from re-timer components arranged on a second substrate.

Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

A technique of min-cut based retiming of a netlist includes forming a min-cut based retiming graph based on a netlist of a circuit design. Forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph. The technique further includes computing a min-cut of the circuit design based on the min-cut based retiming graph, where the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph. Based on the min-cut, a behaviorally equivalent retimed netlist is then formed, including in the particular region.

The embodiment of the utility model discloses a wafer level chip integrated structure. The wafer-level chip integrated structure comprises a plurality of functional components; the plurality of functional components are arranged in an array; the functional component comprises a first functional chip, a second functional chip and a retiming unit; the second functional chips are arranged around the first functional chip in an array manner; the retiming unit is arranged between the second functional chips arranged in the array; the first functional chips are connected through a retiming unit; the retiming unit is used for regenerating and retiming the signal. According to the technical scheme provided by the embodiment of the utility model, the second functional chips are arranged around the first functional chip in the array manner, the re-timing units are arranged among the second functional chips arranged in the array manner to form the functional components, and the plurality of functional components are arranged in the array manner to form the wafer-level chip integrated structure, so that the chip performance is improved, the integration level is improved, and the production cost is reduced. And stable transmission of signals between the chips is ensured.

The invention discloses a communication method of a processor and a retimer, an electronic device and a readable storage medium, and relates to the technical field of communication, and the method comprises the steps: disassembling a bidirectional link establishment process of a processor receiving end and the retimer into two independent stages: the retimer sends a first signal, and the processor sends a second signal, each stage has a clear transmission direction and a detection main body, the signal receiving state can be detected in real time, and an abnormal link can be accurately positioned. Respectively designing repair measures for the two-stage abnormity: resetting and re-initializing the signal if the signal receiving end of the processor cannot receive the first signal; and if the retimer cannot receive the second signal, the substrate management controller restarts the system side receiving end of the substrate management controller. Therefore, interference to normal components is reduced, the problems of rough exception handling and high recovery cost of related methods are solved, and the link establishment efficiency and the system resource utilization rate are improved.

Provided are a storage device group, a storage system, and an operating method of a storage device. The storage device group includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device, and an operation circuit configured to perform an operation function. The storage device includes a first port connected to the retimer, a second port connected to the operation circuit, and a controller configured to control data transmission and reception via the first port and the second port.

This invention discloses a transmitter equalization drive circuit and a method for processing the signal to be transmitted. The circuit includes: a serialization and retiming module for generating multiple parallel data streams based on the signal to be transmitted; a data selector module connected to the serialization and retiming module for receiving a clock signal corresponding to each parallel data stream and generating process data including front-tap data, main-tap data, first back-tap data, and second back-tap data based on the parallel data and the clock signal; a pulse generation module connected to the data selector module for receiving the process data and generating front-tap equalization pulses and first back-tap equalization pulses; and a hybrid equalization drive module connected to the pulse generation module and the data selector module for receiving the front-tap data, front-tap equalization pulses, main-tap data, first back-tap equalization pulses, and second back-tap data to generate the output signal of the signal to be transmitted. This circuit improves the signal quality of the output signal.

Receiving, by an upstream dummy port of a first circuit die of a multi-die integrated circuit module (ICM), a plurality of serial data channels associated with the PCIe data link; corresponding deserializing channel specific data code words are generated; providing the deserialized channel specific data codeword for transmission via a downstream dummy port of the first circuit die of the multi-die ICM, the downstream dummy port having a PCIe data link through to a first endpoint; in response to a failure of the PCIe data link through the first endpoint, rerouting the deserialized channel specific data codeword to a second circuit die of the multi-die ICM via an inter-die data interface employing an inter-die adaptation layer protocol; receiving, by the second circuit die, the deserialized channel specific data codeword from the inter-die data interface; and through a second downstream pseudo port, sending the deserialized channel specific data code word to a second endpoint through a second PCIe data link.

A technique of min-cut based retiming of a netlist includes forming a min-cut based retiming graph based on a netlist of a circuit design. Forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph. The technique further includes computing a min-cut of the circuit design based on the min-cut based retiming graph, where the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph. Based on the min-cut, a behaviorally equivalent retimed netlist is then formed, including in the particular region.

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.