727 results about "SerDes" patented technology

A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

An integrated circuit which utilizes a serial trace output interface instead of the known parallel trace output interface for transferring test data from the integrated circuit, thereby reducing the number of pins needed for outputting test data. Specifically, a preferred embodiment of the present invention uses a serializer/deserializer (SERDES) interface which captures output testing data in frames, serializes the framed data, and outputs the serialized data on at least one pin. The output serialized data is deserialized, and the deserialized data is synchronized in order to find the frame boundaries. The synchronized frames are then unpacked to retrieve the original testing data. Another preferred embodiment of the present invention uses a bi-directional SERDES both for inputting testing and debugging instructions and data from the analysis software and for outputting testing and debugging results and data to the analysis software.

In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x¹⁰+x³+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x⁶+1.

A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent. In this case a signal is generated when the last word has been sent in the serializer that causes new data to be loaded for sending. Half duplex and full duplex configurations as disclosed. Similar, corresponding operations occur at the deserializer.

A clock data recovery and a serial-parallel conversion circuit based on over sampling for the receiver of a high speed serial transceiver comprise PLL module, a data space over sampling module, an edge detection and data recovery module, a judgment module, clock recovery module, a clock frequency-division module and a SerDes module. The data space over sampling module adopts the 16-phase equal-interval clock outputted by the PLL module to continuously sample the 24 bit data of 3 bytes, stores the sampled data in 16 groups of registers, and each group includes 24 registers. The corresponding bits of adjacent two groups of registers carry out OR operation to finish the edge detection, the detection results are added together in grouping mode, the fastest sampling clock corresponding to the group of data with the maximum distance value can be used as the recovery clock, the data sampled through the sampling clock can be used as recovery data, the sampling clock is performed with 8-fractional frequency to synchronize the bytes of the recovery data so as to finish the clock data recovery and serial-parallel conversion. The invention has clear structure, higher performance and reliable operation.

The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection. Input test data is provided to a first serialize or deserialize data communication channel, and is successively serialized and deserialized through each corresponding serialize data communication channel and deserialize data communication channel to provide output test data. The output test data and the input test data are then compared, with SERDES devices having acceptable or unacceptable bit error rates respectively designated as passed or failed.

A detector for determining which interface protocol is in use by a serialiser/deserialiser, and comprising detecting channels composed of clocked delays and bit comparators for detecting the presence of idle signals coded according to either ten-bit or five-bit protocols using either one or two clocks.

The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.

The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments. This flexibility may be achieved by incorporating a programmable processor in the structured ASIC and by defining interfaces and the use of an external FPGA in the present platform. The structured ASIC may include a complete ARM processor subsystem and a plurality of high speed SERDES ports. The processor subsystem may include a bus interface to the external FPGA, allowing custom gate development and test in the FPGA, prior to incorporating it into the customer product. Through the SERDES ports, the test block may be used to show the electrical characteristics of the SERDES IP. In addition, some SERDES ports may be driven from a link layer realized in the FPGA. This may allow the same chip and board to implement SATA (serial advanced technology attachment), GigE, XAUI, XGXS, Fibre Channel, and the like by changing the programming of the FPGA on the board.

A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.

The present invention relates to a system for switching variable-length data packets of a heterogeneous network and a method for the same; and, more particularly, to a switching of variable-length data packets of a heterogeneous network through a serial communication between switching chips to switch the packets with a switching interface module having a network value representing a type of a specific network and a port number of a port which is connected to itself. The present invention has a technical characteristic in comprising a system for data switching variable-length packets of heterogeneous network, comprising: at least two switching interface modules connected to at least two networks respectively to transceive packets; a switching chip for receiving the packets from a first switching interface module among said at least two switching interface modules and for switching the received packets to a second switching interface module among said at least two switching interface modules; a SERDES (serialization and deserialization) channel for transmitting the packets between the switching interface module and the switching chip; and a signaling channel for transmitting a port number between the switching interface module and the switching chip.

Techniques for dynamically measuring and monitoring error rate in Serializer/Deserializer (SerDes) links In one set of embodiments, a method includes polling a SerDes link status of a SerDes link at a predetermined rate. The method also includes storing a predetermined polling results in a memory, determining a number of polling results indicating one or more errors occurred in said SerDes link, determining an action to be taken if said number of polling results exceed a threshold.

A reconfigurable ADD/DROP multiplexer/demultiplexer apparatus is implemented by connecting a multiplexer/demultiplexer apparatus to a serializer/deserializer (SERDES) apparatus having a loop-back capability. By selectively activating the loop-back functionality of the SERDES apparatus the combination can be made to function as a reconfigurable ADD/DROP multiplexer/demultiplexer apparatus.

A hardware platform system of a GPON ONU system based on FPGA design comprises a physical medium correlational layer, a GTC layer, a management control plane interface, a user plane interface and a power management module, wherein, the physical medium correlational layer comprises a GPON ONU transceiver and a SERDES chip which meet the ITU-T G.984.2B+ standard; the GTC layer comprises an FPGA, an SDRAM, an AS set chip, a first connector and a second connector; the management control plane interface comprises a third connector; the user plane interface circuit comprises an Ethernet control ship and an RJ45 with a network isolator; and the power management circuit comprises a 12V converting 3.3V first power chip, a 3.3V converting 2.5V second power chip and a 3.3V converting 1.2V third power chip. The method can effectively reduce the cost of GPON user end equipment, and has high applicability.