494 results about "SerDes" patented technology

The invention discloses a computing node, a computing system, a control method, a control device, equipment and a medium, and relates to the technical field of computers, a plurality of acceleration cards are interconnected through an Ethernet switching module, and low-order channels of serializer / deserializer interfaces of the acceleration cards are connected with the Ethernet switching module through retimers. A high-order channel of at least one serializer / deserializer interface of each accelerator card is connected with the Ethernet switching module through a retimer, and the working mode of the retimer is configured through a first controller on a computing node according to the signal rate of the accelerator cards, so that a framework that communication interfaces between the accelerator cards are fully interconnected is realized. Any two acceleration cards can be directly connected, the communication bandwidth between the acceleration cards is improved, meanwhile, the number of the acceleration cards can be flexibly expanded, longitudinal expansion and transverse expansion of a computing system can be conveniently achieved, the problem that a traditional acceleration card interconnection scheme is not easy to expand is solved, and the method can adapt to service requirements and flexibly adjust working loads.

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale + MPSoCs, and belongs to the technical field of data processing.The method comprises the steps that nanosecond-level synchronous pulses are generated through a PL end of Zynq, initial multi-modal data are collected, the transmission rate and integrity are analyzed through a double-SERDES controller of the PL end, and a dynamic data processing matrix is constructed; pL and PS end data flow distribution is simulated and optimized through a preset multi-data granularity scale, and an exchange instruction set is generated; in combination with an on-chip bus topology, a first data exchange path is formed through DMA-OCM interaction and hardware accelerator adaptation, and a second data exchange path is obtained by adjusting sub-channel allocation and bus priority; and the operation state parameters of the second data exchange path are written back to the data frame state attribute bar corresponding to the dynamic data processing matrix in real time, so that efficient processing and dynamic optimization of the multi-modal data are realized, and the system stability and the transmission efficiency are improved.

The invention particularly relates to a noise suppression test method and device for a vehicle-mounted chip, electronic equipment and a medium, and the method comprises the steps: correspondingly generating a noise waveform and a to-be-tested noise signal based on each piece of noise information of a vehicle, simulating a real noise signal of the vehicle based on the to-be-tested noise signal, and obtaining a target noise signal, the target noise signal is injected into the vehicle-mounted chip data link, the error code state of the vehicle-mounted chip data link is recognized, if no error code exists in the vehicle-mounted chip data link, the resistance value of the digital potentiometer is adjusted, the initial resistance value of the digital potentiometer is reset, and the step of injecting the target noise signal into the vehicle-mounted chip data link through the noise injection module continues to be executed; and generating a noise suppression test result of the vehicle-mounted chip until error codes exist in the data link of the vehicle-mounted chip. Therefore, the problem that the inhibition capability of the SerDes chip in the ultimate noise environment cannot be accurately evaluated due to the fact that complex noise interference in a real vehicle-mounted environment cannot be comprehensively simulated is solved.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.

The invention relates to the field of photoelectric hybrid computing, and discloses an inter-chip data transmission processing method based on a photoelectric hybrid architecture, which comprises the following steps of: converting an electric signal into an optical signal through a high-speed SerDes interface by virtue of cooperative work of an electric chip and an optical chip, and performing high-speed data processing and computing by utilizing an optical device in the optical chip, the processed optical signal is converted into an electric signal through a photoelectric converter, and the electric signal is returned to an electric chip for subsequent calculation; through the photoelectric hybrid architecture, the electric chip focuses on complex calculation tasks, and the optical chip is responsible for high-speed data transmission and primary processing, so that the data transmission efficiency and the calculation performance are remarkably improved, and the power consumption of the system is reduced. The method can effectively improve the performance in a large-scale parallel computing task, has lower energy consumption and higher transmission efficiency, and is particularly suitable for the fields of high-performance computing, deep learning and the like.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.

The invention discloses a look-ahead sliding decision feedback equalizer and a Serdes receiver, and the look-ahead sliding decision feedback equalizer comprises a two-stage assembly line which is composed of an m-tap adder and an n-tap decision device based on a look-ahead structure. Each tap of the n-tap decision device comprises a three-decision device unit 3T-D, a four-decision device unit 4T-D and a five-decision device unit 5T-D, the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation, the five-decision device unit 5T-D comprises two one-out-of-four multiplexers 4-to-1 MUX used for performing look-ahead calculation, and the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation. And a judgment result output by the three-decision-device unit 3T-D is used as a selection signal to act on the four-decision-device unit 4T-D and the five-decision-device unit 5T-D. The invention aims to efficiently process data from the feed-forward equalizer and reduce the delay of a critical path in a decoding part of the sliding decision feedback equalizer.

The invention provides an SSD controller prototype verification method and device based on an FPGA, and the method comprises the steps: carrying out the module division of an RTL code of an SSD controller, and obtaining a plurality of RTL submodules; the method comprises the following steps: deploying a plurality of RTL sub-modules on a plurality of FPGAs (Field Programmable Gate Array) respectively, wherein the plurality of RTL sub-modules communicate with one another through physical connection among Serdes ports of the FPGAs; deploying corresponding preset test parameters and communication port logic according to the test scheme; and starting a system-level test to obtain a test result. According to the method, prototype verification of a large SSD controller chip can be supported, data interaction among multiple interconnected FPGAs is completed through a Serdes port, a user can select a synchronous / asynchronous data transmission scheme according to an actual verification background on the premise that the reliability and efficiency of data transmission are improved, and the data transmission efficiency is improved. The performance of the SSD controller chip in a real working scene is obtained through verification performance analysis, and on the basis of the advantages, the method can efficiently and accurately discover potential problems in the chip research and development process before chip tape-out, and the chip tape-out quality is improved.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

The invention discloses a calibration method for sampling time offset mismatch of TI-ADC for SerDes and a storage medium. The calibration method comprises the following steps: performing operation on a current output value obtained by quantization of each sub-ADC and a previous beat of data recovered by judgment of SerDes; taking a certain sub-ADC channel as a reference to obtain an error function of offset of sampling time of other sub-ADCs relative to the reference time; and the sampling time of the sub-ADCs is adjusted by adopting an LMS algorithm to minimize an error function, so that the calibration of the sampling time offset mismatch is completed. The storage medium is used for storing a computer program for executing the method. The method has the advantages of simple principle, simplicity and convenience in operation, wide application range, good calibration effect, high precision and the like.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

Systems and techniques for synchronizing serializer and deserializer digital reference clocks are described. An example method includes activating a phase locked loop (PLL) to generate an ADC / DAC reference signal, obtaining a DAC Enable (DAC_EN) signal, generating, based on the DAC_EN signal, a SET signal aligned with a phase of the ADC / DAC reference signal, generating, based on the ADC / DAC reference signal, a serializer digital reference clock for a serializer coupled to the DAC, and generating, based on the ADC / DAC reference signal and the SET signal, a deserializer digital reference clock for a deserializer coupled to the ADC. The serializer digital reference clock and the deserializer digital reference clock are each respectively generated by frequency division of the ADC / DAC reference signal. The serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

The invention relates to a digital pre-distortion high-precision phase interpolator with a constant input load. The digital pre-distortion high-precision phase interpolator comprises a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The two pre-filter circuits are used for converting the two full-swing square wave signals into two sine clocks; and the phase interpolation core circuit is used for carrying out nonlinear interpolation on the two paths of sine clocks according to the two paths of weight control codes by using a constant input load, and outputting a small-swing signal. According to the phase interpolator, the interpolation precision is greatly improved, digital pre-distortion of the interpolation weight can be realized by adjusting the control code decoder, the precision of the phase interpolator is further improved, a high-speed and high-precision output clock is realized, and the phase interpolator is suitable for clock generation modules such as a clock data recovery circuit and a phase-locked loop in a high-speed SerDes system.

The embodiment of the invention provides a GPU test device and a GPU test system comprising the same. The device comprises at least one first test chip and at least one first connector in communication connection with the first test chip, wherein the first connector comprises at least one first pin for transmitting a first to-be-tested signal; each first pin is in communication connection with a second pin on the substrate; the first to-be-tested signal comprises a to-be-tested SERDES signal; the second pin receives a to-be-tested SERDES signal sent by the first to-be-tested system, and sends the to-be-tested SERDES signal to the first test chip through the first pin; the first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested; wherein the first to-be-tested system determines the connectivity of the SERDES link between the first to-be-tested system and the GPU based on the first feedback signal, so that the GPU testing device can be used for testing the connectivity of the SERDES link between the first to-be-tested system and the GPU.

The invention provides a serdes chip performance control parameter optimization method and device, and the method comprises the steps: setting the value ranges of all configuration parameters of a preset configuration type in a serdes chip, and generating an initial particle swarm according to each configuration parameter and the corresponding value range; inputting the initial particle swarm as an input particle swarm into a first round of iteration; each round of iteration comprises the steps of inputting each particle in the input particle swarm into a corresponding serdes chip, obtaining an eye diagram corresponding to each particle, and obtaining a target value corresponding to each particle according to the eye diagram corresponding to each particle; obtaining the maximum target value in all particles in the input particle swarm as a local optimal value, and obtaining the local optimal value with the maximum target value in all current iteration rounds as a global optimal value; and after the termination condition is met, the optimal configuration parameter of the serdes chip is obtained, so that the optimization efficiency and the channel compensation performance are improved.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

The invention discloses a port lighting method and system, a mainboard, a storage medium and electronic equipment, and belongs to the field of network equipment communication, and the method comprises the steps that a CPU of the mainboard carries out port lighting according to the number of serializer / deserializer SerDes interfaces provided for each daughter card slot position and the preset lighting sequence of each daughter card slot position; determining the number and the position of the lighting signal of each sub-card slot position in the whole section of lighting signal code stream; the CPU of the mainboard configures the lighting signal type of each daughter card slot position according to the number of the ports of the daughter cards, and outputs the whole section of lighting signal code stream to a programmable logic device of the mainboard through a switching chip; a programmable logic device of the mainboard intercepts the lighting signals of the sub-card slot positions from the whole section of lighting signal code stream according to the determined number and position, and distributes the lighting signals to the sub-card slot positions; and the programmable logic device of the corresponding daughter card in each daughter card slot receives the lighting signal, analyzes the lighting signal and sends the lighting signal to each port LED lamp for lighting. According to the method and the device, the problem of abnormal port lighting caused by change of the number of ports of the daughter card in a hardware lighting scheme is solved on equipment supporting hot plugging of the daughter card, meanwhile, the occupied CPU resource is low, and the real-time performance is high.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

The invention discloses a continuous high-precision pulse width measurement method and system based on a high-speed serdes, and relates to the technical field of electronic measurement, and the method comprises the steps: S1, transmitting a matching calibration signal; s2, a calibration signal is selected and copied; s3, setting an initial delay value; s4, receiving the data and performing template comparison to complete initial calibration; s5, setting phase offsets of a plurality of links; s6, carrying out delay adjustment on the link; s7, carrying out precise delay calibration on link data; s8, analyzing the measurement precision; s9, selecting and copying a tested signal; s10, carrying out parallel interleaving sampling to output sampling data; s11, calculating a pulse width value; s12, calculating a compensated pulse width value according to the compensation coefficient; through the method, the time resolution is less than or equal to 10ps, and the maximum throughput rate is greater than 300M event / s; channel expansion is supported, and the interleaving sampling rate is improved; and a time delay chip with higher resolution can be used as a time delay adjusting module, so that the performance is improved.

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

A memory device includes a plurality of mode registers storing a plurality of status codes; a data input / output circuit that receives one status code of the plurality of status codes from one of the plurality of mode registers and samples the one status code to generate sampled data and transmit the sampled data to the serializer; and a serializer that receives the sampled data from the data input / output circuit, converts the sampled data into serial data, and outputs the serial data through a first connection terminal separate from a data connection terminal configured to exchange access data.