626 results about "SerDes" patented technology

The invention discloses a computing node, a computing system, a control method, a control device, equipment and a medium, and relates to the technical field of computers, a plurality of acceleration cards are interconnected through an Ethernet switching module, and low-order channels of serializer / deserializer interfaces of the acceleration cards are connected with the Ethernet switching module through retimers. A high-order channel of at least one serializer / deserializer interface of each accelerator card is connected with the Ethernet switching module through a retimer, and the working mode of the retimer is configured through a first controller on a computing node according to the signal rate of the accelerator cards, so that a framework that communication interfaces between the accelerator cards are fully interconnected is realized. Any two acceleration cards can be directly connected, the communication bandwidth between the acceleration cards is improved, meanwhile, the number of the acceleration cards can be flexibly expanded, longitudinal expansion and transverse expansion of a computing system can be conveniently achieved, the problem that a traditional acceleration card interconnection scheme is not easy to expand is solved, and the method can adapt to service requirements and flexibly adjust working loads.

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

The invention relates to a quarter-rate architecture SerDes clock path and a serialization circuit. The quarter-rate architecture SerDes clock path comprises a PLL (Phase Locked Loop) used for generating a differential clock signal consisting of two signals with opposite phases; the four-phase clock signal generation module is used for generating four four-phase clock signals with the phase difference of 90 degrees in sequence according to the differential clock signal; the retiming module is used for performing delay processing on the input four-way parallel data according to the four-phase clock signal, so that the delay interval among the input four-way parallel data is 1UI; the 1UI PULSE generation module is used for synthesizing clock signals of two adjacent phases in four-phase clock signals of which the phase difference is 90 degrees in sequence into clock signals with 1UI pulse width; and 4, the 1MUX module is used for synthesizing the four paths of delayed parallel data into one path of serial data according to the clock signal of the 1UI pulse width synthesized by the 1UI PULSE generation module.

An MIPI serializer / deserializer supporting photoelectric dual modes and an MIPI transmission system comprise a high-speed processing circuit, a low-speed processing circuit, forward and reverse packaging circuits, forward and reverse unpackaging circuits and a photoelectric configuration module which respectively comprise a sending unit and a receiving unit, and the sending unit and the receiving unit comprise an electrical path and / or an optical path. High-speed signals and low-speed signals in an MIPI mode are supported to be serially or deserialized together, the data transmission interface comprises an electric channel and an optical channel, data can be independently supported to be transmitted at the same time through any one or two of the electric channel and the optical channel, and therefore long-distance scenes and short-distance scenes can be supported at the same time.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

The invention relates to the technical field of serial deserializer design, and discloses an FPGA-based direct-current balanced digital audio and video signal serial deserializer, which comprises a serializer, a deserializer, a control configuration module, a power management module, a configuration storage module and a time sequence control module, the serializer is used for converting parallel digital audio and video data into high-speed serial data streams; the deserializer is used for detecting and repairing abnormal data in the high-speed serial data stream by using a machine learning technology, and converting the repaired high-speed serial data stream back to parallel digital audio and video data; the control configuration module is used for configuring working parameters of the serializer and the deserializer through an external interface; the time sequence control module is used for managing the time sequence relation in the system and ensuring synchronization of data flow between different modules. According to the method, the defects of a traditional deserializer in the aspects of anomaly detection and repair, signal quality evaluation and parameter optimization are overcome, and the stability and quality of high-resolution digital audio and video data transmission are improved.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale + MPSoCs, and belongs to the technical field of data processing.The method comprises the steps that nanosecond-level synchronous pulses are generated through a PL end of Zynq, initial multi-modal data are collected, the transmission rate and integrity are analyzed through a double-SERDES controller of the PL end, and a dynamic data processing matrix is constructed; pL and PS end data flow distribution is simulated and optimized through a preset multi-data granularity scale, and an exchange instruction set is generated; in combination with an on-chip bus topology, a first data exchange path is formed through DMA-OCM interaction and hardware accelerator adaptation, and a second data exchange path is obtained by adjusting sub-channel allocation and bus priority; and the operation state parameters of the second data exchange path are written back to the data frame state attribute bar corresponding to the dynamic data processing matrix in real time, so that efficient processing and dynamic optimization of the multi-modal data are realized, and the system stability and the transmission efficiency are improved.

The invention particularly relates to a noise suppression test method and device for a vehicle-mounted chip, electronic equipment and a medium, and the method comprises the steps: correspondingly generating a noise waveform and a to-be-tested noise signal based on each piece of noise information of a vehicle, simulating a real noise signal of the vehicle based on the to-be-tested noise signal, and obtaining a target noise signal, the target noise signal is injected into the vehicle-mounted chip data link, the error code state of the vehicle-mounted chip data link is recognized, if no error code exists in the vehicle-mounted chip data link, the resistance value of the digital potentiometer is adjusted, the initial resistance value of the digital potentiometer is reset, and the step of injecting the target noise signal into the vehicle-mounted chip data link through the noise injection module continues to be executed; and generating a noise suppression test result of the vehicle-mounted chip until error codes exist in the data link of the vehicle-mounted chip. Therefore, the problem that the inhibition capability of the SerDes chip in the ultimate noise environment cannot be accurately evaluated due to the fact that complex noise interference in a real vehicle-mounted environment cannot be comprehensively simulated is solved.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.

The invention relates to the field of photoelectric hybrid computing, and discloses an inter-chip data transmission processing method based on a photoelectric hybrid architecture, which comprises the following steps of: converting an electric signal into an optical signal through a high-speed SerDes interface by virtue of cooperative work of an electric chip and an optical chip, and performing high-speed data processing and computing by utilizing an optical device in the optical chip, the processed optical signal is converted into an electric signal through a photoelectric converter, and the electric signal is returned to an electric chip for subsequent calculation; through the photoelectric hybrid architecture, the electric chip focuses on complex calculation tasks, and the optical chip is responsible for high-speed data transmission and primary processing, so that the data transmission efficiency and the calculation performance are remarkably improved, and the power consumption of the system is reduced. The method can effectively improve the performance in a large-scale parallel computing task, has lower energy consumption and higher transmission efficiency, and is particularly suitable for the fields of high-performance computing, deep learning and the like.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.

The invention discloses a look-ahead sliding decision feedback equalizer and a Serdes receiver, and the look-ahead sliding decision feedback equalizer comprises a two-stage assembly line which is composed of an m-tap adder and an n-tap decision device based on a look-ahead structure. Each tap of the n-tap decision device comprises a three-decision device unit 3T-D, a four-decision device unit 4T-D and a five-decision device unit 5T-D, the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation, the five-decision device unit 5T-D comprises two one-out-of-four multiplexers 4-to-1 MUX used for performing look-ahead calculation, and the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation. And a judgment result output by the three-decision-device unit 3T-D is used as a selection signal to act on the four-decision-device unit 4T-D and the five-decision-device unit 5T-D. The invention aims to efficiently process data from the feed-forward equalizer and reduce the delay of a critical path in a decoding part of the sliding decision feedback equalizer.

The invention provides an SSD controller prototype verification method and device based on an FPGA, and the method comprises the steps: carrying out the module division of an RTL code of an SSD controller, and obtaining a plurality of RTL submodules; the method comprises the following steps: deploying a plurality of RTL sub-modules on a plurality of FPGAs (Field Programmable Gate Array) respectively, wherein the plurality of RTL sub-modules communicate with one another through physical connection among Serdes ports of the FPGAs; deploying corresponding preset test parameters and communication port logic according to the test scheme; and starting a system-level test to obtain a test result. According to the method, prototype verification of a large SSD controller chip can be supported, data interaction among multiple interconnected FPGAs is completed through a Serdes port, a user can select a synchronous / asynchronous data transmission scheme according to an actual verification background on the premise that the reliability and efficiency of data transmission are improved, and the data transmission efficiency is improved. The performance of the SSD controller chip in a real working scene is obtained through verification performance analysis, and on the basis of the advantages, the method can efficiently and accurately discover potential problems in the chip research and development process before chip tape-out, and the chip tape-out quality is improved.

A method, a detection circuit and an electronic device for detecting timing sequence of serializer are provided. The method for detecting a timing sequence of a serializer includes: sampling serial data to obtain first sampled serial data and second sampled serial data, wherein the serial data is obtained by parallel-serial conversion of parallel data used for detection by the serializer, and the first sampled serial data and the second sampled serial data respectively include values corresponding to different data bits of the serial data; performing logical operation between on the first sampled serial data and the second sampled serial data to obtain a first result signal; and performing timing sequence detection on the first result signal, wherein the timing sequence detection is used for detecting whether the timing sequence correctness of the serializer is correct.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

The invention discloses a calibration method for sampling time offset mismatch of TI-ADC for SerDes and a storage medium. The calibration method comprises the following steps: performing operation on a current output value obtained by quantization of each sub-ADC and a previous beat of data recovered by judgment of SerDes; taking a certain sub-ADC channel as a reference to obtain an error function of offset of sampling time of other sub-ADCs relative to the reference time; and the sampling time of the sub-ADCs is adjusted by adopting an LMS algorithm to minimize an error function, so that the calibration of the sampling time offset mismatch is completed. The storage medium is used for storing a computer program for executing the method. The method has the advantages of simple principle, simplicity and convenience in operation, wide application range, good calibration effect, high precision and the like.

The embodiment of the invention provides a clock calibration circuit. The circuit comprises a first sampling circuit; the second sampling circuit is connected with the first sampling circuit in series; the first sampling circuit comprises a phase-locked loop (PLL); a first duty cycle calibrator DCC connected in series with the PLL; a first phase interpolator PI connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmission driver connected in series with the first data serializer; the first data serializer is connected with the first DCC in series, the second data serializer is connected with the first DCC in series, the second sending driver is connected with the second data serializer in series, and the PLL is used for outputting a clock signal so as to drive the first data serializer to send data to be sent to the first sending driver and drive the second data serializer to send a feedforward clock signal to the second sending driver; and the second sending driver is used for sending the feed-forward clock signal to the first receiving driver of the second sampling circuit so as to determine the feed-forward clock signal as a sampling clock of the second sampling circuit.

Various examples of the present disclosure relate to a transmitter apparatus, device, method, and computer program, to a receiver apparatus, device, method, and computer program, and to corresponding source and destination devices and communication devices. The transmitter apparatus comprises a plurality of ports for data to be transmitted to a destination device, with each port being associated with a transmission data rate. The transmitter apparatus comprises processing circuitry configured to obtain data to be transmitted to the destination device via the plurality of ports. The processing circuitry is configured to multiplex the data to be transmitted to the destination device according to a weighted round-robin scheme to generate a multiplexed data stream. The weights of the weighted round-robin scheme are based on the transmission data rate of the respective port the data is obtained over. The processing circuitry is configured to transmit the multiplexed data stream to the destination device.

The present invention discloses a clock data recovery circuit and recovery method suitable for high-speed SerDes, including: an analog front end, inputting a received signal and outputting a phase detector result; a phase detector accumulator, used to accumulate the phase detector result; a gain control unit, used to adjust the gain of the trunk signal; a first branch, including a ratio decision device and a phase gain unit; a second branch, including a weight decision device and a frequency integration unit; an adder, used to add the output results of the phase gain unit and the frequency integration unit, and the adder output passes through a phase accumulator and a phase interpolator in turn; the phase interpolator is used to output a sampling clock for use by the analog front end. The present invention can respond in time under small error conditions, with fast CDR locking speed and short time; reduce the cumulative error of the system, strengthen the tracking effect of clock jitter, and ensure the overall performance improvement of the system.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

Systems and techniques for synchronizing serializer and deserializer digital reference clocks are described. An example method includes activating a phase locked loop (PLL) to generate an ADC / DAC reference signal, obtaining a DAC Enable (DAC_EN) signal, generating, based on the DAC_EN signal, a SET signal aligned with a phase of the ADC / DAC reference signal, generating, based on the ADC / DAC reference signal, a serializer digital reference clock for a serializer coupled to the DAC, and generating, based on the ADC / DAC reference signal and the SET signal, a deserializer digital reference clock for a deserializer coupled to the ADC. The serializer digital reference clock and the deserializer digital reference clock are each respectively generated by frequency division of the ADC / DAC reference signal. The serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.

Various example embodiments herein provide methods, circuits, and systems, for controlling a multicycle path in a serializer interface. The method includes determining a desired delay window of a multicycle data path in a serializer interface by sampling at least one step response from serializer delay replica circuitry at an edge of a first clock signal and a gating signal, in response to synchronizing a second clock signal with a negative edge of the first clock signal, configuring a polarity of a latch in a subsequent serializer of a serializer chain based on the determined desired delay window, and controlling the multicycle data path in the serializer interface based on the configured polarity of the latch in the subsequent serializer of the serializer chain.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

The invention relates to a digital pre-distortion high-precision phase interpolator with a constant input load. The digital pre-distortion high-precision phase interpolator comprises a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The two pre-filter circuits are used for converting the two full-swing square wave signals into two sine clocks; and the phase interpolation core circuit is used for carrying out nonlinear interpolation on the two paths of sine clocks according to the two paths of weight control codes by using a constant input load, and outputting a small-swing signal. According to the phase interpolator, the interpolation precision is greatly improved, digital pre-distortion of the interpolation weight can be realized by adjusting the control code decoder, the precision of the phase interpolator is further improved, a high-speed and high-precision output clock is realized, and the phase interpolator is suitable for clock generation modules such as a clock data recovery circuit and a phase-locked loop in a high-speed SerDes system.

The embodiment of the invention provides a GPU test device and a GPU test system comprising the same. The device comprises at least one first test chip and at least one first connector in communication connection with the first test chip, wherein the first connector comprises at least one first pin for transmitting a first to-be-tested signal; each first pin is in communication connection with a second pin on the substrate; the first to-be-tested signal comprises a to-be-tested SERDES signal; the second pin receives a to-be-tested SERDES signal sent by the first to-be-tested system, and sends the to-be-tested SERDES signal to the first test chip through the first pin; the first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested; wherein the first to-be-tested system determines the connectivity of the SERDES link between the first to-be-tested system and the GPU based on the first feedback signal, so that the GPU testing device can be used for testing the connectivity of the SERDES link between the first to-be-tested system and the GPU.