234 results about "SerDes" patented technology

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale + MPSoCs, and belongs to the technical field of data processing.The method comprises the steps that nanosecond-level synchronous pulses are generated through a PL end of Zynq, initial multi-modal data are collected, the transmission rate and integrity are analyzed through a double-SERDES controller of the PL end, and a dynamic data processing matrix is constructed; pL and PS end data flow distribution is simulated and optimized through a preset multi-data granularity scale, and an exchange instruction set is generated; in combination with an on-chip bus topology, a first data exchange path is formed through DMA-OCM interaction and hardware accelerator adaptation, and a second data exchange path is obtained by adjusting sub-channel allocation and bus priority; and the operation state parameters of the second data exchange path are written back to the data frame state attribute bar corresponding to the dynamic data processing matrix in real time, so that efficient processing and dynamic optimization of the multi-modal data are realized, and the system stability and the transmission efficiency are improved.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

A memory device includes a plurality of mode registers storing a plurality of status codes; a data input / output circuit that receives one status code of the plurality of status codes from one of the plurality of mode registers and samples the one status code to generate sampled data and transmit the sampled data to the serializer; and a serializer that receives the sampled data from the data input / output circuit, converts the sampled data into serial data, and outputs the serial data through a first connection terminal separate from a data connection terminal configured to exchange access data.

The invention discloses a double-flow image transmission system and method based on a high-speed SerDes interface, and belongs to the technical field of high-speed image transmission, the system comprises a sending end and a receiving end, an image source A and an image source B of the sending end do not need DDR cache synchronization, and image frames are segmented, interleaved and packaged through a dynamic time slice distribution mechanism and then sent to a single high-speed SerDes channel; and a receiving end collects data and then de-interleaves and recombines the recovered image. The data encapsulation comprises a frame synchronization head, a block synchronization head and the like for identification, the dynamic time slice distribution mechanism alternately or independently sends image blocks according to the image preparation condition, and the image adopts a double-cache mechanism to avoid data coverage. The method improves the channel bandwidth utilization rate, saves hardware resources, is good in compatibility, supports various data stream combinations, reduces frame delay, and is suitable for single-channel multi-stream and multi-channel multi-stream transmission.

The invention relates to the technical field of high-speed serial communication, and discloses a SerDes link initialization method and device, and the method comprises the steps: firstly evaluating the operation states of a plurality of SerDes channels, and marking a corresponding health level for each channel; then, aiming at the channel with the health level reaching the standard, synchronously starting a single-channel alignment attempt and a multi-channel alignment attempt so as to obtain a channel with symbol alignment completed; and finally, according to the method, determining a grouping binding strategy for the successfully aligned channels according to the historical initialization data, and executing a binding operation. According to the method, the speed and adaptability of SerDes link initialization are improved by evaluating the health condition of the channel, parallelizing the alignment process and performing intelligent grouping by using historical data.

The invention provides a vehicle-gauge-level dynamic equalization SerDes system and a working method, and belongs to the technical field of high-speed serial communication, and the method is characterized in that the system comprises an environment feedback module which collects temperature, cable impedance and common-mode noise data in real time; the dynamic equalizer is used for adjusting parameters of the pre-emphasis, the continuous time linear equalizer and the decision feedback equalizer based on the data acquired by the environment feedback module; the link health monitoring unit is used for counting the bit error rate through a hardware counter and triggering a self-repairing process; and the repair controller is used for executing a self-repair process which comprises redundant channel switching, transmission rate degradation and link retraining operation. According to the invention, the hardware-level environment adaptive equalization and millisecond-level self-healing capability of the SerDes link can be realized, and meanwhile, the redundancy design cost is reduced.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

The invention relates to the technical field of SerDes chip development and verification, and particularly discloses an SerDes chip evaluation and verification device and system, and the device comprises a preprocessing module which carries out the preprocessing of a transmission electric signal transmitted by a to-be-tested SerDes chip, obtains a processed transmission electric signal, and carries out the preprocessing of a receiving electric signal, and obtains a processed receiving electric signal; the sending electric signal verification module performs electro-optical conversion on the processed sending electric signal to obtain a sending electric signal performance verification result of the SerDes chip to be tested; and the receiving electric signal verification module performs photoelectric conversion on the preset optical signal to obtain a receiving electric signal performance verification result of the SerDes chip to be tested, and performs photoelectric conversion on the optical signal to be tested to obtain an outer loopback performance verification result of the SerDes chip to be tested. According to the evaluation and verification device for the SerDes chip provided by the invention, the interference of external factors during verification of the electrical signal performance of the SerDes chip is effectively avoided.

Systems, apparatuses, and methods for automatic firmware provision of high speed serializer / deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

There is provided a serializer (3) configured to receive an input feature map represented by a Q-dimensional tensor and to convert the received input feature map into a series of 1D vectors, each corresponding to a convolutional patch. The serializer comprises a memory device (300) comprising a plurality of ports and of memory banks adapted to store data words, the ports comprising a least a write port and at least two read ports. The serializer (3) is adapted to perform write operations consisting in writing a number of 1D vectors to a number of banks of said memory device (300) using the writing port, while being adapted for reading in parallel convolutional patches corresponding to stored 1D vectors from banks of the memory device (300) using the at least two reading ports, the extracted convolutional patches being fed to a convolutional filtering device (90) implementing convolutional filters.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

The invention provides a cluster system comprising a computing unit and a switching unit and a task processing method and device, and relates to the technical field of computers. The cluster system comprises N computing platforms, and each computing platform comprises a switching unit, a computing unit, a power supply unit, a monitoring management unit and a controller. The computing unit comprises at least one of a PC, a CPU, a GPU and a neural network computing module; the switching unit comprises a first type switching module which is used for connecting a hardware or software interface of a network, is responsible for sending, receiving and processing data, and comprises but is not limited to a gigabit Ethernet interface; the second type of switching module provides support for high-speed serial data transmission, adopts high-speed data interfaces, and comprises but is not limited to a Serdes interface and an LVDS (Low Voltage Differential Signaling) interface; the third type of switching module is a high-bandwidth and low-delay data interface which comprises but is not limited to an MCIO interface and a PCIe interface; and the fourth type of switching module is a high-bandwidth and high-density data transmission interface which comprises but is not limited to a QSFP interface and an OSFP interface.

A semiconductor package includes a plurality of stacked memory core dies connected to first data lines, a logic die including a processor connected to second data lines, and a buffer die stacked between the plurality of memory core dies and the logic die and including a data line reconfiguration circuit connected to the first data lines and the second data lines. The data line reconfiguration circuit includes at least one of a multiplexer circuit, a serializer / deserializer circuit, or a compressor.

This invention relates to a high-precision digital predistortion phase interpolator with a constant input load, comprising: a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit, and a control code decoder circuit. The two pre-filter circuits convert two full-swing square wave signals into two sinusoidal clocks. The phase interpolation core circuit performs nonlinear interpolation on the two sinusoidal clocks with a constant input load based on two weighted control codes, outputting a small-swing signal. This phase interpolator significantly improves interpolation accuracy. Digital predistortion of the interpolation weights can be achieved by adjusting the control code decoder, further enhancing the accuracy of the phase interpolator and enabling high-speed, high-precision output clocks. It is suitable for clock data recovery circuits and phase-locked loops in high-speed SerDes systems.

The utility model discloses an RVC camera module and a dynamic vehicle auxiliary line system. The RVC camera module comprises a lens, a sensor, a graphic signal processor ISP, a serializer Serdes, a POC circuit module, a connector and a power management chip PMIC (Power Management Integrated Circuit), the lens is in signal connection with the sensor; the sensor is in signal connection with the image signal processor ISP; the image signal processor ISP is in signal connection with the serializer Serdes; the serializer Serdes is in signal connection with the POC circuit module and the connector respectively; the POC circuit is in signal connection with the power management PMIC; the power management PMIC supplies power to the sensor, the image signal processor ISP and the serializer Serdes respectively. According to the utility model, the dynamic vehicle auxiliary line can be generated in the camera, so that the overall equipment cost of the reversing image system is reduced.

A terminal including a transceiver, an analog-to-digital converter and control circuitry. The transceiver receives a stream of bursts from a plurality of units. One of the units is an electronic device. The analog-to-digital converter receives an upstream burst from the transceiver during an active time slot. The upstream burst is one of the bursts. In response to sampling the upstream burst at a sample rate, the analog-to-digital converter converts the upstream burst from an analog waveform into a sequence of digital values. In response to a coefficient for the electronic device being a default coefficient, the control circuitry stores the digital values into memory during the active time slot.

The application provides a 200GE service data transmission method, a chip and a communication system based on a 224G high-speed SerDes, and the method comprises the following steps: a PCS sending module performs PCS sending processing on upstream data obtained, to obtain first PCS data; the PCS sending module sends the first PCS data to a PMA sending module according to a first PCS clock rate and a first PCS data bit width; a rate improvement module determines first clock information according to a first PMA data bit width, a first PMA clock rate, the first PCS clock rate, the first PCS data bit width and a set bandwidth, to improve the first PCS clock rate; the PCS sending module sends the first PCS data according to the first PMA data bit width and the improved first PCS clock rate; and the PMA sending module processes the first PCS data and sends first serial data. The application can be applied to the field of internet access and related services, avoids the alignment mark insertion process to improve the sending rate of the PCS layer, and accelerates link convergence and improves link stability by introducing a PMA state frame.

The utility model discloses a decoding all-in-one machine based on a single CPU, and relates to the technical field of automobile display, and the decoding all-in-one machine comprises a video data receiving module, an MCU analysis module, an MIPICSIS conversion module, a CPU processing module, a DP data output module, a power management module, a storage module and a function interface module. The video data receiving module receives an original vehicle video signal and a vehicle-mounted auxiliary video signal, an original vehicle video picture is transmitted into the MIPICSIS conversion module through a deserializer, the MIPICSIS conversion module converts a digital video signal of a camera signal and the deserialized original vehicle video signal into a double-path data stream in an MIPICSIS format, the double-path data stream is input into the CPU, image processing and superposition are realized by the CPU, and the video data is transmitted to the video data receiving module through the video data receiving module. And the processed video signal is finally output through a DP interface double-path data stream, is processed by a serializer, and is sent to a display screen for picture output. 360-degree panorama output is added to the picture of the original vehicle, meanwhile, multi-series original vehicle screen refitting is supported, and the advantages of being low in cost, high in stability, capable of supporting a high-resolution display screen and the like are achieved.

A system and method for jitter injection is provided. The system may include a serializer-deserializer (SerDes) circuit. In some examples, the serializer-deserializer (SerDes) circuit have a pre-emphasis circuit and a post emphasis circuit. The system may also include a controller, which may be used to apply specific and varying amounts of pre-emphasis and post-emphasis. The system may also include a jitter injector. In some examples, the jitter injector may be used to inject jitter into the serializer-deserializer (SerDes) circuit based on the applied pre-emphasis and post-emphasis.

There is provided a system and a method for filtering out glitches in a SerDes transmitter. The SerDes transmitter includes a latency generation block, and a 2-to-1 serializer. The latency generation block is configured to synchronize a feed forward equalization (FFE) signal to a half rate domain by creating a latency in a FFE enable signal, and provide the synchronized FFE enable signal to a plurality of synchronized FFE selection multiplexers. The SerDes transmitter further includes a 2-to-1 serializer that is configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

A vertical line card (VLC) arrangement for networking modules is disclosed. The system includes a mainboard containing a high-speed ASIC and one or more outward cage structures, along with a centrally located daughterboard supporting one or more additional cages. This architecture significantly shortens high-speed SerDes traces, preserves front-to-back airflow, and sustains high port density. By mounting certain cages directly on the mainboard, extra insertion losses from interconnects are eliminated, while the centrally positioned daughterboard ensures only minimal additional signal degradation. Strategic cutouts and angled faceplates provide optimal thermal management. Overall, the solution avoids expensive flyover cables or multiple board-to-board connectors and accommodates busbar power delivery for high-current ASICs. This modular design offers flexibility in port counts, component placement, and power management, enabling robust signal integrity and enhanced heat dissipation for next-generation data center and telecom systems.

This invention discloses an in-vehicle video redundancy system. The system includes: an intelligent driving acquisition device for acquiring multiple video streams transmitted in parallel by a target vehicle under different vehicle states; an in-vehicle serializer for converting the parallel-transmitted multiple video streams into serial transmission; an in-vehicle dual-channel deserializer for converting the serially transmitted multiple video streams into target multiple video streams transmitted in parallel, and synchronously transmitting the target multiple video streams to an intelligent driving driving SOC chip and an intelligent driving parking SOC chip respectively; the intelligent driving driving SOC chip and the intelligent driving parking SOC chip are used to process the target multiple video streams according to the vehicle state of the target vehicle and the video stream type of the target multiple video streams, store the processed target multiple video streams, and display them on a display screen. This invention considers the redundancy design and safety backup control of the acquisition device, solving the problem of intelligent driving function loss due to the failure of one SOC, and ensuring the safety of the driver and passengers.

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

This application discloses a high-speed serializer with selectable bit width and a high-speed interface, belonging to the field of high-speed interface technology. The high-speed serializer includes: multiple shift registers and a tree-structured serializer for converting the data output from the multiple shift registers into serial data; the selection signals corresponding to the two-to-one selection modules in each shift register are independent; wherein each signal input terminal of the tree-structured serializer is connected to the signal output terminals of the multiple shift registers. When supporting parallel-to-serial conversion output with different bit widths, only the selection signals of the two-to-one selection modules of the shift registers need to be selected for output, eliminating the need for multiple sets of serializers, thus significantly reducing the hardware overhead required by the serializer. Furthermore, when implementing parallel-to-serial conversion with the same bit width, the number of D flip-flops in the phase-shift register can be reduced, thereby greatly reducing the power consumption required by the serializer.

A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer / deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.