398 results about "SerDes" patented technology

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale + MPSoCs, and belongs to the technical field of data processing.The method comprises the steps that nanosecond-level synchronous pulses are generated through a PL end of Zynq, initial multi-modal data are collected, the transmission rate and integrity are analyzed through a double-SERDES controller of the PL end, and a dynamic data processing matrix is constructed; pL and PS end data flow distribution is simulated and optimized through a preset multi-data granularity scale, and an exchange instruction set is generated; in combination with an on-chip bus topology, a first data exchange path is formed through DMA-OCM interaction and hardware accelerator adaptation, and a second data exchange path is obtained by adjusting sub-channel allocation and bus priority; and the operation state parameters of the second data exchange path are written back to the data frame state attribute bar corresponding to the dynamic data processing matrix in real time, so that efficient processing and dynamic optimization of the multi-modal data are realized, and the system stability and the transmission efficiency are improved.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

Systems and techniques for synchronizing serializer and deserializer digital reference clocks are described. An example method includes activating a phase locked loop (PLL) to generate an ADC / DAC reference signal, obtaining a DAC Enable (DAC_EN) signal, generating, based on the DAC_EN signal, a SET signal aligned with a phase of the ADC / DAC reference signal, generating, based on the ADC / DAC reference signal, a serializer digital reference clock for a serializer coupled to the DAC, and generating, based on the ADC / DAC reference signal and the SET signal, a deserializer digital reference clock for a deserializer coupled to the ADC. The serializer digital reference clock and the deserializer digital reference clock are each respectively generated by frequency division of the ADC / DAC reference signal. The serializer digital reference clock and the deserializer digital reference clock are synchronized to a known phase based on the SET signal.

The invention provides a serdes chip performance control parameter optimization method and device, and the method comprises the steps: setting the value ranges of all configuration parameters of a preset configuration type in a serdes chip, and generating an initial particle swarm according to each configuration parameter and the corresponding value range; inputting the initial particle swarm as an input particle swarm into a first round of iteration; each round of iteration comprises the steps of inputting each particle in the input particle swarm into a corresponding serdes chip, obtaining an eye diagram corresponding to each particle, and obtaining a target value corresponding to each particle according to the eye diagram corresponding to each particle; obtaining the maximum target value in all particles in the input particle swarm as a local optimal value, and obtaining the local optimal value with the maximum target value in all current iteration rounds as a global optimal value; and after the termination condition is met, the optimal configuration parameter of the serdes chip is obtained, so that the optimization efficiency and the channel compensation performance are improved.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

A memory device includes a plurality of mode registers storing a plurality of status codes; a data input / output circuit that receives one status code of the plurality of status codes from one of the plurality of mode registers and samples the one status code to generate sampled data and transmit the sampled data to the serializer; and a serializer that receives the sampled data from the data input / output circuit, converts the sampled data into serial data, and outputs the serial data through a first connection terminal separate from a data connection terminal configured to exchange access data.

The invention discloses an SERDES verification method and device, and the method comprises the steps: obtaining a protocol type and a configuration mode supported by a to-be-tested SERDES, generating a first compiling simulation script according to the protocol type, and enabling the script to comprise the clock frequency, the data rate, the parameter configuration of a coding mode, the generation rule of simulation excitation, and a result output path; based on the test requirement and the protocol type, a test top layer file and a file list are determined, and the file list comprises paths of the to-be-tested design file and the test excitation file; calling a script, executing first compiling simulation, and generating a waveform file and a log file; switching to a second protocol type, updating the test top layer file and the file list, and generating a second compiling simulation script; executing secondary compiling simulation to generate a waveform file and a log file corresponding to the second protocol; the log file is analyzed, the bit error rate, the function coverage rate and the time sequence violation are counted, and a comprehensive test report is generated. The method can accelerate the verification speed and reduce the development time.

The invention discloses a double-flow image transmission system and method based on a high-speed SerDes interface, and belongs to the technical field of high-speed image transmission, the system comprises a sending end and a receiving end, an image source A and an image source B of the sending end do not need DDR cache synchronization, and image frames are segmented, interleaved and packaged through a dynamic time slice distribution mechanism and then sent to a single high-speed SerDes channel; and a receiving end collects data and then de-interleaves and recombines the recovered image. The data encapsulation comprises a frame synchronization head, a block synchronization head and the like for identification, the dynamic time slice distribution mechanism alternately or independently sends image blocks according to the image preparation condition, and the image adopts a double-cache mechanism to avoid data coverage. The method improves the channel bandwidth utilization rate, saves hardware resources, is good in compatibility, supports various data stream combinations, reduces frame delay, and is suitable for single-channel multi-stream and multi-channel multi-stream transmission.

The invention relates to the technical field of high-speed serial communication, and discloses a SerDes link initialization method and device, and the method comprises the steps: firstly evaluating the operation states of a plurality of SerDes channels, and marking a corresponding health level for each channel; then, aiming at the channel with the health level reaching the standard, synchronously starting a single-channel alignment attempt and a multi-channel alignment attempt so as to obtain a channel with symbol alignment completed; and finally, according to the method, determining a grouping binding strategy for the successfully aligned channels according to the historical initialization data, and executing a binding operation. According to the method, the speed and adaptability of SerDes link initialization are improved by evaluating the health condition of the channel, parallelizing the alignment process and performing intelligent grouping by using historical data.

The invention discloses a digital system power distribution network impedance optimization method and system, and the method comprises the following steps: S1, obtaining the frequency-varying parasitic parameters Jg (f), Jr (f) and Jz (f) of a digital system power supply through a vector network analyzer, and enabling f to be a frequency variable; s2, calculating a dynamic matching coefficient DsC based on the frequency-varying parasitic parameter, and calling a PDN decoupling scheme set from a decoupling scheme database according to a DsC matching interval; s3, inputting the PDN decoupling scheme set into ADS software for segmented variable step size impedance simulation, wherein the step size of the frequency band from 1 MHz to 100 MHz is 0.5 MHz, and the step size of the frequency band from 100 MHz to 3 GHz is 5 MHz; and generating a surface-mounted PCB decoupling index DI containing a resonance penalty term and a micro-system substrate decoupling index WI. According to the method, the high-frequency resonance suppression capability is improved, frequency change parasitic parameter extraction is combined with resonance point penalty term design, impedance peak fluctuation is compressed to be within + / -8% of a target value in a 1-3GHz frequency band, and actually measured power supply noise of a 10Gbps SerDes interface is reduced by 62%.

The invention provides a vehicle-gauge-level dynamic equalization SerDes system and a working method, and belongs to the technical field of high-speed serial communication, and the method is characterized in that the system comprises an environment feedback module which collects temperature, cable impedance and common-mode noise data in real time; the dynamic equalizer is used for adjusting parameters of the pre-emphasis, the continuous time linear equalizer and the decision feedback equalizer based on the data acquired by the environment feedback module; the link health monitoring unit is used for counting the bit error rate through a hardware counter and triggering a self-repairing process; and the repair controller is used for executing a self-repair process which comprises redundant channel switching, transmission rate degradation and link retraining operation. According to the invention, the hardware-level environment adaptive equalization and millisecond-level self-healing capability of the SerDes link can be realized, and meanwhile, the redundancy design cost is reduced.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention relates to the technical field of pseudo-random binary sequence design, in particular to a parallel PRBS generation method and system for testing a multi-protocol high-speed serial transceiver, and the method comprises the steps: setting demand parameters of a pseudo-random binary sequence for testing the multi-protocol high-speed serial transceiver, and enabling the demand parameters to comprise an order, a bit number and a feedback polynomial; constructing a generator matrix for describing state transition of the linear feedback shift register according to the feedback polynomial; according to the bit number of the pseudo-random binary sequence, generating a mapping matrix of the pseudo-random binary sequence through the exponentiation of the generated matrix; based on the mapping matrix and the current beat linear feedback shift register state, outputting a pseudo-random binary sequence meeting the requirement parameters for testing the multi-protocol high-speed serial transceiver. According to the method, parallel generation of any PRBS can be supported, the PRBS parallel implementation logic configuration is simple, the hardware implementation complexity is low, the PRBS output throughput rate is high, and the design requirements of multi-protocol high-speed SerDes can be met.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

The invention relates to the technical field of SerDes chip development and verification, and particularly discloses an SerDes chip evaluation and verification device and system, and the device comprises a preprocessing module which carries out the preprocessing of a transmission electric signal transmitted by a to-be-tested SerDes chip, obtains a processed transmission electric signal, and carries out the preprocessing of a receiving electric signal, and obtains a processed receiving electric signal; the sending electric signal verification module performs electro-optical conversion on the processed sending electric signal to obtain a sending electric signal performance verification result of the SerDes chip to be tested; and the receiving electric signal verification module performs photoelectric conversion on the preset optical signal to obtain a receiving electric signal performance verification result of the SerDes chip to be tested, and performs photoelectric conversion on the optical signal to be tested to obtain an outer loopback performance verification result of the SerDes chip to be tested. According to the evaluation and verification device for the SerDes chip provided by the invention, the interference of external factors during verification of the electrical signal performance of the SerDes chip is effectively avoided.

Aspects of the present disclosure include a serializer, a method, and / or a non-transitory computer readable medium for receiving an indication indicating the sensor circuit is connected to a controller circuit, identifying a sensor identifier associated with the sensor circuit from an internal memory of the serializer, transmitting the sensor identifier from the serializer to the controller circuit to a deserializer to identify and load a sensor circuit driver associated with the sensor identifier, transmitting sensor calibration data from the memory circuit on the sensor circuit to the controller circuit, and transmitting sensor data to the deserializer.

Systems, apparatuses, and methods for automatic firmware provision of high speed serializer / deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

There is provided a serializer (3) configured to receive an input feature map represented by a Q-dimensional tensor and to convert the received input feature map into a series of 1D vectors, each corresponding to a convolutional patch. The serializer comprises a memory device (300) comprising a plurality of ports and of memory banks adapted to store data words, the ports comprising a least a write port and at least two read ports. The serializer (3) is adapted to perform write operations consisting in writing a number of 1D vectors to a number of banks of said memory device (300) using the writing port, while being adapted for reading in parallel convolutional patches corresponding to stored 1D vectors from banks of the memory device (300) using the at least two reading ports, the extracted convolutional patches being fed to a convolutional filtering device (90) implementing convolutional filters.