Clock data recovery and serial-parallel conversion circuit based on over sampling

A clock data recovery and conversion circuit technology, applied in electrical components, digital transmission systems, automatic power control, etc., can solve problems such as jitter performance degradation, phase boundary control unit offset, etc.

Inactive Publication Date: 2010-06-23
XIAN UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the existence of various negative factors, such as the offset of the phase boundary control unit, the clock replacement does not occur when the mixing weight is exactly 0
This would produce something like f

Method used

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  • Clock data recovery and serial-parallel conversion circuit based on over sampling
  • Clock data recovery and serial-parallel conversion circuit based on over sampling
  • Clock data recovery and serial-parallel conversion circuit based on over sampling

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Embodiment Construction

[0019] The technical solution and working principle adopted by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0020] A clock data recovery and serial-to-parallel conversion circuit based on oversampling for the receiving end of a high-speed serial transceiver, including a phase-locked loop module U0, a data space oversampling module U1, an edge detection and data recovery module U2, a Judgment module U3, a clock recovery module U4, a clock frequency division module U5 and a SerDes module U6;

[0021] Firstly, the interface signals of each module of the circuit are described. The circuit signal flow diagram of the present invention is as image 3 shown. The description of the input and output interfaces of the module is shown in Table 1; the description of the input and output interfaces of the data space oversampling module (U1) is shown in Table 2; the description of the input and output interfaces of the edge detect...

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Abstract

A clock data recovery and a serial-parallel conversion circuit based on over sampling for the receiver of a high speed serial transceiver comprise PLL module, a data space over sampling module, an edge detection and data recovery module, a judgment module, clock recovery module, a clock frequency-division module and a SerDes module. The data space over sampling module adopts the 16-phase equal-interval clock outputted by the PLL module to continuously sample the 24 bit data of 3 bytes, stores the sampled data in 16 groups of registers, and each group includes 24 registers. The corresponding bits of adjacent two groups of registers carry out OR operation to finish the edge detection, the detection results are added together in grouping mode, the fastest sampling clock corresponding to the group of data with the maximum distance value can be used as the recovery clock, the data sampled through the sampling clock can be used as recovery data, the sampling clock is performed with 8-fractional frequency to synchronize the bytes of the recovery data so as to finish the clock data recovery and serial-parallel conversion. The invention has clear structure, higher performance and reliable operation.

Description

technical field [0001] The present invention relates to a clock data recovery circuit of a high-speed transceiver, in particular to a clock data recovery and serial-to-parallel conversion circuit based on oversampling for a receiver in a high-speed serial transceiver, which belongs to the design technology of a communication-specific integrated circuit field. Background technique [0002] High-speed serial data transceivers are widely used in high-speed two-way data transmission systems, such as Gigabit Ethernet, optical fiber transmission networks, high-speed network routing and wireless base stations, etc., specifically between circuit boards, circuit boards and processors It provides a high-speed interface for communication between the processor and peripherals on the board, and between the chip and the backplane. The rapid development of telecommunication services and Internet services has further increased the demand for high-speed and high-performance transceiver chip...

Claims

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Application Information

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IPC IPC(8): H04L7/033H03L7/08
Inventor 邓军勇蒋林曾泽沧吕菱刘钊远张晋周晏
Owner XIAN UNIV OF POSTS & TELECOMM
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