1066results about "Synchronising arrangement" patented technology

The invention relates to the technical field of data recording, in particular to a data recording system for an automatic driving vehicle, and the system comprises a multi-source signal synchronization module, a behavior stage recognition module, a track abnormity elimination module, a dynamic compression adjustment module and a segmented index marking module. According to the method, a unified time alignment mechanism is constructed in a signal synchronization processing link, a strict corresponding relation between acquisition sequences is ensured, key time sequence characteristics of driving behavior switching are extracted by adopting a multi-behavior parameter comprehensive judgment method, segmented expression of a complex driving process is realized, and the accuracy of driving behavior switching is improved. According to track anomaly identification, through collaborative screening of inertial data and a positioning track, abnormal fragments which do not conform to physical rules are effectively eliminated, data compression dynamically sets interval length according to a parameter combined fluctuation trend, the fidelity of a key period is remarkably improved, non-key data redundancy is inhibited, and after a segmented index structure is established, the data compression efficiency is improved. And the data retrieval process is clearer.

The invention belongs to the technical field of power system measurement, and relates to a three-phase power parameter wireless synchronous measurement and vector analysis method and system, and the method comprises the following steps: generating and broadcasting a synchronous pulse code containing triggering phase information; generating a predicted phase angle; obtaining a comprehensive phase deviation value; performing dynamic feature separation processing on the comprehensive phase deviation value to generate a slowly-varying propagation delay feature and a transient prediction error feature; injecting the prediction error characteristics into a local phase predictor for calibration; acquiring phase voltage / current data based on the compensated sampling time, and calculating a fundamental wave effective value and a phase angle relative to a local calibration time reference; and packaging the fundamental wave effective value, the phase angle and the local timestamp into a simplified data packet and transmitting the simplified data packet to an analysis terminal. According to the method, the problems that in a traditional mode, satellite time service rejects signals in a substation indoor or underground scene, and synchronization interruption is easily caused by electromagnetic interference are solved.

The invention relates to the technical field of communication, and discloses a network communication chip signal interference suppression processing method. The method comprises the following steps: acquiring a local oscillator phase jitter sequence in real time through an on-chip phase noise monitoring unit; estimating Doppler frequency shift and channel coherence time based on the sequence; dynamically adjusting the closed-loop bandwidth of the phase-locked loop; and generating a phase compensation signal, and performing time-varying channel minimum mean square error equalization in combination with a received baseband signal to eliminate inter-symbol interference. The system integrates a phase noise monitoring function module, a channel parameter estimation function module, a phase-locked loop bandwidth regulation function module, a phase compensation generation function module and an interference joint elimination function module. By means of dynamic bandwidth reconstruction and high-precision phase compensation, the bit error rate under high-speed movement is remarkably reduced, the 5G millimeter wave communication standard requirement is met, and the method has the advantages of being achieved on a whole chip, low in delay and high in robustness.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

This application provides a clock recovery method, an apparatus, and a system, and may be applied to a destination device in an optical transport network. The method includes: obtaining first phase difference information, and generating target phase difference information based on the first phase difference information and accumulated phase difference information, where the target phase difference information is used to recover a clock of a first data frame. The first phase difference information is a sum of input phase difference information and a local phase difference. The input phase difference information is a sum of phase differences between one or more groups of two adjacent upstream devices in one or more upstream devices of a destination device through which the first data frame passes. A value of the target phase difference information is a first value, a second value, or 0. The accumulated phase difference information is an accumulation of differences between historical first phase difference information and historical target phase difference information that are present before a destination device obtains the first phase difference information. According to the clock recovery method provided in this application, accuracy of clock recovery of an OTN frame can be improved, to improve system reliability.

The invention relates to the technical field of digital demodulation, in particular to a digital demodulation method suitable for deep ultraviolet light communication, which comprises the following steps of: adopting multiple delay processing with half code element width, and respectively carrying out double extraction processing on a discrete sampling signal which is not subjected to delay processing and a plurality of delay sampling signals to obtain a plurality of delay extraction signals; in this way, the key sampling time in the coverage code element period can be ensured, and a basis is provided for subsequent accurate synchronization; a plurality of delay extraction signals are respectively input into corresponding equalization processing units, a preset local training sequence is loaded to each equalization processing unit to obtain a plurality of equalization filtering signals, and the plurality of equalization filtering signals and the preset local training sequence are respectively subjected to related judgment processing, so that the inter-symbol interference is inhibited, and meanwhile, the equalization processing efficiency is improved. The synchronization signal can be quickly screened out, so that the problem that inter-symbol interference and synchronization are difficult to consider in a traditional demodulation method is solved, and the demodulation efficiency and reliability are remarkably improved.

The in-vehicle device for receiving time synchronization information transmitted from each of a plurality of reference devices and transmitting the received time synchronization information to another device, includes: a communication unit configured to communicate with the other device; and an information processing unit configured to, if the communication unit receives a frame in which the time synchronization information is stored, store the time synchronization information in a specific queue with priority over other information, wherein the communication unit transmits the time synchronization information stored in the specific queue to the other device.

The invention relates to the technical field of video monitoring, and particularly discloses a video acquisition system and method based on time triggering, and the system comprises a high-precision clock source, a hardware triggering signal generation module, an image sensor, a timestamp precise acquisition module and a system main control module. The high-precision clock source provides a reference clock; the hardware trigger signal generation module generates a synchronous trigger pulse to drive the image sensor to expose; the timestamp accurate acquisition module directly captures an exposure completion signal output by the sensor and generates a corresponding high-precision original timestamp; and the system main control module fuses and packages the timestamp and the image data. The method is realized based on the system. According to the invention, the accuracy and stability of the triggering moment are ensured from the source, and the accurate correspondence between the timestamp and the physical exposure moment is realized.

The invention relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device and equipment and a medium, and the method comprises the steps: obtaining initial network time based on a network time protocol and a precise time protocol; recovering the synchronous clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate second-level reference time; the trigger pulse signal and the synchronous clock signal are used for executing high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; the analog-to-digital conversion unit is triggered at the effective jump edge of the sampling driving clock to sample and latch nanosecond-level fine time to generate a sampling timestamp, and the sampling timestamp is output in combination with sampling data. According to the method, time recovery, time refinement and sampling time locking are realized through a unified time base, so that sampling action and time counting are accurately aligned, and the data synchronization precision and consistency of distributed acquisition nodes are improved.

Disclosed is a receiver including a pre-processing block that pre-processes a received signal transmitted from an external transmitter and generates a pre-processing signal, an equalization block that generates an equalization signal based on the pre-processing signal and error threshold values, and a threshold generation block that generates the error threshold values and data threshold values. The threshold generation block generates a delay signal obtained by delaying the equalization signal by a unit time interval, generates a filter signal based on subtracting the delay signal from the equalization signal, and generates the error threshold values and the data threshold values based on the filter signal.

The invention provides an optical module and a link optimization method and system. The method comprises the following steps that: the microcontroller issues a gain value, so that the continuous time linear equalizer performs equalization processing on an input voltage signal; the time processing module is used for sampling a voltage signal output by the continuous time linear equalizer to obtain sampling data; and the microcontroller determines the gain configuration of the continuous time linear equalizer based on the sampling data under different gain values. Compared with the prior art, the power consumption and the time delay of the module are equal to those of a traditional LPO, and meanwhile, the self-adaptive capability which is only achieved by a DSP scheme in the past is obtained. The application scene and deployment flexibility of the LPO technology are expanded; and meanwhile, the link performance can be always maintained near the optimal point, so that the risk that the performance is continuously deteriorated until error codes occur is fundamentally avoided, and intelligent maintenance of the link state is realized.

This application relates to the field of communication technologies, and discloses a communication method and apparatus. On example method includes: a backscatter device receives an excitation signal from an exciter. The backscatter device determines a backscatter signal pattern in a backscatter signal pattern set, where the backscatter signal pattern set includes a plurality of backscatter signal patterns, and backscatter reference signals in the plurality of backscatter signal patterns do not overlap in time domain. The backscatter device modulates a backscatter reference signal and a backscatter data signal on the excitation signal based on the determined backscatter signal pattern, to obtain a backscatter signal. The backscatter device sends the backscatter signal to a receiver.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

The invention provides a bus magnetic encoder precision improving method, system and device and a storage medium, relates to the technical field of servo control, and is applied to a main control chip, and the main control chip is connected with a bus communication chip through a first communication interface and connected with a magnetic encoder chip through a second communication interface. The method comprises the following steps: receiving a position request protocol packet sent to a bus communication chip by a servo driver through a first communication interface; when the position request protocol packet meets the preset requirement, generating a synchronous trigger signal; according to the synchronous trigger signal, calculating a target time point when the second communication interface reads the position data of the magnetic encoder chip; when the time point is reached, reading position data of the magnetic encoder chip; and generating a response position protocol packet according to the position data, and sending the response position protocol packet to the servo driver. The method has the technical effects that the delay of receiving the position data by the servo driver is reduced, and the dynamic change of the delay is minimum.

The invention discloses a filter circuit, a clock data recovery method, a circuit and a receiver, and belongs to the technical field of signal processing. The filter circuit comprises: a voting module configured to vote according to at least two groups of input data to obtain a target voting result, and send the target voting result to a selection module, each group of input data comprising a clock phase and data, and the target voting result indicating a relative relationship between the clock phase and the data; the selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient and send the clock adjustment parameter and the target adjustment coefficient to the processing module; the processing module is configured to obtain recovery parameters according to the clock adjustment parameters and the target adjustment coefficient, and the recovery parameters are used for recovering the clock and the data. The obtained recovery parameters are more accurate, noise is effectively suppressed, and the accuracy of recovering clocks and data based on the recovery parameters is improved.

To enable varying a skew amount and waveform observation.SOLUTION: A differential skew generation device 1 includes: a clock oscillator 2 for oscillating and outputting a clock signal; a first pattern generator 4A for outputting a positive signal to an object W to be measured from a first output terminal 11A at timing of a signal in which a phase angle is adjusted by IQ modulation of the clock signal; a second pattern generator 4B for outputting a negative signal to the object W to be measured from a second output terminal 12B at timing of a signal in which a phase angle is adjusted by IQ modulation of the clock signal; and a monitoring device 5 connected to a second output terminal 12A of a first signal generator 4A and a first output terminal 11B of a second signal generator 4B. The first pattern generator 4A and the second pattern generator 4B operate in synchronization with each other and allocate an integer unit of a UI of a set skew amount to transmission timing shift and a decimal unit as IQ modulation to control.SELECTED DRAWING: Figure 1

Disclosed in the present invention are a method for precise transmission and parsing of a phase-cut transmission control signal, a control system, an apparatus and a gateway device. On the basis of a live wire alternating current sinusoidal signal, generation of a zero-crossing pulse signal is triggered every T / 2 cycle; a synchronization signal immediately follows the generation triggering of a current zero-crossing pulse; during a valid identification cycle Ta, a falling edge of an alternating current half wave is caused to generate a right notch corresponding to a time tR, or an original state is maintained until a next zero-crossing pulse is generated; the generation of a zero-crossing pulse represents a first digital signal, and the generation of a right notch represents a second digital signal, signals outside the cycle Ta being invalid. A midpoint between a rising edge and a falling edge of each zero-crossing pulse is used as a theoretical zero-crossing point to trigger timing, and the position of the theoretical zero-crossing point is corrected in real time for each zero-crossing pulse signal, thereby eliminating communication errors caused by alternating current interference; a synchronization signal and a valid identification cycle are used to mark the start and the end, thereby achieving precise parsing; and when there is no data transmission, only zero-crossing pulses are generated, thereby reducing energy consumption.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

To provide a battery management system capable of performing synchronization of a measurement timing of a battery in a plurality of devices as accurately as possible.SOLUTION: A device 10...1N includes an oscillator 29 that generates a second clock whose frequency can be controlled, and a time information generation part 30 generates second time information from the second clock generated by the oscillator 29. The device 10...1N generates a measurement timing of a battery from the second time information. When receiving a synchronization command from a controller 52, the device 10...1N compares the received first time information with the second time information, and controls the frequency of the oscillator 29 so as to eliminate the time difference from the compared difference. The device 10...1N controls the frequency of the second clock of the oscillator 29 to approach the frequency of the first clock of the controller 52.SELECTED DRAWING: Figure 1

A method of synchronizing time across a plurality of time domains between a master node and a slave node is provided. The method comprises transmitting, by the master node, a reference time indicated by a hardware clock of the master node to the slave node, synchronizing, by the slave node, a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node, transmitting, by an offset clock layer of the master node, an offset of a first time domain among the plurality of time domains to an offset clock layer of the slave node, and obtaining, by the PTP layer of the slave node, a time in the first time domain by applying the offset of the first time domain to a reference time indicated by the hardware clock of the slave node.

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

Provided in the embodiments of the present disclosure are a carrier phase tracking method and device for an orthogonal frequency division multiplexing (OFDM) multi-carrier system. The method includes: performing frequency domain tracking on a received current OFDM symbol and determining a phase of each subcarrier; analyzing a phase curve of all subcarriers and determining an inter-symbol phase average offset, and the inter-symbol phase average offset is used to characterize an estimated value of a difference obtained by subtracting a second value from a first value, the first value is a carrier phase value of the current OFDM symbol, and the second value is an estimated value of a carrier phase of a previous OFDM symbol; and performing time domain tracking by using the inter-symbol phase average offset as an input phase and determining an estimated value of a carrier phase of the current OFDM symbol.

The invention discloses a digital signal processing method and system based on an FPGA, relates to the field of digital signal processing, and introduces a staged variable bandwidth CDR strategy. In the initial stage, the signal frequency offset is quickly estimated through feedforward frequency analysis, and a high-bandwidth loop is started on the basis of the signal frequency offset, so that top-speed locking is realized, and the requirements of production testing and other scenes on efficiency are met. When the system confirms that locking is stable through hardware logic, a multi-step interpolation state machine is triggered, the state machine can smoothly switch the coefficient of the loop filter from a high bandwidth mode to a low bandwidth mode without disturbance, and the lock losing risk in the switching process is avoided. Finally, in a stable low-bandwidth mode, the system can perform accurate jitter decomposition and data analysis by using a high-precision recovery clock. In this way, the two modes of rapid capture and high-precision measurement are fused in one operation process, and the static design limitation in the prior art is solved.

Embodiments of this application provide a synchronization signal block transmission method and a communication apparatus. The method includes: receiving a first synchronization signal block SSB from a network device, where the first SSB is a first-type SSB for a first terminal device; and if the first SSB is a second-type SSB for a second terminal device, determining a first control-resource set and / or first common search space based on the first SSB. In the method, different results may be obtained when the second terminal device and the first terminal device identify a type of the first SSB, and the second terminal device and the first terminal device may use the first SSB in different manners. For example, the second terminal device may determine the first control-resource set and / or the first common search space based on the first SSB, to improve utilization of the SSB.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

An application identifies a metadata field within a Remote Direct Memory Access (RDMA) message structure that can be used for timestamp injection. The application generates a high-resolution timestamp that captures a time when the RDMA message is sent, where the high-resolution timestamp has a first size that exceeds a size of the metadata field. The application compresses the high-resolution timestamp into a compressed timestamp having a second size that fits within the size of the metadata field, and injects the compressed timestamp into the metadata field of the RDMA message, the RDMA message sent from a sender host to a receiver host. The application calculates a one-way delay between the sender host and the receiver host using the compressed timestamp, and outputs a control signal based on the one-way delay.

The invention provides a multi-channel data alignment method and device based on delay compensation. The method comprises the following steps: detecting an alignment mark in target data of a data channel by applying an alignment mark detection module; corresponding data reconstruction modules are arranged on the multiple data channels, and the data reconstruction modules are used for reconstructing the target data, so that the data of the data channels are aligned and marked at the same position in one beat of data after being reconstructed; the data calibration module receives the data output by the plurality of cache modules, detects the delay deviation among the data of the plurality of data channels, outputs the delay deviation to the delay matrix module, and detects the delay deviation among the target data of the plurality of data channels, and the delay matrix module controls the time for each cache module to transmit the data to the data calibration module. The invention further provides a device for implementing the method. According to the invention, multi-channel data alignment can be flexibly realized with low complexity.

The embodiment of the present application provides a data transmission method and related equipment, which are used for synchronously transmitting haptic information and other types of information, increasing transmission efficiency, and improving overall user experience. The method of the embodiment of the present application comprises the following steps: a network device receives a haptic data stream and at least one first data stream sent by a machine side device, wherein the haptic data stream and the at least one first data stream comprise a synchronization identifier; and the network device synchronizes transmission time of the haptic data stream and the at least one first data stream.