623results about "Synchronising arrangement" patented technology

The invention relates to the technical field of data recording, in particular to a data recording system for an automatic driving vehicle, and the system comprises a multi-source signal synchronization module, a behavior stage recognition module, a track abnormity elimination module, a dynamic compression adjustment module and a segmented index marking module. According to the method, a unified time alignment mechanism is constructed in a signal synchronization processing link, a strict corresponding relation between acquisition sequences is ensured, key time sequence characteristics of driving behavior switching are extracted by adopting a multi-behavior parameter comprehensive judgment method, segmented expression of a complex driving process is realized, and the accuracy of driving behavior switching is improved. According to track anomaly identification, through collaborative screening of inertial data and a positioning track, abnormal fragments which do not conform to physical rules are effectively eliminated, data compression dynamically sets interval length according to a parameter combined fluctuation trend, the fidelity of a key period is remarkably improved, non-key data redundancy is inhibited, and after a segmented index structure is established, the data compression efficiency is improved. And the data retrieval process is clearer.

The invention relates to the technical field of communication, and discloses a network communication chip signal interference suppression processing method. The method comprises the following steps: acquiring a local oscillator phase jitter sequence in real time through an on-chip phase noise monitoring unit; estimating Doppler frequency shift and channel coherence time based on the sequence; dynamically adjusting the closed-loop bandwidth of the phase-locked loop; and generating a phase compensation signal, and performing time-varying channel minimum mean square error equalization in combination with a received baseband signal to eliminate inter-symbol interference. The system integrates a phase noise monitoring function module, a channel parameter estimation function module, a phase-locked loop bandwidth regulation function module, a phase compensation generation function module and an interference joint elimination function module. By means of dynamic bandwidth reconstruction and high-precision phase compensation, the bit error rate under high-speed movement is remarkably reduced, the 5G millimeter wave communication standard requirement is met, and the method has the advantages of being achieved on a whole chip, low in delay and high in robustness.

The invention relates to the technical field of digital demodulation, in particular to a digital demodulation method suitable for deep ultraviolet light communication, which comprises the following steps of: adopting multiple delay processing with half code element width, and respectively carrying out double extraction processing on a discrete sampling signal which is not subjected to delay processing and a plurality of delay sampling signals to obtain a plurality of delay extraction signals; in this way, the key sampling time in the coverage code element period can be ensured, and a basis is provided for subsequent accurate synchronization; a plurality of delay extraction signals are respectively input into corresponding equalization processing units, a preset local training sequence is loaded to each equalization processing unit to obtain a plurality of equalization filtering signals, and the plurality of equalization filtering signals and the preset local training sequence are respectively subjected to related judgment processing, so that the inter-symbol interference is inhibited, and meanwhile, the equalization processing efficiency is improved. The synchronization signal can be quickly screened out, so that the problem that inter-symbol interference and synchronization are difficult to consider in a traditional demodulation method is solved, and the demodulation efficiency and reliability are remarkably improved.

The invention relates to the technical field of video monitoring, and particularly discloses a video acquisition system and method based on time triggering, and the system comprises a high-precision clock source, a hardware triggering signal generation module, an image sensor, a timestamp precise acquisition module and a system main control module. The high-precision clock source provides a reference clock; the hardware trigger signal generation module generates a synchronous trigger pulse to drive the image sensor to expose; the timestamp accurate acquisition module directly captures an exposure completion signal output by the sensor and generates a corresponding high-precision original timestamp; and the system main control module fuses and packages the timestamp and the image data. The method is realized based on the system. According to the invention, the accuracy and stability of the triggering moment are ensured from the source, and the accurate correspondence between the timestamp and the physical exposure moment is realized.

The invention relates to the technical field of Ethernet communication and digital information transmission, and discloses an Ethernet-based time synchronization acquisition method, device and equipment and a medium, and the method comprises the steps: obtaining initial network time based on a network time protocol and a precise time protocol; recovering the synchronous clock signal from the Ethernet physical layer signal and generating a trigger pulse signal aligned with a second boundary to generate second-level reference time; the trigger pulse signal and the synchronous clock signal are used for executing high-frequency counting accumulation to generate nanosecond-level fine time; performing frequency division processing on the synchronous clock signal based on the sampling rate configuration parameter to obtain a sampling driving clock; the analog-to-digital conversion unit is triggered at the effective jump edge of the sampling driving clock to sample and latch nanosecond-level fine time to generate a sampling timestamp, and the sampling timestamp is output in combination with sampling data. According to the method, time recovery, time refinement and sampling time locking are realized through a unified time base, so that sampling action and time counting are accurately aligned, and the data synchronization precision and consistency of distributed acquisition nodes are improved.

The invention provides an optical module and a link optimization method and system. The method comprises the following steps that: the microcontroller issues a gain value, so that the continuous time linear equalizer performs equalization processing on an input voltage signal; the time processing module is used for sampling a voltage signal output by the continuous time linear equalizer to obtain sampling data; and the microcontroller determines the gain configuration of the continuous time linear equalizer based on the sampling data under different gain values. Compared with the prior art, the power consumption and the time delay of the module are equal to those of a traditional LPO, and meanwhile, the self-adaptive capability which is only achieved by a DSP scheme in the past is obtained. The application scene and deployment flexibility of the LPO technology are expanded; and meanwhile, the link performance can be always maintained near the optimal point, so that the risk that the performance is continuously deteriorated until error codes occur is fundamentally avoided, and intelligent maintenance of the link state is realized.

To enable varying a skew amount and waveform observation.SOLUTION: A differential skew generation device 1 includes: a clock oscillator 2 for oscillating and outputting a clock signal; a first pattern generator 4A for outputting a positive signal to an object W to be measured from a first output terminal 11A at timing of a signal in which a phase angle is adjusted by IQ modulation of the clock signal; a second pattern generator 4B for outputting a negative signal to the object W to be measured from a second output terminal 12B at timing of a signal in which a phase angle is adjusted by IQ modulation of the clock signal; and a monitoring device 5 connected to a second output terminal 12A of a first signal generator 4A and a first output terminal 11B of a second signal generator 4B. The first pattern generator 4A and the second pattern generator 4B operate in synchronization with each other and allocate an integer unit of a UI of a set skew amount to transmission timing shift and a decimal unit as IQ modulation to control.SELECTED DRAWING: Figure 1

Embodiments of this application provide a synchronization signal block transmission method and a communication apparatus. The method includes: receiving a first synchronization signal block SSB from a network device, where the first SSB is a first-type SSB for a first terminal device; and if the first SSB is a second-type SSB for a second terminal device, determining a first control-resource set and / or first common search space based on the first SSB. In the method, different results may be obtained when the second terminal device and the first terminal device identify a type of the first SSB, and the second terminal device and the first terminal device may use the first SSB in different manners. For example, the second terminal device may determine the first control-resource set and / or the first common search space based on the first SSB, to improve utilization of the SSB.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

The embodiment of the present application provides a data transmission method and related equipment, which are used for synchronously transmitting haptic information and other types of information, increasing transmission efficiency, and improving overall user experience. The method of the embodiment of the present application comprises the following steps: a network device receives a haptic data stream and at least one first data stream sent by a machine side device, wherein the haptic data stream and the at least one first data stream comprise a synchronization identifier; and the network device synchronizes transmission time of the haptic data stream and the at least one first data stream.

The invention discloses a PCIe multichannel data alignment method based on SKP code detection, and relates to the technical field of data processing. The method comprises the following steps: collecting link state parameters of a PCIe link in real time, wherein the link state parameters at least comprise inter-channel offset, an elastic buffer water level and a link error rate; based on a preset adaptive strategy, dynamically determining an insertion strategy of an SKP ordered set through an adaptive decision engine according to the collected link state parameters, and obtaining an SKP insertion instruction which at least comprises an SKP insertion frequency adjustment parameter; based on an SKP insertion instruction, an original fixed interval counter is covered through an SKP insertion scheduler, and synchronous insertion of an SKP ordered set on all active channels is triggered at a specified moment; and continuously monitoring a real-time link state and adjusting an SKP insertion strategy until dynamic self-adaptive alignment of multi-channel data is realized. According to the PCIe multi-channel data alignment method and device, the timeliness and flexibility of PCIe multi-channel data alignment are effectively improved.

A first partition of a distributed computing system can synchronously receive first data from a second partition of the distributed computing system. The first partition can execute one or more processor operations based at least in part on the first data to generate second data. The first partition can synchronously send the second data to a third partition of the distributed computing system. The one or more processor operations can be executed asynchronously with respect to at least one of the second partition and third partition.

The invention provides a multi-frequency TDD (Time Division Duplex) analog synchronization circuit and method, which can solve the problems of high cost, poor precision and low sensitivity of a TDD synchronization scheme in the prior art, and comprises a radio frequency selection path used for selecting and outputting a single-frequency-band radio frequency signal from input radio frequency signals according to a control signal; the detector is connected with the radio frequency selection path and used for performing envelope detection on the target radio frequency signal, and the detector is provided with an inverted output end VDN; the processor comprises an ADC input end, and the ADC input end is connected with the inverted output end VDN of the detector and used for collecting the detected voltage signals; the processor is also connected with the radio frequency selection path and is used for sending a control signal to control the radio frequency selection path to gate a corresponding frequency band channel; the processor identifies the frame header position of the radio frequency signal according to the voltage signal collected by the ADC input end, and outputs an uplink switching signal and a downlink switching signal.

The invention discloses a Starlink satellite downlink signal timing synchronization method based on deep learning, and the method comprises the steps: firstly carrying out the segmentation cross-correlation preprocessing of a received signal, and generating a two-dimensional real number feature map with significant spectral line features; then, an improved SS-YOLOv9 network model is constructed and trained, according to the model, in a YOLOv9 infrastructure, a lightweight SimAM saliency attention module is embedded into a backbone network to enhance feature separability, an FAF adaptive feature fusion module is introduced into a path aggregation structure of a neck network to optimize multi-scale feature fusion, and the feature fusion is optimized; precise positioning is realized by adopting a decoupling detection head and a coordinate attention mechanism; and finally decoding bounding box coordinates output by the network into timing synchronization points in original signals. According to the method, the problem that the performance of a traditional method is sharply deteriorated in a severe channel environment is effectively solved, and the method has high precision, high robustness and excellent environmental adaptability.

A half-duplex data communication system, comprising a first communication device and a second communication device, wherein the first communication device is connected to the second communication device by means of a communication link. The first communication device sends a first signal to the second communication device; the second communication device sends a second signal to the first communication device; the first signal comprises a synchronization frame; the second communication device recovers a data frame synchronization signal on the basis of the received synchronization frame; the second communication device communicates with a peripheral device on the basis of the data frame synchronization signal; a local clock generation module in the second communication device generates a local clock of the second communication device; the clock for sending the second signal by the second communication device is the local clock of the second communication device; and the first signal and the second signal are transmitted on the communication link in a time-division manner.

The present disclosure relates to a method and system for synchronizing multi-band radio systems of a 5G NR Integrated Macro gNB with Carrier Aggregation The method includes receiving a primary reference clock signal at least one of a Global Positioning System module and a precision time protocol source; continually monitoring the received primary reference clock signal to determine if the primary reference clock signal is received at least one of the Global Positioning System module and the precision time protocol source; generating a 1 pulse per second output signal and clock based on the determined primary reference clock signal; transmitting the generated 1 pulse per second output signal to a system synchronizer and designating the 1 pulse per second and clock output signal as principal input source for a phase and frequency synchronization of all associated clock outputs.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

An NTP time-stamp rewriting device (1) comprises: a PTP time synchronization unit which acquires information of a reference time from a grand master device (2) by PTP; an NTP time-stamp rewriting unit which rewrites, as a PTP reference time, the time stamp of a response from an NTP server device (3) to a request for time synchronization by NTP from an NTP client device (4), which is a target of time synchronization; and an output control unit which transmits the response acquired by rewriting the time stamp to the NTP client device (4). The NTP client device (4) performs time synchronization on the basis of the time stamp of the response received from the output control unit of the NTP time-stamp rewriting device (1).

The application provides a substation-oriented anchor point timestamp calibration method and related device, which is applied to a collection terminal in a substation monitoring system, the substation monitoring system further comprises a master clock and a sensor in communication connection with the collection terminal, and the method comprises the following steps: determining a drift parameter of a local crystal oscillator of the collection terminal according to a clock offset sequence between the collection terminal and the master clock in a plurality of continuous synchronization periods; correcting a sampling counter in the collection terminal by using the drift parameter; if a transient partial discharge signal is detected according to a data frame sequence collected by the sensor on a target metal pipeline in the substation, a dynamic anchor point is established at a triggering moment of the transient partial discharge signal; and based on the dynamic anchor point, the generated sampling count sequence after correction and a time reference of the collection terminal, a data frame related to the transient partial discharge signal in the data frame sequence is timestamped. The accuracy of timestamping is improved.

A communication method and apparatus, which relate to the technical field of communications, and can enable each first device to synchronously send a message to each terminal device during a burst concurrency process, thereby improving the concurrency performance of a communication system. The method comprises: one or more first devices sending first information to a second device, wherein the first information is used for indicating the duration of a BA frame corresponding to the first device; and the second device respectively sending second information to the one or more first devices on the basis of the one or more pieces of first information, wherein the second information is used for indicating a synchronization timestamp at which the first device sends a message next time.

Wireless earbuds, a system, and an operation method therefor are disclosed. The wireless earbuds according to at least one of various embodiments of the present disclosure comprise: a first synchronization device for receiving audio data from a source device; and a second sink device for snooping the audio data transmitted from the source device, wherein the first synchronization device can transmit synchronization information related to the replay of a data packet to the second synchronization device.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

A system includes a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs. The system also includes an edge swallower or a pulse swallower coupled to the clock input of the deserializer.

The utility model belongs to the technical field of industrial automation, and provides an industrial network synchronization device which comprises an installation shell, a network synchronization module is arranged in the installation shell, vertical installation plates are symmetrically arranged on the inner top wall of the installation shell, the network synchronization module is located between the two installation plates, and the network synchronization module is located between the two installation plates. A heat dissipation chamber is formed between one side, far away from the network synchronization module, of the mounting plate and the mounting shell; the network synchronization module further comprises heat dissipation holes, the heat dissipation holes are formed in the side wall, right facing the installation shell, of the installation plate and are distributed in a multi-layer height mode, and a heat dissipation fan is arranged above the network synchronization module. Through the designed heat dissipation structure, the heat dissipation efficiency of the industrial network synchronizer can be improved, and the service life of internal parts can be prolonged.

The invention relates to a method for synchronizing a clock signal (CLK) with a reference clock (RCLK), wherein the clock signal is obtained on the basis of a local master clock and an adjustable frequency multiplication factor. The method utilizes a master clock signal to synchronize a frequency multiplication factor to compensate for frequency deviation. In a data packet gap of communication standards such as Bluetooth, corresponding signals are transmitted and received.

To avoid overflow and underflow of a modulator input buffer for a terrestrial digital broadcast and a next-generation terrestrial broadcast and to reproduce and provide a modulator clock for slave synchronization of each broadcast program signal.SOLUTION: A STL / TTL modulator (100) in a system for multiplexing a plurality of broadcast program signals with counter values added thereto by STL / TTL and transmitting the multiplexed signals includes counter sections (14, 17) for counting clocks synchronized with a modulation clock of the STL / TTL and a plurality of counter value adding sections (151-15N, 181-18M) for adding the counter values supplied from the counter sections (14, 17) to the packets to generate broadcast program signals with counter values at timing when the packets of the plurality of broadcast program signals arrive.SELECTED DRAWING: Figure 3A

The present disclosure describes a system, and a method to improve the system performance through hardware offload of a Best Master Clock Algorithm (BMCA). The system comprising at least one hardware entity integrated with a primary BMCA. The at least one hardware entity is configured to receive a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the at least one hardware entity is configured to select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity and transmit the best PTP master to a second entity for synchronizing a slave clock.

Techniques are provided for streaming service data with streaming frames including subframe(s) of O-RAN data and / or management data and subframe(s) of time-domain digital baseband data. The streaming frames are transported in a DAS fronthaul network configured to be implemented with conventional Ethernet links.

The invention discloses an unmanned aerial vehicle dynamic SFO compensation method and system based on filtering and double windows, and the method comprises the steps: carrying out the coarse synchronization of a leader sequence of a received signal of an unmanned aerial vehicle, obtaining an initial four-dimensional state variable, and initializing a forward window state vector and a backward window state vector based on the initial four-dimensional state variable; according to the initialized forward window state vector and the initialized backward window state vector, sequentially performing segmented SFO compensation on the plurality of data segments in the received signal to obtain segmented SFO compensation results of the plurality of data segments; according to the segmented SFO compensation results of the multiple data segments, smooth compensation is carried out on overlapping areas between the adjacent data segments, and smooth compensation results of the multiple overlapping areas are obtained; and combining the segmented SFO compensation results of the plurality of data segments and the smooth compensation results of the plurality of overlapping regions to obtain a receiving signal after SFO compensation. According to the invention, accurate SFO compensation can be realized.