2209results about "Synchronising arrangement" patented technology

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

The invention relates to the technical field of audio optimization, and discloses an audio data offset detection and compensation method and system, a storage medium and equipment, and the method comprises the steps: building a timestamp synchronization mechanism with nanosecond precision, and distributing a unique time identifier for each floating-point audio sampling point; detecting time sequence offsets of input and output signals through a self-adaptive sliding window, and positioning and determining an offset value based on a cross-correlation function extreme value; a compensation strategy is dynamically selected according to different intervals where the offset absolute value is located, and meanwhile a dynamic cache management mechanism is established to support real-time offset compensation operation; constructing a time sequence relation model through inter-channel signal correlation analysis in the multi-channel system, and implementing coordinated offset compensation based on a correlation analysis result and the compensation strategy; a performance monitoring index system is established to evaluate the offset compensation effect in real time, compensation parameters are adaptively adjusted according to audio content characteristics and system performance feedback, and accurate time sequence control over audio data is achieved through the method.

According to the optical carrier microwave stable transmission system based on the temperature control optical fiber delay line provided by the invention, accurate reverse compensation is carried out on delay jitter change through the delay compensation module, and excellent delay consistency is shown in ultra-wideband signal transmission; the defect that compensation devices such as a traditional piezoelectric ceramic optical fiber stretcher, an optical phase shifter, a cascade multi-stage optical switch and a motor space optical delay line cannot meet the requirements of large range, high precision, quick response and wide frequency spectrum compensation capability at the same time is overcome; that is to say, the link delay compensation scheme in the transmission system has large-range, high-precision, quick-response and wide-spectrum compensation capabilities, and is particularly suitable for optical fiber transmission links with high stability and consistency requirements on ultra-wideband signal transmission.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

The invention relates to the technical field of data recording, in particular to a data recording system for an automatic driving vehicle, and the system comprises a multi-source signal synchronization module, a behavior stage recognition module, a track abnormity elimination module, a dynamic compression adjustment module and a segmented index marking module. According to the method, a unified time alignment mechanism is constructed in a signal synchronization processing link, a strict corresponding relation between acquisition sequences is ensured, key time sequence characteristics of driving behavior switching are extracted by adopting a multi-behavior parameter comprehensive judgment method, segmented expression of a complex driving process is realized, and the accuracy of driving behavior switching is improved. According to track anomaly identification, through collaborative screening of inertial data and a positioning track, abnormal fragments which do not conform to physical rules are effectively eliminated, data compression dynamically sets interval length according to a parameter combined fluctuation trend, the fidelity of a key period is remarkably improved, non-key data redundancy is inhibited, and after a segmented index structure is established, the data compression efficiency is improved. And the data retrieval process is clearer.

The invention discloses a high-precision frequency synchronization method based on cross-spectrum phase slope. The method comprises the following steps: a reference node sends a frequency information transmission signal; the common node receives the frequency information transmission signal; the common node performs mutual correlation with a reference signal generated by a local clock through matched filtering to obtain time delay information; the common node calculates a phase difference according to the time delay information and calibrates a local frequency according to the phase difference; wherein the time delay information is measured through a cross-spectrum phase slope method, and the cross-spectrum phase slope method calculates time delay according to the slope of a phase-frequency response curve of a matched filtering result. According to the high-precision frequency synchronization method based on the cross-spectrum phase slope, the problems of low phase discrimination resolution and low frequency offset resolution during frequency synchronization caused by low sampling frequency of a distributed system are solved.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The invention discloses a serial port communication transmission method and system with high baud rate tolerance. The method comprises the following steps: S1, monitoring a serial port communication line until a level change from logic '1' to logic '0' is detected, and detecting a start bit of a data frame through a triple acknowledgement mechanism; s2, after the transmission of the data bits and the optional parity check bits is completed, continuously monitoring the serial port communication line until the level change from the logic '0' to the logic '1' is detected, and confirming a stop bit for detecting a data frame through triple sampling; and S3, after the stop bit of the data frame is ended, returning to the step S1 to detect the start bit of the next frame of data. According to the invention, by adopting a triple acknowledgement mechanism and a triple sampling acknowledgement method, the start bit and the stop bit of the data frame can be accurately detected, accurate receiving of data can be kept even under the conditions of Baud rate change and noise interference, and an efficient and reliable serial port communication solution is provided for users.

The invention belongs to the technical field of power system measurement, and relates to a three-phase power parameter wireless synchronous measurement and vector analysis method and system, and the method comprises the following steps: generating and broadcasting a synchronous pulse code containing triggering phase information; generating a predicted phase angle; obtaining a comprehensive phase deviation value; performing dynamic feature separation processing on the comprehensive phase deviation value to generate a slowly-varying propagation delay feature and a transient prediction error feature; injecting the prediction error characteristics into a local phase predictor for calibration; acquiring phase voltage / current data based on the compensated sampling time, and calculating a fundamental wave effective value and a phase angle relative to a local calibration time reference; and packaging the fundamental wave effective value, the phase angle and the local timestamp into a simplified data packet and transmitting the simplified data packet to an analysis terminal. According to the method, the problems that in a traditional mode, satellite time service rejects signals in a substation indoor or underground scene, and synchronization interruption is easily caused by electromagnetic interference are solved.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

The invention relates to the technical field of communication, and discloses a network communication chip signal interference suppression processing method. The method comprises the following steps: acquiring a local oscillator phase jitter sequence in real time through an on-chip phase noise monitoring unit; estimating Doppler frequency shift and channel coherence time based on the sequence; dynamically adjusting the closed-loop bandwidth of the phase-locked loop; and generating a phase compensation signal, and performing time-varying channel minimum mean square error equalization in combination with a received baseband signal to eliminate inter-symbol interference. The system integrates a phase noise monitoring function module, a channel parameter estimation function module, a phase-locked loop bandwidth regulation function module, a phase compensation generation function module and an interference joint elimination function module. By means of dynamic bandwidth reconstruction and high-precision phase compensation, the bit error rate under high-speed movement is remarkably reduced, the 5G millimeter wave communication standard requirement is met, and the method has the advantages of being achieved on a whole chip, low in delay and high in robustness.

The invention discloses a low-power-consumption data transmission method for a low-orbit satellite internet-of-things terminal, and relates to the technical field of satellite communication, and the method comprises the steps: calculating an overhead time window through employing a satellite ephemeris and a terminal GNSS coordinate, and introducing atmospheric refraction and movement position correction; determining a wake-up advance containing equipment preheating and error compensation, and waking up the terminal before the window; the battery voltage is collected, and three strategies of band cascade coding, compression and error correction sending and only data abstract sending are divided according to the electric quantity; receiving satellite dynamic energy factors to adjust transmitting power and the number of data packets; and after completion, entering dormancy, and only leaving a low-power-consumption clock to maintain a time sequence. Through accurate awakening, hierarchical transmission, double-clock calibration and self-learning, the terminal endurance is prolonged, the access success rate and the link utilization rate are improved, and power consumption and reliability are balanced.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit and an LVDS transmitting circuit for cross-BANK transmission. The LVDS receiving circuit for cross-BANK transmission comprises a clock channel and a plurality of data channels, the clock channel and the data channels are distributed in at least two BANKs, and the clock channel and at least one of the data channels are located in the same BANK; the programmable phase-locked loop is used for receiving a single-ended clock signal generated by the clock channel, and the first global clock buffer and the second global clock buffer are respectively used for buffering a first clock and a second clock and then outputting the first clock and the second clock; each of the clock channel and the data channel comprises a differential-to-single-ended module, a delay module and a serial-to-parallel conversion module. The programmable phase-locked loop and the global clock buffer are introduced, the clock channels and the data channels are distributed in the at least two BANKs, it is guaranteed that part of the data channels and the clock channels are located in the same BANK, and a flexible and efficient LVDS transmission architecture for cross-BANK transmission is achieved.

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

Embodiments of the present disclosure provide a data transmission method, a data link layer, a chip interconnection interface, and an electronic device. The data transmission method is applied to the data link layer of the chip interconnection interface, the data link layer communicates with the system bus and the physical layer, the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or in a second clock domain and a third clock domain. The method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer; or, the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in the third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

Two pointers are initialized. The first pointer is incremented every M cycles of a monitored clock and the second pointer is incremented every N cycles of a reference clock, where M and N are determined from a frequency relationship between the clocks. If the positions of the pointers are determined to differ by more than a drift threshold, an error is detected and corrective action may be taken.

The invention discloses a clock synchronization information acquisition method and device, and belongs to the technical field of communication. According to the method, the network is subjected to frequency synchronization simulation according to the obtained physical topology of the network and the frequency configuration information of the multiple network devices in the network, so that the frequency synchronization information of the multiple network devices is obtained, and the frequency synchronization information comprises the frequency state information and / or the frequency synchronization path. The frequency state information and / or the frequency synchronization path of the network equipment under the current frequency configuration can be accurately calculated through offline simulation of the real behavior of the network equipment in the frequency synchronization process, so that the frequency synchronization problem possibly occurring in the network can be positioned, and the network operation reliability is improved.

The invention relates to a synchronous acquisition and vector synthesis method for residual current data of multiple acquisition units, and the method comprises the steps: a collection unit which prepares to read the information of each acquisition unit; the acquisition unit interrupts multiple times of triggering acquisition and stores residual current data until residual current information of a complete sine period is acquired; processing the acquired residual current data, and judging whether the acquisition unit has a fault or not; and the collection unit completes residual current data vector synthesis and calculates the magnitude of the residual current. The invention further discloses a synchronous acquisition and vector synthesis system for the residual current data of the multiple acquisition units. According to the invention, the collection unit broadcasts the synchronization signal to the plurality of collection units, and the collection units can receive the synchronization signal at the same time and start to collect the residual current signal at the same time, thereby achieving the synchronous collection of the residual current, avoiding the phase error caused by the synchronization error in the residual current signal collection process, and improving the collection precision of the residual current signal.

This application provides a clock recovery method, an apparatus, and a system, and may be applied to a destination device in an optical transport network. The method includes: obtaining first phase difference information, and generating target phase difference information based on the first phase difference information and accumulated phase difference information, where the target phase difference information is used to recover a clock of a first data frame. The first phase difference information is a sum of input phase difference information and a local phase difference. The input phase difference information is a sum of phase differences between one or more groups of two adjacent upstream devices in one or more upstream devices of a destination device through which the first data frame passes. A value of the target phase difference information is a first value, a second value, or 0. The accumulated phase difference information is an accumulation of differences between historical first phase difference information and historical target phase difference information that are present before a destination device obtains the first phase difference information. According to the clock recovery method provided in this application, accuracy of clock recovery of an OTN frame can be improved, to improve system reliability.

Systems, methods, techniques, and other embodiments are disclosed to compensate, by applying an artificial intelligence / machine learning (AI / ML) model, a time synchronization error in a communication network, e.g. a wireless network. In one example, a system associated with the communication network configured to support time-sensitive deterministic communication, comprises a processor configured to; obtain time synchronization data of a plurality of communication network (CN) components in the communication network, wherein the time synchronization data indicates a time synchronization error in the communication network; apply an artificial intelligence (Al) model on the time synchronization data to adjust at least one control parameter; and compensate for the time synchronization error in the communication network using the adjusted at least one control parameter.

The invention relates to the technical field of digital demodulation, in particular to a digital demodulation method suitable for deep ultraviolet light communication, which comprises the following steps of: adopting multiple delay processing with half code element width, and respectively carrying out double extraction processing on a discrete sampling signal which is not subjected to delay processing and a plurality of delay sampling signals to obtain a plurality of delay extraction signals; in this way, the key sampling time in the coverage code element period can be ensured, and a basis is provided for subsequent accurate synchronization; a plurality of delay extraction signals are respectively input into corresponding equalization processing units, a preset local training sequence is loaded to each equalization processing unit to obtain a plurality of equalization filtering signals, and the plurality of equalization filtering signals and the preset local training sequence are respectively subjected to related judgment processing, so that the inter-symbol interference is inhibited, and meanwhile, the equalization processing efficiency is improved. The synchronization signal can be quickly screened out, so that the problem that inter-symbol interference and synchronization are difficult to consider in a traditional demodulation method is solved, and the demodulation efficiency and reliability are remarkably improved.

The in-vehicle device for receiving time synchronization information transmitted from each of a plurality of reference devices and transmitting the received time synchronization information to another device, includes: a communication unit configured to communicate with the other device; and an information processing unit configured to, if the communication unit receives a frame in which the time synchronization information is stored, store the time synchronization information in a specific queue with priority over other information, wherein the communication unit transmits the time synchronization information stored in the specific queue to the other device.

A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.

The invention discloses a clock source selection method and device and a communication system, and belongs to the technical field of communication. The method comprises: a first device obtains a first data set and a second data set, the first data set comprising a first clock level and a first clock identifier, and the second data set comprising a second clock identifier; and under the condition that the first clock level is not superior to a clock level threshold, the first equipment determines a clock source according to the first clock identifier and the second clock identifier, wherein the clock level threshold is configurable. According to the invention, the time synchronization precision can be improved, and the flexibility of clock source selection can be improved.

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

An optical communication system includes a master station device, and a slave station device. The master station device generates a first digital signal including control information, and transmits, to the slave station device, a downlink optical signal including the generated first digital signal and an analog main signal. The slave station device acquires the first digital signal included in the downlink optical signal received from the master station device, and performs a loop-back process of transmitting an uplink optical signal including the acquired first digital signal to the master station device. The master station device acquires the control information from the first digital signal included in the uplink optical signal received from the slave station device.

A subscriber station for a serial bus system and a method for communication. The subscriber station has a communication control device controlling a communication of the subscriber station with at least one other subscriber station of the bus system and generating a transmit signal. The communication control device generates the transmit signal according to a frame and to insert a field having a rising edge and a subsequent falling edge into the frame for the transition from a first communication phase to a second communication phase. The field has a predetermined length between the rising edge and the subsequent falling edge such that a sampling time at which a communication control device of the at least one other subscriber station of the bus system will sample the first bit of the second communication phase is situated between the rising edge and the subsequent falling edge.