261results about How to "To overcome the large delay" patented technology

In an improved system for receiving digital voice signals from a data network, a jitter buffer manager monitors packet arrival times, determines a time varying transit delay variation parameter and adaptively controls jitter buffer size in response to the variation parameter. A speed control module responds to a control signal from the jitter buffer manager by modifying the rate of data consumption from the jitter buffer, to compensate for changes in buffer size, preferably in a manner which maintains audio output with acceptable, natural human speech characteristics. Preferably, the manager also calculates average packet delay and controls the speed control module to adaptively align the jitter buffer's center with the average packet delay time.

A digital mobile communication system is provided with a facility by means of which it can establish a connection to the Internet network (12) via an Internet access point (14, 15). IAP settings needed for establishing a connection are stored in a mobile station (MS). When a mobile station (MS) roams, the closest point may, however, change, and IAP settings should be updated in the mobile station (MS). The invention comprises dividing the mobile communication system into IAP areas, which are given preferred IAPs. An IAP area may be e.g. a mobile communication network (11, 17). Mobile communication networks broadcast system information on the basis of which a mobile station may detect that the IAP area has changed and start a procedure for updating IAP settings. Updating may comprise retrieval of IAP settings from a special server (13) in the network maintained by an Internet service provider. Retrieval can be done e.g. via a short message service center (10). In one embodiment the mobile communication network broadcasts messages giving recommended IAP settings to mobile stations.

A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

An apparatus is provided for suppressing an echo signal included in a measured signal corresponding to a measured sound. In the apparatus, the measured signal and a reference signal in a time domain are transformed into a frequency domain, and calculated for obtaining each value of a ratio and a correlation between the measured signal and the reference signal in the frequency domain. With executing a comparison of the values of the ratio and the correlation, a coefficient is derived, where a product of the coefficient and the measured sound in the frequency domain gives an estimated value of the echo signal. The echo in the measured signal is suppressed with subtracting the estimation of the echo signal from the measured signal, respectively in the frequency domain.

A delta-sigma modulator comprising a first quantizer providing a first digital signal d0(k) representing the input signal g(t); a loop filter with input signal paths; a loop quantizer providing a corrective digital signal d1(k) representing the loop filter's output signal y(t); an array of feedback DACs D/A converting the sum d(k)=df(k)=d0(k)+d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter.The loop filter's input node is applied the difference of the input signal g(t) and the global analog feedback signal a3(t). The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k). The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs. The feedback DACs' different delays and gain coefficients are designed such that the modulator is stable. The filter's input signal paths and the compensating DAC are designed such that the gain from the input signal g(t) to the loop quantizer is small, ideally zero. Thus, the loop quantizer's resolving range can be a fraction of the first quantizer's resolving range, whereby the output signal's d(k) resolution can be much higher than the individual resolutions of d0(k) and d1(k).The delta-sigma modulator is well suited for the implementation of high-resolution wide-bandwidth A/D converters. Important applications include digital communication systems.

Embodiments of the present invention provide a method for transmitting low rate signals over an optical transport network, including: adapting the low rate signals into low rate optical channel data units of the same rate level with the low rate signals; asynchronously mapping each of the low rate optical channel data units into a low rate optical channel data tributary unit respectively, and generating justification overhead used for rate adaptation for each of the low rate optical channel data units; and forming a higher order optical channel data unit with at least one low rate optical channel data tributary unit and justification overhead corresponding to the low rate optical channel data tributary unit. The present invention enables the optical transport network to support mapping, multiplexing and highly efficient transmission of low rate signals.

The present invention relates to an architecture for stack robust fine granularity scalability (SRFGS), more particularly, SRFGS providing simultaneously temporal scalability and SNR scalability. SRFGS first simplifies the RFGS temporal prediction architecture and then generalizes the prediction concept as the following: the quantization error of the previous layer can be inter-predicted by the reconstructed image in the previous time instance of the same layer. With this concept, the RFGS architecture can be extended to multiple layers that forming a stack to improve the temporal prediction efficiency. SRFGS can be optimized at several operating points to fit the requirements of various applications while the fine granularity and error robustness of RFGS are still remained. The experiment results show that SRFGS can improve the performance of RFGS by 0.4 to 3.0 dB in PSNR.

One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system selectively perform security processing on data incoming from the network based on security associations stored in a memory external to the network interface system, typically a host system memory. The security association for any given frame, when available, is fetched from the external memory after the frame begins to arrive in the network interface system based in part on information contained in the frame. Preferably, the fetch begins before the frame is fully received and the security association is queued whereby security processing can begin without having to wait for the security association to be fetched.

When either a command value or an actually measured value is appropriately selected as an angular velocity used for the frictional torque calculation, the frictional compensation can be made valid at all times in both the case in which a robot is actively operated according to an angular velocity command and the case in which the robot is passively operated being pushed by an external force. In the case where a motor rotating direction and a collision direction are reverse to each other after a collision has been detected, the control mode is switched from the positional control to the electric current control and a torque, the direction of which is reverse to the direction of the motor rotation is generated by the motor, so that the motor rotating speed can be reduced and the collision energy can be alleviated. After that, when the motor rotating speed is reduced to a value not more than the setting value, the control mode is switched to the compliance control and the distortion caused in a reduction gear is dissolved. On the other hand, in the case where the motor rotating direction and the collision direction are the same, the control mode is directly switched from the positional control to the compliance control without passing through the electric current control. When the robot is operated whole following a collision force, the collision force can be alleviated.

A lamp emits pulse-shaped visible light when a wait period begins. If a radiation emission switch is not pressed in the wait period, X-ray radiation is not emitted from an X-ray source, and no charges are accumulated in photoelectric conversion elements of an X-ray imaging apparatus. In a non-read period, although signals are sequentially read from the photoelectric conversion elements, an output signal does not change. When the radiation emission switch is pressed in synchronization with a radiation-induced signal in a certain wait period, the X-ray source emits X-rays. After irradiation of X-rays, a photoelectric conversion period transitions to an actual read period. In the photoelectric conversion period, X-rays are emitted and transmitted X-ray information of a patient are accumulated in the photoelectric conversion elements of the X-ray imaging apparatus. In the actual read period, the accumulated information is read.

A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device including an oxide semiconductor film. A semiconductor device including the transistor is provided. A high-performance display device including the transistor is provided.

According to one aspect, there is provided a method of controlling access to a network resource. The method comprises receiving a request to grant a user access to the network resource, the request including a user identifier, determining whether the received user identifier is stored in a local user data store associated with the resource, and where it is not so determined determining, from user details stored in a master user data store, whether the user is authorized to access the resource, and where it is so determined obtaining a password, and storing the obtained password and user details in the local data store associated with the network resource.

An improved mechanism is provided for generating an execution log and coverage data for a set of computer code. To minimize the amount of storage required for storing execution log information, the mechanism: (1) stores only information pertaining to instructions that are actually executed during execution; and (2) stores the information in a hierarchically organized set of lists. In addition, to minimize the impact of execution log and coverage data generation on the execution of the computer code, coverage data is generated after execution has completed. By generating the execution log and coverage data in this manner, storage requirements are reduced, and execution performance is improved.

In embodiments of the present disclosure, improved capabilities are described for conserving back haul utilization in a wireless network, where optimization servers utilizing publish-subscribe broker services are provided within the wireless network to provide streaming data services required for applications streaming data to a plurality of mobile cellular devices, where the streaming data is not necessarily delivered to each of the plurality of mobile cellular devices at the same time.

It is inter alia disclosed a method, a computer program, an apparatus and a system for predictive behavioural targeting. Information on an access behaviour of a current user accessing content is obtained. At least one characteristic of the current user is predicted by a prediction module of the apparatus in response to the obtaining of the information on the access behaviour of the current user, the prediction at least being based on a model for the characteristic and on the obtained information on the access behaviour of the current user. The model is at least based on a set of parameters determined by a training module at least based on information from a plurality of training sets and provided to the prediction module from time to time for updating purposes.

An audio signal encoder includes a transform-domain path which obtains spectral coefficients and noise-shaping information on the basis of a portion of the audio content, and which windows a time-domain representation of the audio content and applies a time-domain-to-frequency-domain conversion. The audio signal decoder includes a CELP path to obtain a code-excitation information and a LPD parameter information. A converter applies a predetermined asymmetric analysis window in both if a current portion is followed by a subsequent portion to be encoded in the transform-domain mode or in the CELP mode. Aliasing cancellation information is selectively provided in the later case.

The system includes a jitter buffer for receiving speech packets in a Voice over Internet Protocol (VoIP) system, a playback device for adjusting the playback speed of the received speed packets, and a jitter buffer manager for detecting out of sequence packets in the jitter buffer and for sending commands to the playback device to adjust playback speed based on the detection. The speech signal is played back at the nominal speed when there are no out of sequence packets. The playback speed is decreased when an out of sequence packet is detected, thereby tending to increase the jitter buffer length. When an out of sequence packet arrives, the playback speed is increased in order to restore jitter buffer length to its nominal length.

In embodiments of the present disclosure, improved capabilities are described for conserving back haul utilization in a wireless network, where optimization servers utilizing publish-subscribe broker services are provided within the wireless network to provide streaming data services required for applications streaming data to a plurality of mobile cellular devices, where the streaming data is not necessarily delivered to each of the plurality of mobile cellular devices at the same time.

A solution to latencies associated with server side processing time, as well as to latency resulting from the transit of information or tools from a server side to a client or user side is provided. The server side and client side can be coupled via a hard link or a network-type connection such as the Internet or a local area network. Select delta page information is stored in a concise manner on client side. As a result, the client does not have to contact the server when a user requests page information that is associated with stored delta page information. The stored delta page information can be accessed and used to update the current page thereby yielding the requested page. Thus, latency from server side processing and network transit time is reduced. An algorithm can be implemented on the client side to identify relevant stored delta page information, and to update the current page with that delta page information.

An emergency stop signaling device for vehicles is disclosed, including a deceleration sensor which produces deceleration values, an integrated circuit control circuit which receives the deceleration values and produces LED activation control signals. An LED array lights in response to the LED activation control signals from the Integrated Circuit control circuit to produce a light pattern which is distinguishable from an ordinary braking signal. The deceleration sensor is preferably a digital deceleration sensor. The LED array is a flexible LED array, a portable LED array, a linear LED array or a circular LED or a combination of these. The IC control circuit produces signals which activate the LED array to a plurality modes of activity including a tail light mode, a stop light mode, and a panic stop mode.

A communication system that includes multiple conferencing devices connected in a daisy-chain configuration is communicably connected to far-end conference participants. Multiple conferencing devices provide improved sound quality to the far-end participants by reducing aural artifacts resulting from reverberation and echo. The daisy-chain communication system also reduces the processing and transmission time of the near-end audio signal by processing and transmitting the audio signal in frequency domain. Each conferencing device in the daisy chain performs signal conditioning on its audio signal before transmitting it in the frequency domain to a mixer. The output signal of the mixer is converted back to the time domain before being transmitted to the far-end. The daisy-chain configuration also provides a distributed bridge to external communication devices that can be connected to each conferencing device.

A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.

On a distributed data processing system, a history of file migration is maintained. When access to a file is requested and the file is not found, the migration history is consulted to determine the current location of the file, and to update links contained in other files that point to the request file.

Upon initialization, a VPC is set up between edge nodes. A control processor of each node creates an IP address/VPC mapping table using IP routing information and an address mapping table mapping correspondence between IP addresses and ATM addresses and supplied by a network management system. A gateway assigns a VCC to each packet input to the network. A sending-side edge node inputs the packet to the VPC corresponding to its destination by referring to the IP address/VPC mapping table. A transit node performs packet switching over VP. A receiving-side edge node transfers each packet to the gateway corresponding to its destination. If a series of packets meet a predetermined condition in a given edge node, its control processor sends VCC information to input interfaces of the edge node so that the packets are switched by an ATM switch in the edge node without intervention of the control processor.

A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.