219results about "General purpose stored program computer" patented technology

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. In some embodiments, the graph is populated according to rules relating to memory use and the numbers of cores necessary to implement a particular layer of the machine trained network such that nodes for a particular layer, in some embodiments, represent fewer than all the possible groupings of sets of clusters.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention discloses a chip particle interconnection interface protocol layer circuit compatible with a CHI protocol and a chip, and the chip particle interconnection interface protocol layer circuit comprises a transmitting unit and a receiving unit which are connected with an adapter layer and a physical layer in a protocol layer. The sending unit comprises a sending end virtual channel management module, a sending buffer unit and a packaging module which are connected in sequence, and the sending buffer unit is used for caching micro-packets of all channels and respectively comprises a request-monitoring sending buffer, a response sending buffer, a test sending buffer and a data sending buffer which are parallel; the receiving unit comprises an analysis module, a receiving buffer unit and a receiving end virtual channel management module which are connected in sequence, and the receiving buffer unit comprises a request-monitoring receiving buffer, a response receiving buffer, a test receiving buffer and a data receiving buffer which are parallel. The invention aims to enable the core particle interconnection interface to be compatible with the CHI protocol, so that the core particles realized by the ARM architecture can realize consistent interconnection through the CHI protocol.

Embodiments of the present disclosure provide a method that may include defining an object model containing a structural representation of events and artefacts through which contracts are created, changed, and brought to an end. The method may include accessing a machine learning classifier comprising a plurality of rule sets. The method may include applying the plurality of rule sets to one or more words of each corresponding contract document. The method may include linking identified one or more core attributes and one or more words of each corresponding contract document to an applicable object of the object model, determining prevailing terms of each corresponding contract document, and evaluating contract data variables and assigning a contract data risk value to one or more of contract data values. The method may include alerting a user when a contract risk exceeds a threshold value.

The invention relates to a cache architecture optimization method and device for a multi-chip integration system and a storage medium, and the method comprises the steps: obtaining an architecture topological graph of the multi-chip integration system; the architecture topological graph comprises a storage hierarchy graph and a network topological graph; the storage hierarchy graph is a hierarchy connection graph of a cache subsystem of the multi-chip integration system; the network topological graph is a core particle connection graph of the multi-core particle integrated system; constructing a system performance model based on the architecture topological graph; and solving the system performance model to obtain a target cache parameter, and generating a target cache architecture graph based on the target cache parameter and the storage hierarchy graph. According to the method and the device, the problem that the architecture of the cache subsystem in the multi-chip particle integrated system is difficult to achieve optimal optimization is solved.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.

The present application relates to the technical field of storage application, and discloses a physical address query method, a flash memory device controller and a flash memory device. The physical address query method comprises: acquiring a logical address; by querying a compact array, determining whether the compact array can map the logical address to a corresponding physical address; if the compact array cannot map the logical address to the corresponding physical address, querying a range bucket hash structure to determine whether a range bucket node corresponding to the logical address exists in a least recently used cache; and if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address from the range bucket node to obtain the physical address corresponding to the logical address. By querying from the compact array and the range bucket hash structure the physical address corresponding to the logical address, the present application can save DRAM resources and also maintain high indexing performance, thereby improving the query efficiency of the physical address.

Data processing systems and methods according to various embodiments are adapted for automatically detecting and documenting privacy-related aspects of computer software. Particular embodiments are adapted for: (1) automatically scanning source code to determine whether the source code include instructions for collecting personal data; and (2) facilitating the documentation of the portions of the code that collect the personal data. For example, the system may automatically prompt a user for comments regarding the code. The comments may be used, for example, to populate: (A) a privacy impact assessment; (B) system documentation; and / or (C) a privacy-related data map. The system may comprise, for example, a privacy comment plugin for use in conjunction with a code repository.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention belongs to the technical field of computers and artificial intelligence, and discloses a priority differential cache-based MoE batch reasoning method and system, and the method comprises the steps: recognizing global hot experts with higher activation frequency in each layer, enabling the global hot experts to remain in a high-priority cache during initialization, and building a priority list of the experts in each layer; in the reasoning stage, selecting an expert set needing to be activated in the current layer; the expert priority score is dynamically updated according to the activation and reuse behaviors of the experts, and the experts are migrated and replaced among the high-level cache, the middle-level cache and the low-level cache according to the priority score and a cache threshold value; according to a current layer gating result and a historical activation track, predicting an expert set which may be activated in a next layer, and asynchronously loading the expert set to a low-priority cache during current layer calculation so as to realize time overlapping of calculation and communication. According to the method, the expert migration frequency can be reduced, the cache hit rate and the throughput rate are improved, the video memory utilization rate is remarkably optimized, and good expansibility and universality are achieved.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention relates to an intelligent decision-making method and system for server customization demand matching. The method comprises the steps of obtaining a server customization demand input by a user; constructing a multi-dimensional demand portrait based on the server customization demand, wherein the demand portrait comprises a quantitative index and a configuration constraint condition; according to the demand portrait, executing configuration compatibility check, and identifying whether a compatibility problem exists or not; when the compatibility check is passed, a candidate configuration scheme is generated by adopting a multi-target genetic algorithm based on the demand portrait passing the compatibility check; and sorting and screening the candidate configuration schemes based on user preference data in the demand portraits passing the compatibility check to obtain a recommended scheme list, and transmitting the recommended scheme list to a display interface for a user to select and confirm, the recommended scheme comprising a component list, a price, a performance index and a recommendation reason. The method has the effect of improving the accuracy of server customization recommendation.

An inter-chip timing synchronization method comprising: for each pair of chips in a plurality of chips of a semiconductor device: determining a first one-way latency for transmissions from a first chip in the pair to a second chip in the pair of chips, and determining a second one-way latency for transmissions from the second chip in the pair to the first chip in the pair of chips; receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of chips; determining, by the semiconductor device driver and from the respective first one-way latency and the second one-way latency for each pair of chips, a loop latency between each pair of chips; adjusting, by the semiconductor device driver and for at least one pair of chips, a local counter of the second chip in the at least one pair of chips based on a characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of chips.

A neural network device including an on-chip buffer memory that stores an input feature map of a first layer of a neural network, a computational circuit that receives the input feature map of the first layer through a single port of the on-chip buffer memory and performs a neural network operation on the input feature map of the first layer to output an output feature map of the first layer corresponding to the input feature map of the first layer, and a controller that transmits the output feature map of the first layer to the on-chip buffer memory through the single port to store the output feature map of the first layer and the input feature map of the first layer together in the on-chip buffer memory.

A system on chip including: a plurality of processors; a system level cache memory that is shared by the plurality of processors; and a cache controller that transmits first data to another chip if an atomic operation has been performed on the first data, when the system level cache memory receives the first data from at least one of the plurality of processors.

Data processing systems and methods, according to various embodiments, are adapted for determining an applicable privacy policy based on various criteria associated with a user and the associated product or service. User and product criteria may be obtained automatically and / or based on user input and analyzed by a privacy policy rules engine to determine the applicable policy. Text from the applicable policy can then be presented to the user. A default policy can be used when no particular applicable policy can be identified using by the rules engine. Policies may be ranked or prioritized so that a policy can be selected in the event the rules engine identifies two, conflicting policies based on the criteria.

In variants, a device system can include a set of device parts that communicate using a response-request framework.

A method includes translating an instruction, received via a network interface, from a home control system to a command for an architectural covering. The method further includes transmitting the command to the architectural covering via a wireless covering interface. The method further includes estimating a position of a covering of the architectural covering. The method further includes transmitting the position to the home control system.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

An device is disclosed. A first buffer to store a query data point, and a second buffer to store a matrix of candidate data points. A processing element may process the query data point and the matrix of candidate data points to identify candidate data points in the matrix of candidate data points that are nearest to the query data point.

To provide a method for executing machine learning calculation using a calculation unit of special purpose, a storage device and an electronic system.SOLUTION: In a method by a computing device, a controller at least partially receives input activations provided from a memory address position associated with an index, determines whether or each of the input activations has either a zero value or a non-zero value, stores at least the one input activation in a memory bank and generates an index including the one or more memory address positions having the input activation value that is the non-zero value, broadcasts at least the one input activation on a data bus accessible by the one or more units among calculation arrays from the memory bank, detects the broadcast, and provides a control signal for preventing multiplication operation associated with zero input to at least the one unit among the calculation arrays.SELECTED DRAWING: Figure 5

Multifunctional electronic component, device, method and corresponding programs. The invention relates to an electronic data processing platform, comprising a general-purpose processor (PS) and a so-called level 1 memory (L1). This platform further comprises a programmable logic component (PL) comprising a so-called level 0 memory (L0), the programmable logic component being configured so as to define typologies of executable calculations, said platform further comprising orchestration software running on the general-purpose processor, the orchestration software being responsible for providing, to the programmable logic component, a set of configuration data for its execution within the limits of the typologies of executable calculations. Abstract figure: Figure 5

The invention provides a data processor starting system, equipment and a cluster. The data processor starting system comprises a data processor simulation peripheral device interconnection expansion device, and the peripheral device interconnection expansion device comprises a peripheral device interconnection expansion bridge device and a peripheral device interconnection expansion end device. The peripheral device interconnection expansion end device comprises a plurality of storage devices, the plurality of storage devices are connected with a plurality of operating system block devices, operating systems are mounted in the operating system block devices, the nonvolatile memory comprises option read-only memory mirror images, and the option read-only memory mirror images guide the operating systems in the corresponding operating system block devices to run; when the processor scans an upstream port of the peripheral device interconnection expansion bridge equipment, loading a first option read-only memory mirror image in the nonvolatile memory into a memory of the processor, and matching corresponding first operating system block equipment according to the first option read-only memory mirror image, and mounting the first operating system in the first operating system block device.

The present invention discloses an intelligent Android integrated basic control box, comprising a chassis and a cover, wherein two ends of the bottom of the chassis are provided with slide grooves, the interior of the slide grooves is connected with a bracket, the bracket is fixed to the chassis by a first screw, wherein a mounting hole is provided at the bottom end of the bracket, a card plate is provided at the top edge of the chassis, a card slot is provided inside the card plate, the cover is connected to the card slot inside the card plate, a fixing plate is provided at one side edge of the cover, and the fixing plate is connected to a groove on one side of the chassis. The intelligent Android integrated basic control box, when it is necessary to clean the heat sink for ventilation and heat dissipation inside the chassis, the knob on the threaded column is turned so that the knob is removed from the threaded column, and then the heat sink in the through hole is pushed from the side of the chassis so that the heat sink is removed along the threaded column, thereby facilitating the cleaning of the heat sink blocked by the ventilation holes.

Water buoys sense water characteristics and wirelessly transfer the water characteristics for delivery to a computer system. The computer system receives the water characteristics wirelessly transferred by the water buoys. The computer system receives a location and a user water condition preference transferred by a user communication device. The computer system processes the water characteristics, the location, and the user water condition preference, and in response, generates and transfers water condition information for the location for delivery to the user communication device.