37results about "General purpose stored program computer" patented technology

The invention belongs to the technical field of computers and artificial intelligence, and discloses a priority differential cache-based MoE batch reasoning method and system, and the method comprises the steps: recognizing global hot experts with higher activation frequency in each layer, enabling the global hot experts to remain in a high-priority cache during initialization, and building a priority list of the experts in each layer; in the reasoning stage, selecting an expert set needing to be activated in the current layer; the expert priority score is dynamically updated according to the activation and reuse behaviors of the experts, and the experts are migrated and replaced among the high-level cache, the middle-level cache and the low-level cache according to the priority score and a cache threshold value; according to a current layer gating result and a historical activation track, predicting an expert set which may be activated in a next layer, and asynchronously loading the expert set to a low-priority cache during current layer calculation so as to realize time overlapping of calculation and communication. According to the method, the expert migration frequency can be reduced, the cache hit rate and the throughput rate are improved, the video memory utilization rate is remarkably optimized, and good expansibility and universality are achieved.

The invention relates to an intelligent decision-making method and system for server customization demand matching. The method comprises the steps of obtaining a server customization demand input by a user; constructing a multi-dimensional demand portrait based on the server customization demand, wherein the demand portrait comprises a quantitative index and a configuration constraint condition; according to the demand portrait, executing configuration compatibility check, and identifying whether a compatibility problem exists or not; when the compatibility check is passed, a candidate configuration scheme is generated by adopting a multi-target genetic algorithm based on the demand portrait passing the compatibility check; and sorting and screening the candidate configuration schemes based on user preference data in the demand portraits passing the compatibility check to obtain a recommended scheme list, and transmitting the recommended scheme list to a display interface for a user to select and confirm, the recommended scheme comprising a component list, a price, a performance index and a recommendation reason. The method has the effect of improving the accuracy of server customization recommendation.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

Water buoys sense water characteristics and wirelessly transfer the water characteristics for delivery to a computer system. The computer system receives the water characteristics wirelessly transferred by the water buoys. The computer system receives a location and a user water condition preference transferred by a user communication device. The computer system processes the water characteristics, the location, and the user water condition preference, and in response, generates and transfers water condition information for the location for delivery to the user communication device.

The application discloses a multi-task execution method, device, equipment and medium, and belongs to the technical field of power electronics. The method comprises the following steps: setting independent threads for each operation task in an IEC61131-3 multi-operation task in advance; setting a task priority list for each operation task in the IEC61131-3 multi-operation task, and setting a target reference list according to the data calling relationship of each operation task; and sending the task priority list and the target reference list to a programmable logic controller, so that the programmable logic controller controls each operation task in the IEC61131-3 multi-operation task according to the task priority list and the target reference list. By using the method, the programmable logic controller can execute each operation task in the IEC61131-3 multi-operation task without being affected by other operation tasks, and the CPU load is more stable.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Systems and methods for automated workflow comprise assigning a set of first targets to an uncompiled first workflow. The uncompiled first workflow specifies a first set of process modules. Each such module is associated with a subset of unit operations. Each unit operation includes a time interval and specifies an instrument. For each target in the set of first targets, the uncompiled workflow is translated into an instance of a compiled first workflow comprising a linear temporal order of unit operations, each including execution instructions for an addressed instrument. A set of second targets is obtained and assigned a second uncompiled workflow. Compilation of the second uncompiled workflow for each second target produces a different instance of a compiled second workflow. Each second compiled workflow comprises a linear temporal order of unit operations, with each unit operation including execution instructions for an addressed instrument and specifying a time interval.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The application discloses a nuclear power KRTN16 channel in-situ processor hardware integrated system and a hot switching method, which comprises a total power supply, a main power supply, a backup power supply, a normal channel switch, a backup channel switch, a switching execution unit, a switching control unit, a mainboard card and a backup board card. The total power supply is connected with the input end of the normal channel switch and the input end of the backup channel switch. The main power supply is connected with the output end of the normal channel switch and the input end of the mainboard card. The control signal output end of the mainboard card and the control signal output end of the backup board card are connected with the input end of the switching control unit. The output end of the switching control unit is connected with the input end of the switching execution unit. The output end of the switching execution unit is connected with the execution signal input end of the normal channel switch and the execution signal input end of the backup channel switch. The output end of the backup channel switch is connected with the input end of the backup board card through the backup power supply. The application can realize hot switching quickly.

Various Data Subject Access Request (DSAR) processing systems are adapted for presenting a first webform on a first web site, the first webform being adapted to receive DSAR's and to route the requests to a first designated individual for processing; presenting a second webform on a second web site, the second webform being adapted to receive DSAR's and to route the requests to a second designated individual for processing; receiving, via the first webform, a first DSAR; at least partially in response to the receiving the first DSAR, automatically routing the first DSAR to the first designated individual for handling; receiving, via the second webform, a second DSAR; at least partially in response to the receiving the second DSAR, automatically routing the second DSAR to the second designated individual for handling; and communicating a status of both the first DSAR and the second DSAR via a single user interface.

The invention relates to the field of computing means, and more particularly to microprocessors. A device for controlling the computing devices of a neural network inference accelerator contains the following elements disposed on a chip: a parameter configuration unit connected to an external control device; a segmented buffer memory connected to an external memory; at least two units for processing instruction streams, each of which is configured to be capable of buffering a stream of instructions received from the segmented buffer memory and decoding and synchronizing the instruction stream; a descriptor pointer unit configured to be capable of receiving descriptor pointers from the external control device; a unit for managing requests to read descriptors according to pointers from the descriptor pointer unit; a unit for processing descriptors of an instruction set; an instruction stream scheduler configured to be capable of loading an instruction set and monitoring the fullness of segments of the buffer memory. The invention makes it possible to enhance accelerator performance by reducing the idle time of computing cores.

A water buoy data system stabilizes an offshore vessel. Water buoys sense wind characteristics and water characteristics at a location of the vessel. The water buoys wirelessly transfer data messages that indicate the wind characteristics and water characteristics at the location of the vessel for delivery to a computer system. The computer system receives the data messages wirelessly transferred by the water buoys that indicate the wind characteristics and the water characteristics at the location of the vessel. The computer system determines wave forces based on the wind characteristics and the water characteristics at the location of the vessel. The computer system indicates the wave forces to control vessel engine thrusters to counter the wave forces and stabilize the vessel.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

In a water buoy, a power system generates electrical energy from water kinetics and transfers the electrical energy to a sensor array, processing circuitry, and communication interface. In the water buoy, the sensor array detects buoy locations, water velocities, water velocity directions, and wind speeds. In the water buoy, the processing circuitry aggregates the detected buoy locations, the detected water velocities, the detected water velocity directions, and the detected wind speeds into data messages. In the water buoy, the communication interface wirelessly transfers the data messages for delivery to a computer system.

The invention relates to a chiplet architecture (2) for a technical system (1) comprising the following chiplets (3): - a control unit for system management (4) of the technical system (1), - a hardware accelerator for applications using artificial intelligence (5), - a central processing unit for applications (6) of the technical system (1), - an internal graphics processing unit (7), and - a working memory (8).

A system on chip including: a plurality of processors; a system level cache memory that is shared by the plurality of processors; and a cache controller that transmits first data to another chip if an atomic operation has been performed on the first data, when the system level cache memory receives the first data from at least one of the plurality of processors.

Processing cores having the ability to suppress operations based on estimates of the contributions of those operations to improve overall performance of the core are disclosed. Related methods that can be implemented by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A full execution of the composite computation generates an accurate output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes performing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computations while performing the partial execution based on the evaluation of the component computation approximation with the reference value.

The invention relates to an integrated circuit performing loopback operation and a method of operating the same. An integrated circuit may include first to Nth data receiving circuits configured to receive first to Nth data through first to Nth data terminals based on a multi-phase clock to generate first to Nth multi-phase data, respectively, where N is an integer equal to or greater than 2; first to Nth delay circuits configured to delay first to Nth data having a selected phase among the first to Nth multi-phase data, respectively; a clock delay circuit configured to delay a clock having a selected phase in the multi-phase clock; and a loopback circuit configured to transfer the clock delayed by the clock delay circuit to a loopback clock terminal, and transfer one of the first to Nth data having the selected phase delayed by the first to Nth delay circuits to a loopback data terminal based on the clock delayed by the clock delay circuit.

Systems and methods for automated workflow comprise assigning a set of first targets to an uncompiled first workflow. The uncompiled first workflow specifies a first set of process modules. Each such module is associated with a subset of unit operations. Each unit operation includes a time interval and specifies an instrument. For each target in the set of first targets, the uncompiled workflow is translated into an instance of a compiled first workflow comprising a linear temporal order of unit operations, each including execution instructions for an addressed instrument. A set of second targets is obtained and assigned a second uncompiled workflow. Compilation of the second uncompiled workflow for each second target produces a different instance of a compiled second workflow. Each second compiled workflow comprises a linear temporal order of unit operations, with each unit operation including execution instructions for an addressed instrument and specifying a time interval.

The present disclosure relates to the technical field of computer, and particularly relates to a data acquisition method and device, electronic equipment and storage medium, comprising: in a task starting stage, initializing data is pre-filled into an on-chip cache; when a data read request for a target address is received, if the target address is not hit by a query, and the requested data belongs to the initializing data stored in the on-chip cache, the initializing data corresponding to the target address pre-filled in the on-chip cache is returned as response data. According to the embodiment of the present disclosure, the dependence on off-chip memory can be significantly reduced, the delay of data processing is reduced, and the performance of GPU is improved.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

The application relates to a cache architecture optimization method, device and storage medium of a multi-core particle integrated system, wherein the cache architecture optimization method of the multi-core particle integrated system comprises the following steps: acquiring an architecture topology graph of the multi-core particle integrated system; the architecture topology graph comprises a storage hierarchy graph and a network topology graph; the storage hierarchy graph is a hierarchical connection graph of a cache subsystem of the multi-core particle integrated system; the network topology graph is a core particle connection graph of the multi-core particle integrated system; based on the architecture topology graph, a system performance model is constructed; the system performance model is solved to obtain target cache parameters, and based on the target cache parameters and the storage hierarchy graph, a target cache architecture graph is generated. Through the application, the problem that the architecture of the cache subsystem in the multi-core particle integrated system is difficult to achieve optimal optimization is solved.

A distributed compute system may include a plurality of compute nodes located in geographically distributed sites. A data processing task is performed in a distributed manner among the plurality of compute nodes. The distributed compute system may include a first power management unit located in a first site of the geographically distributed sites. The first site consumes electrical power for both a first compute nodes of the plurality of compute nodes and for a non-data processing load. The first power management unit monitors power consumption at the first site. An allocation of the data processing task to the first compute node is controlled at least partially based on power consumption at the first site monitored by the first power management unit.

The invention relates to a method for generating a task-specific adapted topology for circuit quantum electrodynamics (cQED)-based hardware, characterized in that it comprises the iterative steps of: - determining an error made by a circuit initially obtained by transpiling an agnostic M qubit generated from a client task, - comparing said transpiled circuit error to an error threshold corresponding to said circuit of agnostic M qubits, - if said transpiled circuit error is greater than said error threshold, modifying certain of said hardware specifications to be addressed in the transpilation step, - if said transpiled circuit error is less than said error threshold, providing said transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit. Figure to be published with the abstract: Fig. 1

A data transmission device, a data transmission method, an electronic device and a storage medium. The data transmission device comprises an analysis module, a plurality of distribution modules corresponding to a plurality of request devices respectively, and a plurality of forwarding modules corresponding to a plurality of receiving devices respectively. The analysis module is configured to receive at least one request sent by each request device, analyze the transmission type corresponding to the request for each request, and send the request to the corresponding distribution module. Each distribution module is configured to respond to the request sent by the analysis module, send the request to one or more of the plurality of forwarding modules according to the transmission type corresponding to the request. Each forwarding module is configured to respond to the request sent by the distribution module and send the request to the corresponding receiving device.

The invention discloses a multi-core chip, a calculation method, electronic equipment and a storage medium. The multi-core chip comprises a plurality of computing cores, the plurality of computing cores comprise a first computing core and a second computing core, and the first computing core is in communication connection with the second computing core and is a downstream computing core of the second computing core. And the second calculation core is configured to provide data corresponding to a first data pulling request to the first calculation core in response to receiving the first data pulling request sent by the first calculation core and storing the data corresponding to the first data pulling request. According to the multi-core chip, the resource utilization rate of a multi-core storage and calculation integrated system can be improved, a production line is free of cavitation bubbles, off-chip access and storage are efficiently connected, and efficient parallel calculation is achieved.

A computer-implemented method includes receiving, by a computing device, input activations and determining, by a controller of the computing device, whether each of the input activations has either a zero value or a non-zero value. The method further includes storing, in a memory bank of the computing device, at least one of the input activations. Storing the at least one input activation includes generating an index comprising one or more memory address locations that have input activation values that are non-zero values. The method still further includes providing, by the controller and from the memory bank, at least one input activation onto a data bus that is accessible by one or more units of a computational array. The activations are provided, at least in part, from a memory address location associated with the index.

The invention discloses an InfiDeck artificial intelligence operating system and extended hardware equipment thereof. The system comprises a power management module, an AI calculation module, an edge learning manager, a privacy and data management module, an inference engine and adapter management module, a knowledge index and model warehouse module and a communication interface module. Dynamic power consumption adjustment is achieved through SoC / temperature / idle degree ternary gating, low-bit mixed precision operation is processed, and strategies such as a charging trigger continuous learning mechanism, a self-playback learning mechanism, a model compression self-adjustment system and privacy and energy consumption cooperative control are set. A portable device capable of locally completing personalized AI training and reasoning is provided, and the problems of energy consumption, temperature and privacy security are solved at the same time.

The invention relates to a processor and a cache writing method. The invention discloses a specially designed first-level data cache in a processor core. An arbiter is used to couple a first write interface and a second write interface of the first-level data cache. The arbiter obtains a first write-in data of a first write-in request and a second write-in data of a second write-in request from the first write-in interface and the second write-in interface respectively in the same unit cycle. The arbiter further combines the first write-in data and the second write-in data into fused data. Write-in wires are connected between the arbiter and all cache stacks of the first-level data cache and used for transmitting the fused data. Therefore, transmission of the first write-in data and the second write-in data shares routing, and routing optimization of the first-level data cache is achieved.

The invention provides a local cache synchronization method and device, equipment and a storage medium, and relates to the technical field of computers. The method includes creating a message queue on a message queue node in response to initiation of a first service. And under the condition that the data in the first local cache managed by the first service is updated, a cache updating message is sent to the message queue node through the message queue, and the cache updating message is used for indicating the data updating content in the first local cache. And the second service receives the cache update message through the message queue, the second service is deployed at the first computing node, or the second service is deployed at a second computing node in the distributed system. And the second service updates a second local cache managed by the second service according to the cache update message.