66results about "General purpose stored program computer" patented technology

The invention belongs to the technical field of computers and artificial intelligence, and discloses a priority differential cache-based MoE batch reasoning method and system, and the method comprises the steps: recognizing global hot experts with higher activation frequency in each layer, enabling the global hot experts to remain in a high-priority cache during initialization, and building a priority list of the experts in each layer; in the reasoning stage, selecting an expert set needing to be activated in the current layer; the expert priority score is dynamically updated according to the activation and reuse behaviors of the experts, and the experts are migrated and replaced among the high-level cache, the middle-level cache and the low-level cache according to the priority score and a cache threshold value; according to a current layer gating result and a historical activation track, predicting an expert set which may be activated in a next layer, and asynchronously loading the expert set to a low-priority cache during current layer calculation so as to realize time overlapping of calculation and communication. According to the method, the expert migration frequency can be reduced, the cache hit rate and the throughput rate are improved, the video memory utilization rate is remarkably optimized, and good expansibility and universality are achieved.

The invention relates to an intelligent decision-making method and system for server customization demand matching. The method comprises the steps of obtaining a server customization demand input by a user; constructing a multi-dimensional demand portrait based on the server customization demand, wherein the demand portrait comprises a quantitative index and a configuration constraint condition; according to the demand portrait, executing configuration compatibility check, and identifying whether a compatibility problem exists or not; when the compatibility check is passed, a candidate configuration scheme is generated by adopting a multi-target genetic algorithm based on the demand portrait passing the compatibility check; and sorting and screening the candidate configuration schemes based on user preference data in the demand portraits passing the compatibility check to obtain a recommended scheme list, and transmitting the recommended scheme list to a display interface for a user to select and confirm, the recommended scheme comprising a component list, a price, a performance index and a recommendation reason. The method has the effect of improving the accuracy of server customization recommendation.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

To provide a method for executing machine learning calculation using a calculation unit of special purpose, a storage device and an electronic system.SOLUTION: In a method by a computing device, a controller at least partially receives input activations provided from a memory address position associated with an index, determines whether or each of the input activations has either a zero value or a non-zero value, stores at least the one input activation in a memory bank and generates an index including the one or more memory address positions having the input activation value that is the non-zero value, broadcasts at least the one input activation on a data bus accessible by the one or more units among calculation arrays from the memory bank, detects the broadcast, and provides a control signal for preventing multiplication operation associated with zero input to at least the one unit among the calculation arrays.SELECTED DRAWING: Figure 5

Water buoys sense water characteristics and wirelessly transfer the water characteristics for delivery to a computer system. The computer system receives the water characteristics wirelessly transferred by the water buoys. The computer system receives a location and a user water condition preference transferred by a user communication device. The computer system processes the water characteristics, the location, and the user water condition preference, and in response, generates and transfers water condition information for the location for delivery to the user communication device.

The invention relates to a computer architecture (110) enabling data transfer between several functional units. A functional unit supply structure (111) provides several functional units. A selection structure (112) provides a selection of functional units and linking information, the selected functional units being linked to perform predefined data processing. An interface structure (113) provides an interface for data transfer between linked selected functional units, this interface being designed to transform at least a portion of the output data content of the selected functional unit into input data of the other functional unit, according to the selected functional units and the linking information. [Abstract figure] Fig. 1

Disclosed in the embodiments of the present disclosure are a communication method inside a chip, an apparatus, a chip, a storage medium and a program product. The communication method inside a chip comprises: when a sender transmits target data to a receiver, determining from a memory of a target chip at least one target cache area corresponding to the sender and capable of storing the target data; and, on the basis of a preset communication protocol, writing the target data into the at least one target cache area according to a preset storage format, the preset storage format comprising a cache area guidance used for indicating the next cache area.

The application provides a message notification method and device, which can solve the problem that a plurality of query commands need to be sent by software of a main chip to know the command execution state of a flash memory, reduces the additional software overhead, and is suitable for the case that the logic circuit of the main chip initiatively sends a sleep request to the flash memory. The message notification method comprises that the flash memory receives a first sleep request from the main chip. The flash memory detects the execution state of a work command initiated by the flash memory. The work command is used to initiate a read / write operation between the flash memory and the main chip. The flash memory sends a first notification to the main chip, and the first notification is used to indicate the execution state of the work command.

The application discloses a multi-task execution method, device, equipment and medium, and belongs to the technical field of power electronics. The method comprises the following steps: setting independent threads for each operation task in an IEC61131-3 multi-operation task in advance; setting a task priority list for each operation task in the IEC61131-3 multi-operation task, and setting a target reference list according to the data calling relationship of each operation task; and sending the task priority list and the target reference list to a programmable logic controller, so that the programmable logic controller controls each operation task in the IEC61131-3 multi-operation task according to the task priority list and the target reference list. By using the method, the programmable logic controller can execute each operation task in the IEC61131-3 multi-operation task without being affected by other operation tasks, and the CPU load is more stable.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

The utility model provides a configurable interface expansion module based on an FPGA (Field Programmable Gate Array). The configurable interface expansion module comprises an FPGA chip; the expansion interface module is arranged on one side of the FPGA chip, a configuration control module is arranged on one side of the expansion interface module, and a data bus control module is arranged on one side of the configuration control module. According to the FPGA-based configurable interface expansion module provided by the utility model, two FPGA chips are integrated on an FPGA board, an FPGA interconnection line between the two FPGA chips provides bandwidth, and a bus transmits data at the same time, so that a simple and configurable mode is provided for a user to utilize a multi-FPGA chip system, and the FPGA-based configurable interface expansion module has relatively high performance; in addition, the FPGA board can be connected with peripheral equipment through the expansion interface module, multi-board connection can also be achieved through the expansion interface module, interference among multiple structures is small, and various choices are provided for users.

Systems and methods for automated workflow comprise assigning a set of first targets to an uncompiled first workflow. The uncompiled first workflow specifies a first set of process modules. Each such module is associated with a subset of unit operations. Each unit operation includes a time interval and specifies an instrument. For each target in the set of first targets, the uncompiled workflow is translated into an instance of a compiled first workflow comprising a linear temporal order of unit operations, each including execution instructions for an addressed instrument. A set of second targets is obtained and assigned a second uncompiled workflow. Compilation of the second uncompiled workflow for each second target produces a different instance of a compiled second workflow. Each second compiled workflow comprises a linear temporal order of unit operations, with each unit operation including execution instructions for an addressed instrument and specifying a time interval.

A system, method, and computer-program product includes obtaining a set of compute architecture design parameters associated with a target subscriber, generating a HPC architecture data object for the target subscriber that satisfies the set of compute architecture design parameters, executing, in real-time or near real-time, one or more automated pairwise assessments between the HPC architecture data object generated for the target subscriber and a reference HPC architecture data object, computing, in real-time or near real-time, a percent of potential value that indicates a degree of performance disparity between the HPC architecture data object generated for the target subscriber and the reference HPC architecture data object based on pairwise assessment findings outputted by the one or more automated pairwise assessments, and constructing, for the target subscriber, an optimal HPC environment corresponding to the HPC architecture data object when the percent of potential value satisfies a predetermined minimum score threshold value.

The utility model discloses a miniaturized high-speed signal processing SiP integrated device, which belongs to the technical field of electronics and comprises a broadband high-speed signal processing SiP micro module, a power conversion module, a clock generation and distribution module, an ADC / DAC front-end module, a photoelectric conversion module and a data input / output interface module. The broadband high-speed signal processing SiP micromodule comprises a clock input port, a digital-analog / analog-digital converter, an FPGA (Field Programmable Gate Array), a FLASH, a GTH interface and an IO (Input / Output) interface. According to the utility model, the integration density of traditional signal processing hardware is improved, miniaturization, standardization and modularization of high-speed signal processing hardware are realized, unmanned and lightweight development requirements of equipment in the field of communication and radar electronic countermeasure can be met, and the high engineering application value is realized.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The application discloses a nuclear power KRTN16 channel in-situ processor hardware integrated system and a hot switching method, which comprises a total power supply, a main power supply, a backup power supply, a normal channel switch, a backup channel switch, a switching execution unit, a switching control unit, a mainboard card and a backup board card. The total power supply is connected with the input end of the normal channel switch and the input end of the backup channel switch. The main power supply is connected with the output end of the normal channel switch and the input end of the mainboard card. The control signal output end of the mainboard card and the control signal output end of the backup board card are connected with the input end of the switching control unit. The output end of the switching control unit is connected with the input end of the switching execution unit. The output end of the switching execution unit is connected with the execution signal input end of the normal channel switch and the execution signal input end of the backup channel switch. The output end of the backup channel switch is connected with the input end of the backup board card through the backup power supply. The application can realize hot switching quickly.

Various Data Subject Access Request (DSAR) processing systems are adapted for presenting a first webform on a first web site, the first webform being adapted to receive DSAR's and to route the requests to a first designated individual for processing; presenting a second webform on a second web site, the second webform being adapted to receive DSAR's and to route the requests to a second designated individual for processing; receiving, via the first webform, a first DSAR; at least partially in response to the receiving the first DSAR, automatically routing the first DSAR to the first designated individual for handling; receiving, via the second webform, a second DSAR; at least partially in response to the receiving the second DSAR, automatically routing the second DSAR to the second designated individual for handling; and communicating a status of both the first DSAR and the second DSAR via a single user interface.

Computer computing device with memory optimized for matrix calculation. Computer computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a loading circuit (114) comprising: - an indexed loading block (116) having a secondary memory (118) and a FIFO query memory (120) for sending values ​​stored in the secondary memory to the computing unit; - an indexed loading engine (122) configured to sequentially generate and store the queries in the FIFO query memory in an order in which the values ​​are intended to be sent to the computing unit;the order in which queries are stored is calculated and stored in the form of a microprogram (124). Figure for the abbreviation: Fig. 1;

A data transmission apparatus, a data transmission method, an electronic device and a storage medium. The data transmission apparatus (210) comprises a parsing module (211), a plurality of distribution modules (212), which respectively correspond to a plurality of requesting apparatuses (220), and a plurality of forwarding modules (213), which respectively correspond to a plurality of receiving apparatuses (230), wherein the parsing module (211) is configured to receive at least one request, which is sent by each requesting apparatus (220), perform parsing on each request to obtain a transmission type corresponding to the request, and send the request to a corresponding distribution module (212); each distribution module (212) is configured to send, in response to receiving a request which is sent by the parsing module (211), the request to one or more of the plurality of forwarding modules (213) on the basis of the transmission type corresponding to the request; and each forwarding module (213) is configured to send, in response to receiving a request which is sent by a distribution module (212), the request to a corresponding receiving apparatus (230).

Systems and methods described herein can involve a customizable application framework that allows for fast implementation and efficient application of functional neural network architectures, ease of use, shareability, and reproducibility of results. The application framework improves model performance by capturing underlying complex functions and non-linear relationship information in time series data to solve time series analysis tasks.

The invention relates to the field of computing means, and more particularly to microprocessors. A device for controlling the computing devices of a neural network inference accelerator contains the following elements disposed on a chip: a parameter configuration unit connected to an external control device; a segmented buffer memory connected to an external memory; at least two units for processing instruction streams, each of which is configured to be capable of buffering a stream of instructions received from the segmented buffer memory and decoding and synchronizing the instruction stream; a descriptor pointer unit configured to be capable of receiving descriptor pointers from the external control device; a unit for managing requests to read descriptors according to pointers from the descriptor pointer unit; a unit for processing descriptors of an instruction set; an instruction stream scheduler configured to be capable of loading an instruction set and monitoring the fullness of segments of the buffer memory. The invention makes it possible to enhance accelerator performance by reducing the idle time of computing cores.

The invention provides a system conversion method and device based on a dynamic mapping rule, and belongs to the technical field of computer systems. According to the system conversion method based on the dynamic mapping rule, the binary data set is dynamically converted into the ternary data sets in parallel by adopting the preset compression code table and the bit parallel conversion logic, so that the storage cost and hardware resource occupation are remarkably reduced, and the storage efficiency is improved. The efficient, flexible and reliable large-scale binary-to-ternary data conversion is realized, the conversion time is greatly shortened, and the conversion throughput is improved.

A water buoy data system stabilizes an offshore vessel. Water buoys sense wind characteristics and water characteristics at a location of the vessel. The water buoys wirelessly transfer data messages that indicate the wind characteristics and water characteristics at the location of the vessel for delivery to a computer system. The computer system receives the data messages wirelessly transferred by the water buoys that indicate the wind characteristics and the water characteristics at the location of the vessel. The computer system determines wave forces based on the wind characteristics and the water characteristics at the location of the vessel. The computer system indicates the wave forces to control vessel engine thrusters to counter the wave forces and stabilize the vessel.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

In a water buoy, a power system generates electrical energy from water kinetics and transfers the electrical energy to a sensor array, processing circuitry, and communication interface. In the water buoy, the sensor array detects buoy locations, water velocities, water velocity directions, and wind speeds. In the water buoy, the processing circuitry aggregates the detected buoy locations, the detected water velocities, the detected water velocity directions, and the detected wind speeds into data messages. In the water buoy, the communication interface wirelessly transfers the data messages for delivery to a computer system.

The invention relates to a chiplet architecture (2) for a technical system (1) comprising the following chiplets (3): - a control unit for system management (4) of the technical system (1), - a hardware accelerator for applications using artificial intelligence (5), - a central processing unit for applications (6) of the technical system (1), - an internal graphics processing unit (7), and - a working memory (8).

A system on chip including: a plurality of processors; a system level cache memory that is shared by the plurality of processors; and a cache controller that transmits first data to another chip if an atomic operation has been performed on the first data, when the system level cache memory receives the first data from at least one of the plurality of processors.

Processing cores having the ability to suppress operations based on estimates of the contributions of those operations to improve overall performance of the core are disclosed. Related methods that can be implemented by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A full execution of the composite computation generates an accurate output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes performing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computations while performing the partial execution based on the evaluation of the component computation approximation with the reference value.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.