145results about "General purpose stored program computer" patented technology

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention relates to a cache architecture optimization method and device for a multi-chip integration system and a storage medium, and the method comprises the steps: obtaining an architecture topological graph of the multi-chip integration system; the architecture topological graph comprises a storage hierarchy graph and a network topological graph; the storage hierarchy graph is a hierarchy connection graph of a cache subsystem of the multi-chip integration system; the network topological graph is a core particle connection graph of the multi-core particle integrated system; constructing a system performance model based on the architecture topological graph; and solving the system performance model to obtain a target cache parameter, and generating a target cache architecture graph based on the target cache parameter and the storage hierarchy graph. According to the method and the device, the problem that the architecture of the cache subsystem in the multi-chip particle integrated system is difficult to achieve optimal optimization is solved.

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.

The present application relates to the technical field of storage application, and discloses a physical address query method, a flash memory device controller and a flash memory device. The physical address query method comprises: acquiring a logical address; by querying a compact array, determining whether the compact array can map the logical address to a corresponding physical address; if the compact array cannot map the logical address to the corresponding physical address, querying a range bucket hash structure to determine whether a range bucket node corresponding to the logical address exists in a least recently used cache; and if the range bucket node corresponding to the logical address exists in the least recently used cache, querying the logical address from the range bucket node to obtain the physical address corresponding to the logical address. By querying from the compact array and the range bucket hash structure the physical address corresponding to the logical address, the present application can save DRAM resources and also maintain high indexing performance, thereby improving the query efficiency of the physical address.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention belongs to the technical field of computers and artificial intelligence, and discloses a priority differential cache-based MoE batch reasoning method and system, and the method comprises the steps: recognizing global hot experts with higher activation frequency in each layer, enabling the global hot experts to remain in a high-priority cache during initialization, and building a priority list of the experts in each layer; in the reasoning stage, selecting an expert set needing to be activated in the current layer; the expert priority score is dynamically updated according to the activation and reuse behaviors of the experts, and the experts are migrated and replaced among the high-level cache, the middle-level cache and the low-level cache according to the priority score and a cache threshold value; according to a current layer gating result and a historical activation track, predicting an expert set which may be activated in a next layer, and asynchronously loading the expert set to a low-priority cache during current layer calculation so as to realize time overlapping of calculation and communication. According to the method, the expert migration frequency can be reduced, the cache hit rate and the throughput rate are improved, the video memory utilization rate is remarkably optimized, and good expansibility and universality are achieved.

In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain embodiments, a cluster node module is configured to communicate with the kernel and other cluster node modules. The cluster node module can accept instructions from the user interface and can interpret at least some of the instructions such that several cluster node modules in communication with one another and with a kernel can act as a computer cluster.

The invention relates to an intelligent decision-making method and system for server customization demand matching. The method comprises the steps of obtaining a server customization demand input by a user; constructing a multi-dimensional demand portrait based on the server customization demand, wherein the demand portrait comprises a quantitative index and a configuration constraint condition; according to the demand portrait, executing configuration compatibility check, and identifying whether a compatibility problem exists or not; when the compatibility check is passed, a candidate configuration scheme is generated by adopting a multi-target genetic algorithm based on the demand portrait passing the compatibility check; and sorting and screening the candidate configuration schemes based on user preference data in the demand portraits passing the compatibility check to obtain a recommended scheme list, and transmitting the recommended scheme list to a display interface for a user to select and confirm, the recommended scheme comprising a component list, a price, a performance index and a recommendation reason. The method has the effect of improving the accuracy of server customization recommendation.

An inter-chip timing synchronization method comprising: for each pair of chips in a plurality of chips of a semiconductor device: determining a first one-way latency for transmissions from a first chip in the pair to a second chip in the pair of chips, and determining a second one-way latency for transmissions from the second chip in the pair to the first chip in the pair of chips; receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of chips; determining, by the semiconductor device driver and from the respective first one-way latency and the second one-way latency for each pair of chips, a loop latency between each pair of chips; adjusting, by the semiconductor device driver and for at least one pair of chips, a local counter of the second chip in the at least one pair of chips based on a characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of chips.

A neural network device including an on-chip buffer memory that stores an input feature map of a first layer of a neural network, a computational circuit that receives the input feature map of the first layer through a single port of the on-chip buffer memory and performs a neural network operation on the input feature map of the first layer to output an output feature map of the first layer corresponding to the input feature map of the first layer, and a controller that transmits the output feature map of the first layer to the on-chip buffer memory through the single port to store the output feature map of the first layer and the input feature map of the first layer together in the on-chip buffer memory.

Data processing systems and methods, according to various embodiments, are adapted for determining an applicable privacy policy based on various criteria associated with a user and the associated product or service. User and product criteria may be obtained automatically and / or based on user input and analyzed by a privacy policy rules engine to determine the applicable policy. Text from the applicable policy can then be presented to the user. A default policy can be used when no particular applicable policy can be identified using by the rules engine. Policies may be ranked or prioritized so that a policy can be selected in the event the rules engine identifies two, conflicting policies based on the criteria.

A method includes translating an instruction, received via a network interface, from a home control system to a command for an architectural covering. The method further includes transmitting the command to the architectural covering via a wireless covering interface. The method further includes estimating a position of a covering of the architectural covering. The method further includes transmitting the position to the home control system.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

To provide a method for executing machine learning calculation using a calculation unit of special purpose, a storage device and an electronic system.SOLUTION: In a method by a computing device, a controller at least partially receives input activations provided from a memory address position associated with an index, determines whether or each of the input activations has either a zero value or a non-zero value, stores at least the one input activation in a memory bank and generates an index including the one or more memory address positions having the input activation value that is the non-zero value, broadcasts at least the one input activation on a data bus accessible by the one or more units among calculation arrays from the memory bank, detects the broadcast, and provides a control signal for preventing multiplication operation associated with zero input to at least the one unit among the calculation arrays.SELECTED DRAWING: Figure 5

Multifunctional electronic component, device, method and corresponding programs. The invention relates to an electronic data processing platform, comprising a general-purpose processor (PS) and a so-called level 1 memory (L1). This platform further comprises a programmable logic component (PL) comprising a so-called level 0 memory (L0), the programmable logic component being configured so as to define typologies of executable calculations, said platform further comprising orchestration software running on the general-purpose processor, the orchestration software being responsible for providing, to the programmable logic component, a set of configuration data for its execution within the limits of the typologies of executable calculations. Abstract figure: Figure 5

The present invention discloses an intelligent Android integrated basic control box, comprising a chassis and a cover, wherein two ends of the bottom of the chassis are provided with slide grooves, the interior of the slide grooves is connected with a bracket, the bracket is fixed to the chassis by a first screw, wherein a mounting hole is provided at the bottom end of the bracket, a card plate is provided at the top edge of the chassis, a card slot is provided inside the card plate, the cover is connected to the card slot inside the card plate, a fixing plate is provided at one side edge of the cover, and the fixing plate is connected to a groove on one side of the chassis. The intelligent Android integrated basic control box, when it is necessary to clean the heat sink for ventilation and heat dissipation inside the chassis, the knob on the threaded column is turned so that the knob is removed from the threaded column, and then the heat sink in the through hole is pushed from the side of the chassis so that the heat sink is removed along the threaded column, thereby facilitating the cleaning of the heat sink blocked by the ventilation holes.

Water buoys sense water characteristics and wirelessly transfer the water characteristics for delivery to a computer system. The computer system receives the water characteristics wirelessly transferred by the water buoys. The computer system receives a location and a user water condition preference transferred by a user communication device. The computer system processes the water characteristics, the location, and the user water condition preference, and in response, generates and transfers water condition information for the location for delivery to the user communication device.

The utility model discloses a development board based on an ESP32 chip, and the development board comprises a main control module which comprises an ESP32-S3-R8 chip and an onboard FLASH chip; the ESP32-S3-R8 chip is used for providing a storage space of the 8MBPSRAM; the onboard FLASH chip is used for providing a 16MBFLASH storage space; the onboard FLASH chip is electrically connected with the ESP32-S3-R8 chip, and the ESP32-S3-R8 chip The SPACE-S3 development board has the beneficial effects that the SPACE-S3 development board is high in integration level and small in size, can be used as a development board, can also be used as a core board of a minimum system, can be selectively provided with a screen, is fully led out and is suitable for various application development.

The invention relates to a computer architecture (110) enabling data transfer between several functional units. A functional unit supply structure (111) provides several functional units. A selection structure (112) provides a selection of functional units and linking information, the selected functional units being linked to perform predefined data processing. An interface structure (113) provides an interface for data transfer between linked selected functional units, this interface being designed to transform at least a portion of the output data content of the selected functional unit into input data of the other functional unit, according to the selected functional units and the linking information. [Abstract figure] Fig. 1

A method and system that utilizes a metagraph pattern matching chip (MPMC), which includes on-chip and off-chip software. The chip is designed with parallel MIMD cores optimized for artificial general intelligence (AGI) software programs. Specialized on-chip memory caches, each attached to their own specialized processing units, allow for dynamic updating and a mixture of discrete and floating-point operations. Additional software provides the interface between the CPU and MPMC to manage cache. The result is faster execution time for any graph-based architectures and implementation of functional programming interpreters.

Disclosed in the embodiments of the present disclosure are a communication method inside a chip, an apparatus, a chip, a storage medium and a program product. The communication method inside a chip comprises: when a sender transmits target data to a receiver, determining from a memory of a target chip at least one target cache area corresponding to the sender and capable of storing the target data; and, on the basis of a preset communication protocol, writing the target data into the at least one target cache area according to a preset storage format, the preset storage format comprising a cache area guidance used for indicating the next cache area.

The application provides a message notification method and device, which can solve the problem that a plurality of query commands need to be sent by software of a main chip to know the command execution state of a flash memory, reduces the additional software overhead, and is suitable for the case that the logic circuit of the main chip initiatively sends a sleep request to the flash memory. The message notification method comprises that the flash memory receives a first sleep request from the main chip. The flash memory detects the execution state of a work command initiated by the flash memory. The work command is used to initiate a read / write operation between the flash memory and the main chip. The flash memory sends a first notification to the main chip, and the first notification is used to indicate the execution state of the work command.

System and methods are disclosed to perform operations including communicatively coupling a plurality of client devices that are accessible by a user to enable the user to communicate with the processor. Receiving a first set of information associated with a user and a second set of information associated with financial advisors as a function of the first set of information. Matching a user with a financial advisor and generating performance metrics with the selected financial advisor to train the matching algorithm to modify the financial advisor information as a function of the performance metrics.

The application discloses a multi-task execution method, device, equipment and medium, and belongs to the technical field of power electronics. The method comprises the following steps: setting independent threads for each operation task in an IEC61131-3 multi-operation task in advance; setting a task priority list for each operation task in the IEC61131-3 multi-operation task, and setting a target reference list according to the data calling relationship of each operation task; and sending the task priority list and the target reference list to a programmable logic controller, so that the programmable logic controller controls each operation task in the IEC61131-3 multi-operation task according to the task priority list and the target reference list. By using the method, the programmable logic controller can execute each operation task in the IEC61131-3 multi-operation task without being affected by other operation tasks, and the CPU load is more stable.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

The utility model provides a configurable interface expansion module based on an FPGA (Field Programmable Gate Array). The configurable interface expansion module comprises an FPGA chip; the expansion interface module is arranged on one side of the FPGA chip, a configuration control module is arranged on one side of the expansion interface module, and a data bus control module is arranged on one side of the configuration control module. According to the FPGA-based configurable interface expansion module provided by the utility model, two FPGA chips are integrated on an FPGA board, an FPGA interconnection line between the two FPGA chips provides bandwidth, and a bus transmits data at the same time, so that a simple and configurable mode is provided for a user to utilize a multi-FPGA chip system, and the FPGA-based configurable interface expansion module has relatively high performance; in addition, the FPGA board can be connected with peripheral equipment through the expansion interface module, multi-board connection can also be achieved through the expansion interface module, interference among multiple structures is small, and various choices are provided for users.

Systems, methods, and apparatuses for accelerating streaming data-transformation operations are described. In one example, an execution circuit executes a decoded instruction to generate and send a single descriptor to an accelerator circuit, comprising a work dispatcher circuit and one or more work execution circuits, to: when a field of the single descriptor is a first value, cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits to perform an operation indicated in the single descriptor to generate an output, and when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform the operation indicated in the single descriptor to generate the output as a single stream.