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190 results about "Multi-core processor" patented technology

A multi-core processor is a computer processor integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions, as if the computer had several processors. The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that don't even share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.

Power consumption and performance balanced scheduling method and system for heterogeneous multi-core processor

The invention discloses a power consumption and performance balanced scheduling method and system for a heterogeneous multi-core processor, and belongs to the technical field of computers, and the method comprises the steps: obtaining historical load data and current system state parameters, generating a load sequence and carrying out load prediction analysis, generating a predicted load value for feature fusion and quantification, and generating a task feature vector; constructing a core capability portrait, calculating a matching degree between the task characteristic vector and the core capability portrait, and generating a scheduling strategy; and dynamically combining the physical cores into a logic calculation unit according to a scheduling strategy, configuring a power consumption state, and executing task allocation and migration. According to the method, the technical means of load prediction analysis, quantitative matching of tasks and cores and dynamic combination and configuration of physical cores are adopted, and pre-judgment and prospective distribution of system resources can be achieved, so that performance requirements are met, meanwhile, the system energy efficiency is effectively optimized, and deep balance of power consumption and performance of a processor is achieved.
Owner:BING TANG INTELLIGENT TECH (SHANGHAI) CO LTD

Chip simulation verification acceleration method and device, equipment and storage medium

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

Method for inter-core communication mode of multi-core processor

The invention provides a method of an inter-core communication mode of a multi-core processor, which comprises the following steps of: S1, determining a processor module partition, performing inter-partition communication initialization, and configuring a corresponding virtual partition, a virtual port and a corresponding driving program; s2, calling an interface program for communication between corresponding partitions in each partition application needing communication; s3, providing a corresponding communication service by the partition application; and S4, when data messages are required to be continuously received in sequence, calling an interface for creating the queue ports, sending messages to a source port in the queue ports through the interface for sending the messages in the partition application, calling the interface in the partition application in the partition needing to receive the messages, and receiving the messages of a destination queue port in sequence. And finally, communication monitoring and maintenance are performed, ID and state information of queues and sampling ports are searched regularly or as required, communication conditions are judged according to results, and if the queues are jammed or no new messages exist in the sampling ports, strategies are adjusted in time, faults are eliminated in time, and stable and efficient communication is ensured.
Owner:SANXIA JINSHAJIANG YUNCHUAN HYDROPOWER DEV CO LTD +1

Data transmission optimization method and system in hybrid deployment of real-time and non-real-time systems based on Jailhouse

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.
Owner:HARBIN INST OF TECH

System-on-chip, system-on-chip configuration method and electronic equipment

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.
Owner:GOWIN SEMICON CORP LTD

Embedded system resource allocation method and system based on hardware virtualization

The invention discloses an embedded system resource allocation method and system based on hardware virtualization. The method comprises the following steps: deploying a Type-1 virtual machine monitor system on a multi-core processor hardware platform supporting virtualization extension; the Type-1 virtual machine monitor carries out virtualization, resource partitioning and security isolation on hardware resources, and creates operation system execution environment'domain 'partitions zoneG and zoneR. A universal operating system is deployed in a zoneG domain partition to take charge of a high-computing-power computing task, and a real-time operating system is deployed in a zoneR to take charge of a real-time computing task. Low-delay inter-core communication between a real-time operating system and a general operating system is realized based on an OpenAMP protocol, and data is transmitted through a shared memory and an interrupt mechanism; according to the requirements of real-time tasks and non-real-time tasks, a Type-1 virtual machine monitor dynamically adjusts a resource allocation strategy, and the priority and deadline of the real-time tasks are ensured.
Owner:NARI INFORMATION & COMM TECH

Instruction-level simulation and performance modeling system for parallel computing architecture

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.
Owner:YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD

Multi-core consistency dynamic synchronization method and system based on RISC-V architecture

The invention is suitable for the field of computer system structures, and provides a multi-core consistency dynamic synchronization method and system based on an RISC-V. The method comprises the steps that the core of a multi-core processor is spatially divided into n consistency domains, each consistency domain is configured with an independent area directory cache and an independent RCC, and transactions in the area are locally processed by the corresponding RCC; when a core in the consistency domain initiates a data operation request, the RCC to which the core belongs checks the state of target data in the consistency domain; according to the data state, the RCC carries out internal synchronization in the consistency domain by adopting an optimized broadcast protocol, or carries out directory type point-to-point communication with other consistency domains through the GDSA to realize cross-domain synchronization; on the premise of ensuring strict consistency, communication delay and energy consumption are remarkably reduced, the overall throughput and expandability of the system are improved, and an efficient consistency solution idea is provided for the RISC-V multi-core processor.
Owner:SHANDONG UNIV +1

Data cache access method and device of multi-core processor

The invention provides a data cache access method and device of a multi-core processor, and relates to the technical field of computer processors. The method comprises the following steps: accessing a data cache according to an access instruction, and responding to the access instruction to hit access data and write back the access data, or responding to the access instruction to not hit the access data, fetching back-filling data from a memory access failure queue and forwarding the back-filling data to the access queue. Accessing the data cache according to the data storage instruction, writing the stored data into the data cache in response to the access hit of the data cache, or calling a stored data retransmission unit in response to the access miss of the data cache; and sending a data storage failure request to the memory access failure queue, and taking back the backfill data and / or authority by the memory access failure queue. According to the method, the flexibility of the processing mode of the data cache access pipeline on the memory access instruction and the external consistency request can be improved, the access parallelism degree is improved, and the hardware resource utilization rate of the processor is increased.
Owner:BEIJING VCORE TECH CO LTD

Multi-core processor dynamic regulation and control method and system based on load and temperature sensing

The invention discloses a multi-core processor dynamic regulation and control method and system based on load and temperature sensing, and relates to the technical field of temperature control scheduling management, and the method comprises the steps: collecting and preprocessing load and temperature data in real time, and building a thermal sensing model to predict the temperature change; constructing a self-adaptive heuristic scheduling algorithm, and adjusting task distribution according to real-time data of the core load and the temperature; according to the load and temperature states, a dynamic voltage frequency adjustment strategy is adopted, and the frequency and the voltage are automatically adjusted when the load and the temperature are too high; and when the load and the temperature exceed set threshold values, a scheduling algorithm is optimized by adopting a self-learning mechanism, and a scheduling strategy and a temperature control scheme are automatically adjusted. According to the method, a more flexible and accurate dynamic regulation and control scheme is provided, the stability and high efficiency of the processor in a high-load and high-temperature environment can be ensured, performance reduction and hardware damage are avoided, and the obvious effects of saving energy and improving system stability are achieved.
Owner:KING BEST TECH CO LTD

Microprocessor dynamic power consumption optimization system based on deep learning

The invention discloses a microprocessor dynamic power consumption optimization system based on deep learning, which belongs to the technical field of microprocessor power consumption management, and comprises a working load feature extraction module, a neural network prediction module, a dynamic core distribution module and a particle size power supply management module, the working load feature extraction module extracts feature parameters of calculation intensity, memory access intensity and input and output intensity of an application program in real time through a hardware circuit; the neural network prediction module predicts future power consumption and performance requirements based on a deep reinforcement learning network; the dynamic core distribution module intelligently selects an optimal core combination; the particle size power supply management module independently executes dynamic voltage frequency regulation on each core; according to the invention, accurate power consumption optimization of the heterogeneous multi-core processor is realized through deep coupling and closed-loop cooperation of the four modules, and compared with the prior art, the energy efficiency ratio is improved by more than 40%, and the power consumption prediction error is reduced to be within 5%.
Owner:NANCHANG UNIV

Virtual power plant rapid frequency modulation control system and control method

The invention discloses a virtual power plant rapid frequency modulation control system and control method, and the method comprises the steps: adaptively adjusting a sampling period through a dynamic sampling algorithm based on a sliding window variance; low-delay calculation of high-frequency data is realized by adopting a multi-thread queue communication technology; a multi-core ARM processor running a real-time operating system is used for executing a multi-thread control model, and data acquisition, algorithm control, fault diagnosis and communication tasks are processed in parallel; according to the control algorithm, frequency prediction feedforward signals based on an AI model and SOC state feedback are fused, and dynamic optimization of PID parameters is achieved. According to the method, millisecond-level frequency modulation response can be realized, the instruction response delay is less than 80ms, the frequency adjustment error is less than + / -0.01 Hz, the frequency modulation performance of a virtual power plant and the stability of a power grid are remarkably improved, and meanwhile, the service life of energy storage equipment is prolonged through SOC collaborative optimization. The invention aims to solve the problems of slow response and low precision of the existing frequency modulation technology.
Owner:JIANGSU AURORA YUNNENG NEW ENERGY CO LTD

Electric power meter data real-time analysis and abnormity early warning method based on edge calculation

The invention provides an electric power meter data real-time analysis and abnormity early warning method based on edge calculation, and belongs to the technical field of data analysis and early warning, and the method comprises the steps: collecting the multi-modal data of an electric power meter based on a multi-channel analog-to-digital converter, employing a hardware filter circuit to eliminate high-frequency noise, and obtaining the data of the electric power meter; signal gain self-adaptive adjustment is carried out based on a reconfigurable amplifier; a digital signal processing accelerator is used to carry out Fourier transform on a matrix constructed by the standardized data stream, and a multi-core processor is combined to carry out analysis to generate a feature vector; the method comprises the following steps: acquiring environmental parameters in real time based on an environmental sensor, dynamically adjusting an anomaly detection threshold in combination with a machine learning model trained by historical data, and comparing a feature vector with the dynamic threshold to generate an anomaly signal; the relay control circuit triggers sound-light alarm, the physically isolated communication module sends an early warning instruction to the cloud platform, and meanwhile, the redundant power supply module is started to control the electric power meter to operate continuously. And the efficiency and accuracy of subsequent abnormity early warning are improved.
Owner:SHENZHEN ZHENMEI ELECTRIC POWER TECHNOLOGY CO LTD

Graph convolutional network accelerator and equipment based on dynamic compression and sparse reordering

The invention discloses a graph convolutional network accelerator and equipment based on dynamic compression and sparse reordering, the graph convolutional network accelerator comprises a combination engine, an aggregation engine, a controller and a storage unit, the aggregation engine comprises an ECSR decoder, a scheduler and a plurality of multi-core SIMD processors which are connected in sequence, the ECSR decoder is used for extracting side information from an adjacency matrix represented by a sparse compression format ECSR, the adjacency matrix represented by the sparse compression format ECSR comprises a row pointer array and a column index array, the row pointer array comprises row numbers containing non-zero elements in the adjacency matrix, the column index array stores column position indexes of all rows containing the non-zero elements, and the column position indexes of all the rows containing the non-zero elements are stored in the column index array. The column position index is generated by adopting differential coding and variable byte coding. The method aims at improving the effective data throughput rate and the memory access efficiency of graph convolutional network acceleration, improving the calculation performance during feature updating and accelerating the reasoning process of the graph convolutional network.
Owner:NAT UNIV OF DEFENSE TECH

Server multi-core computing processor load optimization test method, device and equipment and medium

The invention relates to the technical field of server testing, in particular to a server multi-core computing processor load optimization testing method, device and equipment and a medium, and the method comprises the following steps: automatically identifying hardware configuration information of a server; generating a multi-dimensional pressure test plan based on the hardware configuration information; executing the test plan, and monitoring the load rate, the memory bandwidth, the cache hit rate and the I / O performance index of each CPU core in real time; dynamically adjusting a task allocation strategy based on a set load difference threshold to realize task dynamic optimization, and if the difference between the maximum core load rate and the minimum core load rate is monitored to exceed the threshold, triggering a task migration operation; system performance data are collected again, performance indexes before and after optimization are compared and analyzed, and system performance bottlenecks are recognized; and automatically generating a performance test report. The utilization rate and the overall task throughput of the multi-core processor are improved, and the problem that a static task allocation strategy is difficult to adapt to dynamic load changes is solved.
Owner:SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD

System and method for a safety critical operating environment container architecture

A system for providing a safety critical operating environment container architecture, the system including a computing device having a memory communicatively connected to at least one multi-core processor, the memory containing instructions configuring the processer to receive at least a software module to be executed on the at least one multi-core processor, create a separate virtual environment for the at least a software module, wherein creating the virtual environment further includes generating a virtualization layer and allocating a dedicated private static memory space through the virtualization layer, wherein the separate virtual environment includes a dedicated operating system, integrate the at least a software module into the virtual environment by instantiating, the software module into at least one software container, wherein the at least one software container includes a plurality of dedicated software packages and execute the software module on each software container for each virtual environment.
Owner:PARRY LABS LLC

Method of performing atomic memory operations and multicore processor

The present disclosure provides an execution method of an atomic memory operation and a multi-core processor. The method comprises: a first node interacts with a master node to execute the atomic memory operation, wherein the first data is generated after the execution of the atomic memory operation; the first node sends a unique permission read request to the master node; the first node receives the first data returned by the master node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.
Owner:SANECHIPS TECH CO LTD

Magnetic control system based on multi-core DSP and control method thereof

The invention relates to the technical field of magnetic control transformer control, and discloses a magnetic control system based on a multi-core DSP and a control method thereof, and the system comprises a sampling module which is connected with a magnetic control transformer and is used for collecting the electric power parameters of the magnetic control transformer; the main control module is connected with the sampling module and used for receiving the electric power parameters of the magnetic control transformer and generating a control instruction according to the electric power parameters, the main control module is a multi-core DSP processor and comprises a plurality of cores, and each core is used for processing a corresponding task; and the power module is respectively connected with the magnetic control transformer and the main control module and is used for executing corresponding actions according to the control instruction so as to control the magnetic control transformer. Reliability and real-time performance of task processing of the magnetic control system can be improved so that real-time and reliable control of the magnetic control system on the magnetic control transformer can be realized. And through controllable output of the power module, accurate control of the magnetic control transformer is realized.
Owner:STATE GRID BEIJING ELECTRIC POWER CO +2

Cache testing method and device of multi-core processor, electronic equipment and medium

The present disclosure provides a cache test method and device of a multi-core processor, electronic equipment and medium, and relates to the technical field of processors. First, a test stimulus transaction to be executed at the current time is determined, then simulation verification is performed on the to-be-tested module based on the test stimulus transaction, a simulation verification result is obtained, and based on at least one of the cache hit result in the simulation verification result and the execution time of the test stimulus transaction, a first identifier corresponding to the simulation verification result is generated, then based on the memory access address in the simulation verification result and the first identifier, a score board is searched to obtain reference cache data, and finally based on the reference cache data, the cache data in the simulation verification result is checked to obtain a test result of the to-be-tested module.
Owner:BEIJING VCORE TECH CO LTD

A numerical control ethercat master station bandwidth adaptive scheduling and link fault bypass control system and method

PendingCN122640271AFault toleranceData stream
The application provides a numerical control EtherCAT master station bandwidth adaptive scheduling and link fault bypass control system and method, belongs to the numerical control system industrial Ethernet bus control technical field, and the system comprises a heterogeneous multi-core processor, a field programmable gate array, a local bus, a gigabit Ethernet physical layer unit and a storage unit; the heterogeneous multi-core processor contains a high-performance computing core and a low-power control core, is interconnected with the field programmable gate array through the local bus, and executes physically isolated task scheduling; the field programmable gate array solidifies message preprocessing filtering, message hardware shunting, bandwidth clipping and a multi-channel hardware bypass switch array module, each module is cascaded in cooperation according to a data flow direction, message hardware unloading, bandwidth dynamic adjustment and fault bypass topology reconstruction are realized. The application reduces bus cycle jitter, improves bandwidth utilization efficiency and link fault tolerance capability, and is suitable for high-end numerical control machine tool multi-axis linkage control scenes.
Owner:GENERAL TECH GRP MASCH TOOL ENG RES INST CO LTD

Multi-core task scheduling and real-time optimization system, method and device of EDC controller, processor and storage medium thereof

The invention relates to a multi-core task scheduling and real-time optimization system and method of an EDC controller, and belongs to the technical field of automobile chassis control. The system comprises a multi-core processor, a scheduling module, an inter-core communication module and the like. The method comprises the following steps: dividing sensor acquisition, algorithm calculation and actuator control tasks among multiple cores; strictly controlling the time sequence of the acquisition tasks on the first core based on the scheduling table; through an inter-core event notification mechanism, the algorithm task of the second core is triggered by depending on the first core acquisition completion event, and the actuator control task of the first core is triggered by depending on the second core calculation completion event. According to the method, strict and determined time sequence synchronization among multi-core tasks is realized through double constraints of the dispatch table and event driving, the problems of disordered task time sequence and poor multi-core coordination in a traditional mode are effectively solved, and the real-time performance, the control precision and the reliability of a chassis suspension control system are remarkably improved.
Owner:DONGFENG ELECTRONICS TECH

Method and device for verifying memory consistency of multi-core processor

The invention relates to a multi-core processor memory consistency verification method and device, the method is executed by a memory model in a processor co-simulation verification architecture, and the method comprises the following steps: monitoring a storage instruction of each processor core in an RTL, and maintaining a storage queue for each processor core based on the storage instruction; in response to a data request initiated when the ISS executes the loading instruction, speculating a set of compliance values possibly read by the loading instruction based on the storage queue and the visible relation of the storage instructions between the maintained different processor cores; comparing the actual read data of the loading instruction obtained from the RTL with the set of compliance values; and if the actually read data is in the set of compliance values, determining that the memory consistency verification of the multi-core processor is compliant. Therefore, an RISC-V multi-core processor memory consistency verification scheme which can be integrated in a front simulation environment, supports real-time accurate verification and has high coverage is provided.
Owner:CHENGDU QUNXIN MICROELECTRONICS TECHNOLOGY CO LTD

A multi-core cache coherency debugging method based on multi-view access

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.
Owner:58TH RES INST OF CETC

A high dynamic SAR image corner anti-discriminating method

The application discloses a high-dynamic SAR image corner anti-discrimination method, which utilizes a multi-core DSP processor to perform parallel operation, converts high-dynamic M-bit image data to be processed into M / 2-bit image data through power transformation, performs a maximum value searching operation on the M / 2-bit image data after the power transformation, performs target pixel position merging on the pixel maximum value, performs ROI slice segmentation on the merged pixel maximum value, performs ROI processing on the segmented ROI slice, generates an ROI binary graph, calculates a connected region area value in the ROI binary graph, and distinguishes targets and corner anti-discriminations. The application can quickly screen out high-value targets and corner anti-discriminations in a high-dynamic scene, has strong robustness, wide applicability, high automation degree and rapid processing.
Owner:SHANGHAI RADIO EQUIP RES INST

Intelligent driving Linux system multi-mode dynamic adjustment method based on multi-core processor

The invention discloses an intelligent driving Linux system multi-mode dynamic adjustment method based on a multi-core processor, relates to the technical field of intelligent driving, and aims to solve the problems that in existing intelligent driving system multi-core scheduling, calculation power and power consumption are difficult to balance, real-time performance is insufficient, reliability is limited, and performance is reduced due to resource competition. The real-time performance is guaranteed by adopting a Linux system, multi-core distribution is optimized through task CPU affinity configuration, three dynamic switching modes of low power consumption, triple modular redundancy and high performance are designed, and on-demand distribution of computing power, dynamic optimization of power consumption and rapid fault tolerance are realized in combination with a module dependency analysis and partition scheduling strategy. According to the method, the real-time response capability, the endurance performance and the reliability of the intelligent driving system are remarkably improved, the resource waste is reduced, and the method is suitable for various multi-core processor vehicle-mounted intelligent driving platforms.
Owner:DONGFENG MOTOR GRP

Storage controller, read-write method and server

The invention provides a storage controller, a read-write method and a server, which can be applied to the technical field of storage. The storage controller comprises at least one multi-core processor, and each multi-core processor comprises a plurality of processing units which are connected with one another; the at least one multi-core processor is configured to sequentially control a plurality of processing units on a storage access path, receive a data transmission instruction and perform data reading and writing on a disk according to the data transmission instruction; wherein the plurality of processing units on the storage access path are configured to realize ordered communication through the host interaction layer, the cache layer, the redundant array of disks and the disk management layer according to the processing sequence of the data transmission instruction.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD

Method and device for monitoring inclination angle of measuring instrument by fusing vision assistance

The invention discloses a measuring instrument inclination angle monitoring method and device fused with vision assistance, belongs to the technical field of precise instrument measurement, and aims to solve the problem of poor reliability of inclination angle detection of a measuring instrument in the prior art. According to the technical key points, the method comprises the following steps: respectively acquiring an image containing a level gauge and an inclination angle measurement value by using an image sensor module and an inclination angle sensor in an inclination angle detection device fixed on a measuring instrument; a multi-core processor in the dip angle detection device is used for processing images containing the level gauge, bubble position information of the level gauge is extracted, and a dip angle value of the level gauge is obtained according to the bubble position information; and carrying out fusion processing on the dip angle value of the level gauge and the dip angle measurement value to obtain a fused dip angle value, and taking the fused dip angle value as a final dip angle monitoring result of the measuring instrument. The method is suitable for a high-precision measuring instrument with extremely high requirements on the real-time performance and the accuracy of horizontal inclination angle monitoring.
Owner:TIANJIN DAT TRANSDUCER TECH CO LTD

Efficient processing on a dual core processing system

A system may include: a plurality of processing cores including at least a first processing core and a second processing core; a shared memory communicatively coupled to each of the plurality of processing cores, and accessible by each of the plurality of processing cores; a global monitor communicatively coupled to each of the plurality of processing cores and configured to control exclusive access to the memory by each of the plurality of processing cores; and a software architecture embodied in a non-transitory computer readable medium and configured to divide a plurality of processing tasks between the first processing core and the second processing core when read and executed by the multi-core processor.
Owner:CIRRUS LOGIC INT SEMICON LTD

Matrix multiplication task allocation method and device and electronic equipment

The invention provides a matrix multiplication task distribution method and device and electronic equipment, and the method comprises the steps: segmenting a to-be-multiplied matrix into a plurality of data blocks based on the total number of cores of a multi-core processor, and taking the multiplication operation of each pair of data blocks as a task; obtaining core state data of each core in the multi-core processor, wherein the core state data comprises a current load, a historical load fluctuation coefficient and a cache data address; determining a remaining computing power score for each core based on the core state data; a core to execute each task is assigned to each task based on the remaining computing power score. According to the method and the device, a proper execution core can be matched for each task according to the current computing power of each core, so that dynamic load balancing is realized, the bottleneck that part of cores are overloaded while other cores are idle is effectively avoided, the resource utilization rate of a multi-core processor is maximized, and the overall operation efficiency of large-scale matrix multiplication is remarkably improved.
Owner:YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD