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360 results about "Multi-core processor" patented technology

A multi-core processor is a computer processor integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions, as if the computer had several processors. The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that don't even share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.

Intelligent traffic management using reinforcement learning

An intelligent traffic management device for optimizing traffic flow at one or more intersections using reinforcement learning, comprising: a central control unit housed in a weatherproof enclosure and mounted on a structural support near an intersection; a sensor interface operatively connected to a variety of multimodal sensors, including at least radar-based vehicle detectors, inductive loop sensors embedded in the road surface, infrared pedestrian detection detectors, and high-resolution optical imaging modules; a powerful embedded computing unit consisting of a multi-core processor and a GPU configured for on-device inference; a reinforcement learning engine embedded in the computing unit, comprising a deep reinforcement learning model trained to map environmental states defined by traffic-related sensor inputs to optimized action policies for traffic light control; a signal actuation module electrically connected to traffic signal controllers, with action policies outputting signal phase durations and transitions in real time; a communications module supporting wireless connectivity and configured for device-to-device communication and cloud synchronization; a policy synchronization module configured to perform federated learning-based updates of model parameters by exchanging gradient weights or distilled traffic state vectors with neighboring intelligent traffic management devices deployed in a traffic network; where the reinforcement learning engine continuously observes traffic state vectors consisting of vehicle counts, average speeds, queue lengths, and pedestrian activity, and dynamically updates the policy to maximize cumulative traffic throughput and minimize average delay.
Owner:MOHAMMED ABDUL SALAM DR

Dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on RISC-V architecture

The invention relates to a dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on an RISC-V architecture. The method comprises the following steps: 1) initializing a dynamic adjustable multi-core cooperation system; comprising the steps that a hardware module is initialized, and the hardware module comprises a high-performance core P-core, a low-power-consumption core E-core, a hardware scheduling unit HSU and a power management unit PMU; loading a task queue, and marking task characteristics; 2) core state monitoring; comprising the following steps: an HSU monitors a core state; the power management unit PMU monitors voltage and frequency; 3) dynamic task scheduling; comprising the steps that task characteristics are allocated to a high-performance core P-core or a low-power-consumption core E-core; the idle core enters a low-power-consumption mode; and 4) self-adaptive energy saving is realized, and task migration is carried out. And through a dynamic task scheduling and energy-saving optimization algorithm, the flexibility and efficiency of the RISC-V multi-core processor are remarkably improved.
Owner:SHANDONG UNIV

Cooling circulation system of multi-core processor and control method thereof

The invention discloses a control method for a cooling circulation system of a multi-core processor, and relates to the technical field of computer hardware heat dissipation, and the control method comprises the following steps: the multi-core processor is responsible for executing a calculation task; the sensor module monitors the temperature of each core; the cooling system control module is used for receiving data from the temperature sensor and the load monitoring module, calculating the cooling requirement of each core according to the data and commanding a cooling unit to adjust; the cooling unit is used for adjusting cooling equipment to reduce the temperature of the processor according to an instruction of the control unit; and the debugging interface is used for monitoring the state of the system and displaying the temperature, the load and the cooling resource distribution condition of each core. The method has the beneficial effects that the rotating speed of the fan, the liquid cooling flow and the working state of the heat pipe system can be accurately controlled by combining the accurate analysis of the load change and the temperature data, the heat dissipation efficiency of the processor is improved, and the energy waste is reduced.
Owner:KING BEST TECH CO LTD

Cryptocurrency hardware wallet on monolithic chip with common physical countermeasures and secure memory

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.
Owner:CROSSBAR INC

Cache consistency state maintenance method and device, multi-core processor and server

The invention discloses a cache consistency state maintenance method and device, a multi-core processor and a server, and relates to the field of multi-core processors, the method is applied to the multi-core processor, and the method comprises the following steps: a local processor node obtains a local cache consistency maintenance message; wherein the local processor node is any processor node in the multi-core processor; determining a target directory from an exclusive directory and a shared directory according to a cache consistency state of a target cache line corresponding to the local cache consistency maintenance message; wherein the target directory is an exclusive directory or a shared directory; searching a target directory entry from the target directory, and adjusting the target directory entry; according to the method, the cache consistency catalog is divided into the exclusive catalog and the shared catalog, the exclusive catalog is used for recording the exclusive node information of the exclusive data, and the shared catalog is used for recording the shared node information of the shared data, so that the scale and resource occupation of the cache consistency catalog are reduced, and the query speed and efficiency of the catalog are improved.
Owner:SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD

Power consumption and performance balanced scheduling method and system for heterogeneous multi-core processor

The invention discloses a power consumption and performance balanced scheduling method and system for a heterogeneous multi-core processor, and belongs to the technical field of computers, and the method comprises the steps: obtaining historical load data and current system state parameters, generating a load sequence and carrying out load prediction analysis, generating a predicted load value for feature fusion and quantification, and generating a task feature vector; constructing a core capability portrait, calculating a matching degree between the task characteristic vector and the core capability portrait, and generating a scheduling strategy; and dynamically combining the physical cores into a logic calculation unit according to a scheduling strategy, configuring a power consumption state, and executing task allocation and migration. According to the method, the technical means of load prediction analysis, quantitative matching of tasks and cores and dynamic combination and configuration of physical cores are adopted, and pre-judgment and prospective distribution of system resources can be achieved, so that performance requirements are met, meanwhile, the system energy efficiency is effectively optimized, and deep balance of power consumption and performance of a processor is achieved.
Owner:BING TANG INTELLIGENT TECH (SHANGHAI) CO LTD

Hot patching method for MIPS architecture software and related equipment

The invention discloses a hot patching method and related equipment for MIPS architecture software, and the method comprises the steps: making a hot patch corresponding to a to-be-patched function by using a pre-written patch making script, and compiling the hot patch to a dynamic library; loading the dynamic library, and putting a hot patch corresponding to the dynamic library into a memory of the MIPS architecture software; closing an instruction cache component of each processor in the MIPS architecture software, and reading and writing a memory to obtain a hot patch; and performing patch application on the hot patch to realize hot patch processing for the to-be-patched function. According to the method, hot patching of the MIPS architecture software of the multi-core processor is realized, and software defects can be quickly and safely repaired.
Owner:HUBEI ANXIN SMART TECH CO LTD

System and method for a safety critical operating environment container architecture

A system for providing a safety critical operating environment container architecture, the system including a computing device having a memory communicatively connected to at least one multi-core processor, the memory containing instructions configuring the processer to receive at least a software module to be executed on the at least one multi-core processor, create a separate virtual environment for the at least a software module, wherein creating the virtual environment further includes generating a virtualization layer and allocating a dedicated private static memory space through the virtualization layer, wherein the separate virtual environment includes a dedicated operating system, integrate the at least a software module into the virtual environment by instantiating, the software module into at least one software container, wherein the at least one software container includes a plurality of dedicated software packages and execute the software module on each software container for each virtual environment.
Owner:PARRY LABS LLC

Chip simulation verification acceleration method and device, equipment and storage medium

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

AIREBO potential optimization method and system suitable for multi-core processor

The invention discloses an AIREBO potential optimization method and system suitable for a multi-core processor, and relates to the technical field of molecular dynamics simulation. The method comprises the steps that atomic information is acquired, and a layered adjacency list is constructed according to the truncation radius characteristic of the AIREBO potential and the atomic information; a key sequence network is pre-constructed according to connectivity information between atoms in the adjacency list, and the pre-constructed key sequence network is utilized when the FLJ function is calculated; classifying and grouping according to different types of interactions among atoms, calculating FREBO functions in batches according to a classifying and grouping result, splitting calculation tasks, and processing the split tasks by using a multi-core processor; and integrating the calculation results of the FLJ function and the FREBO function, and combining the calculation result of the FORRSION function to obtain the final AIREBO potential. According to the method, AIREBO potential efficient parallel computing is realized on the basis of a multi-core processor architecture, and the overall molecular dynamics simulation efficiency is improved.
Owner:SHANDONG UNIV

Method for inter-core communication mode of multi-core processor

The invention provides a method of an inter-core communication mode of a multi-core processor, which comprises the following steps of: S1, determining a processor module partition, performing inter-partition communication initialization, and configuring a corresponding virtual partition, a virtual port and a corresponding driving program; s2, calling an interface program for communication between corresponding partitions in each partition application needing communication; s3, providing a corresponding communication service by the partition application; and S4, when data messages are required to be continuously received in sequence, calling an interface for creating the queue ports, sending messages to a source port in the queue ports through the interface for sending the messages in the partition application, calling the interface in the partition application in the partition needing to receive the messages, and receiving the messages of a destination queue port in sequence. And finally, communication monitoring and maintenance are performed, ID and state information of queues and sampling ports are searched regularly or as required, communication conditions are judged according to results, and if the queues are jammed or no new messages exist in the sampling ports, strategies are adjusted in time, faults are eliminated in time, and stable and efficient communication is ensured.
Owner:SANXIA JINSHAJIANG YUNCHUAN HYDROPOWER DEV CO LTD +1

Data transmission optimization method and system in hybrid deployment of real-time and non-real-time systems based on Jailhouse

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.
Owner:HARBIN INST OF TECH

Multi-core processor

The invention discloses a multi-core processor, which is used for improving the accuracy degree of data prefetching and further improving the data access efficiency of the multi-core processor. The processor comprises a plurality of processing units, a prediction unit, a prefetching unit and a memory unit, any processing unit comprises a first data collector, and the first data collector is used for collecting first historical data of the processing unit; the first historical data comprises an instruction executed by the processing unit, a memory address accessed by the instruction and whether data of the memory address is hit in a cache; the prediction unit is used for analyzing first historical data of any processing unit in a past period of time to obtain a predicted access sequence of the processing unit to the memory unit in a future period of time; and the prefetching unit is used for prefetching data from the memory unit according to the predicted access sequence and transmitting the prefetched data to the processing unit.
Owner:CHONGQING XINLIANXIN INTELLIGENT TECHNOLOGY CO LTD

Multi-node MPI set communication performance modeling method and system

ActiveCN119676099Aeasy to distinguishTransmissionMemory modelCommunication source
The invention discloses a multi-node MPI set communication performance modeling method and system, and the method comprises the steps: firstly determining model parameters needing to be measured according to the information of a multi-core processor in a node and the hierarchical information of a platform network; then measuring intra-node communication parameters and inter-node communication parameters on different network levels on the platform; analyzing a set communication source code and simulating a communication algorithm behavior to obtain all communication characteristics of each round of communication of the algorithm; and finally, corresponding parameters are selected in combination with communication characteristics, and the communication time of each round is represented by a mathematical formula of the corresponding parameters. Compared with an existing model, supercomputing network hierarchical structure information and a point-to-point communication primitive type used by a communication algorithm bottom layer are introduced, and the application range of the model is expanded from a single-node shared memory model to a hybrid model of a multi-node shared memory and an interconnection network; the model can more accurately predict the communication time of the multi-node set communication operation.
Owner:XI AN JIAOTONG UNIV

Network card drive optimization method and device, equipment and storage medium

The invention provides a network card drive optimization method and device, equipment and a storage medium, and the method comprises the steps: resetting a throttling counter in a drive interrupt path according to an interrupt merging factor and a throttling parameter of a hardware interrupt response determined by an interrupt behavior state model, and generating a merging control strategy; polling and reading the use state of the buffer area according to the combination control strategy, and updating an interrupt response state table; and determining an optimal interrupt processing core set according to the interrupt response state table and the original operation data, generating an interrupt affinity mapping strategy, grouping the to-be-processed data packets of the receiving queue, and performing batch scheduling on the soft interrupt threads of the corresponding groups based on different soft interrupt priority levels of each group. According to the scheme, the interrupt processing core is selected by constructing the dynamic interrupt affinity mapping strategy, adaptive allocation of interrupt scheduling is achieved, resource idling and core migration expenses are reduced, and the interrupt processing efficiency and the resource utilization rate of the multi-core processor are effectively improved.
Owner:SHENZHEN LIANBING TECHNOLOGY CO LTD

System-on-chip, system-on-chip configuration method and electronic equipment

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.
Owner:GOWIN SEMICON CORP LTD

Heterogeneous calculation and dynamic model updating method and device for brain-like chip and medium

The invention provides a brain-like chip heterogeneous calculation and dynamic model updating method, which comprises the following steps: constructing a neuron pulse coding and video feature parallel calculation model, carrying out heterogeneous integration on a brain-like chip supporting an SNN pulse neural network and a multi-core processor, and constructing a spatial-temporal feature dual-channel processing unit; developing a task load balancing algorithm based on synaptic weight dynamic allocation, including constructing a resource state matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment; a direct memory access channel is established between a brain-like chip and a video codec, a dedicated instruction set is expanded, and motion vector data of a video encoder is read through instruction level collaboration; carrying out binary differential coding on the key layer by adopting hierarchical parameter importance sorting, and compressing the update quantity of the key layer by combining a compression algorithm; and migrating a full-amount model to a lightweight model through dynamic knowledge distillation, and dynamically generating an adaptive model in combination with an attention migration loss function.
Owner:BEIJING ENGINEERING DIGITAL INTELLIGENCE (BEIJING) TECHNOLOGY CO LTD

Embedded system resource allocation method and system based on hardware virtualization

The invention discloses an embedded system resource allocation method and system based on hardware virtualization. The method comprises the following steps: deploying a Type-1 virtual machine monitor system on a multi-core processor hardware platform supporting virtualization extension; the Type-1 virtual machine monitor carries out virtualization, resource partitioning and security isolation on hardware resources, and creates operation system execution environment'domain 'partitions zoneG and zoneR. A universal operating system is deployed in a zoneG domain partition to take charge of a high-computing-power computing task, and a real-time operating system is deployed in a zoneR to take charge of a real-time computing task. Low-delay inter-core communication between a real-time operating system and a general operating system is realized based on an OpenAMP protocol, and data is transmitted through a shared memory and an interrupt mechanism; according to the requirements of real-time tasks and non-real-time tasks, a Type-1 virtual machine monitor dynamically adjusts a resource allocation strategy, and the priority and deadline of the real-time tasks are ensured.
Owner:NARI INFORMATION & COMM TECH

Shared LLC cache optimization management method based on multi-core processor

According to the shared LLC cache optimization management method based on the multi-core processor, exclusive shared LLC is divided for virtual machines with specific requirements, especially virtual machines with high real-time requirements, the memory access bandwidth of the virtual machines is dynamically adjusted, and meanwhile memory access operations of other virtual machines with low priorities are blocked, so that the memory access efficiency of the virtual machines is improved. And the real-time performance of the memory access response of the virtual machine with specific requirements is ensured.
Owner:EAST CHINA INST OF COMPUTING TECH

On-chip inter-core communication system and method

The invention relates to an on-chip inter-core communication system and method, the system comprises a plurality of processor cores, a shared memory and an interrupt control unit, the shared memory is connected with the plurality of processor cores, the plurality of processor cores are respectively connected with the interrupt control unit, the plurality of processor cores are divided into data sending cores and data receiving cores, the server is responsible for executing tasks and inter-core communication; a data frame lookup table and an annular buffer area are divided in the shared memory; and the interrupt control unit is used for processing inter-core interrupt. According to the multi-core processor, the advantage that the processor core in the multi-core processor quickly accesses the on-chip shared memory is utilized, so that the time delay of data writing / reading is reduced.
Owner:西安翔腾微电子科技有限公司

Spin lock optimization method and electronic equipment

The invention discloses a spin lock optimization method and electronic equipment, and the method comprises the steps: creating and initializing a spin lock structural body which comprises a lock holder pointer; when each thread obtains the spin lock, creating a corresponding request node structure body to form a waiting queue; in the waiting queue, determining spin lock holders in the plurality of threads based on the lock holder pointers; and after the processor core corresponding to the spin lock holder executes the critical zone code of the corresponding thread, traversing the waiting queue, reading the critical zone function pointer of each waiting node, and sequentially executing the critical zone code in each request node structure body on the current processor core based on the critical zone function pointer. According to the method, the performance bottleneck of a traditional spin lock in a multi-core environment is broken through, all-around optimization of cache consistency overhead, queue delay, energy efficiency ratio and multi-core expansibility is achieved, and the performance of the spin lock in the multi-core processor environment is remarkably improved.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD

Request processing method of multi-core processor, multi-core processor, product and server

The invention discloses a request processing method of a multi-core processor, the multi-core processor, a product and a server, and relates to the technical field of multi-core processors. In the method, a main node queries a directory according to a request and obtains a query result, and based on the query result, different request response strategies are adopted to respond to the request. According to the method, the consistency of the shared caches in the non-inclusion relation is maintained in a directory mode, the utilization rate of the shared caches is increased, and the chip area occupied by the caches is reduced under the condition that the cache capacity is fixed; secondly, based on the shared cache architecture of the non-inclusion relationship, the data is allowed to be stored in the private cache and the shared cache at the same time, so that the problem of excessive data exchange caused by cache position exchange in an exclusive architecture can be avoided, meanwhile, the private cache is allowed to reserve the data which does not exist in the shared cache, and the problem of reverse failure in an inclusion mode is avoided. According to the method, the utilization rate of the shared cache is improved, and the data exchange amount and the maintenance cost of cache consistency are reduced.
Owner:SHANDONG BOSUAN ZHIXIN INFORMATION TECHNOLOGY CO LTD

Instruction-level simulation and performance modeling system for parallel computing architecture

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.
Owner:YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD

Memory access method and device, medium and product

The invention discloses a memory access method and device, a medium and a product, and relates to the field of memory management.The memory access method comprises the steps that when a multi-core RISC-V processor allocates a memory area for a target process from a system memory, if the system memory is insufficient, the future access probability of each replaceable process to the corresponding memory area in the system memory is predicted, taking the process with the minimum future access probability as a process to be replaced; replacing the memory page table of the to-be-replaced process from the system memory to a hard disk to release a corresponding memory area in the system memory, and completing memory area distribution of the target process based on the released system memory; if it is pre-judged that the memory page table of the replaced process needs to be accessed, the memory area is allocated to the replaced process again, and the memory page table of the replaced process is replaced from the hard disk to the current reallocated memory area, so that access to the memory page table of the replaced process is completed. According to the multi-core RISC-V processor, the overall performance of the multi-core RISC-V processor can be improved.
Owner:SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD

Multi-core consistency dynamic synchronization method and system based on RISC-V architecture

The invention is suitable for the field of computer system structures, and provides a multi-core consistency dynamic synchronization method and system based on an RISC-V. The method comprises the steps that the core of a multi-core processor is spatially divided into n consistency domains, each consistency domain is configured with an independent area directory cache and an independent RCC, and transactions in the area are locally processed by the corresponding RCC; when a core in the consistency domain initiates a data operation request, the RCC to which the core belongs checks the state of target data in the consistency domain; according to the data state, the RCC carries out internal synchronization in the consistency domain by adopting an optimized broadcast protocol, or carries out directory type point-to-point communication with other consistency domains through the GDSA to realize cross-domain synchronization; on the premise of ensuring strict consistency, communication delay and energy consumption are remarkably reduced, the overall throughput and expandability of the system are improved, and an efficient consistency solution idea is provided for the RISC-V multi-core processor.
Owner:SHANDONG UNIV +1

Heterogeneous multi-core processor task scheduling method, system, equipment and medium

The invention discloses a heterogeneous multi-core processor task scheduling method, system and device and a medium, and mainly relates to the technical field of task scheduling. The method is used for solving the problems that a traditional scheduling algorithm cannot process task dependency and communication overhead of a heterogeneous multi-core processor, a heuristic algorithm is prone to falling into local optimum, and a basic sparrow search algorithm has premature convergence in task scheduling. Comprising the following steps: taking a task scheduling sequence related to a DAG task scheduling graph, a communication frequency sum corresponding to the task scheduling sequence and a cross-core communication overhead sum as input data of a sparrow search algorithm; a discoverer in the sparrow population is updated through a random fractal search mechanism, and an addresser in the sparrow population is updated through a topology adaptive mechanism; meanwhile, a minimum scheduling length calculation function is used as a target function, and constraint conditions are configured; and when a preset iteration stopping condition is reached, outputting an optimal task scheduling sequence meeting the target function and the constraint condition.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

Low-power-consumption audio and video decoding system and method based on plug-in product

The invention relates to the technical field of audio and video decoding, and relates to a low-power-consumption audio and video decoding system and method based on a plug-in product. The system comprises a main control unit which integrates a multi-core processor and a task scheduler and is used for distributing decoding tasks in real time and supporting dynamic frequency adjustment; the plug-in decoding module is connected with the main control unit through an expansion interface; the intelligent power consumption management module is connected with the main control unit and the plug-in decoding module, comprises a load prediction algorithm and a self-adaptive voltage regulation unit, and is used for dynamically regulating the working voltage and the clock frequency of the decoding module according to the task load; and the power supply management module supplies power to the main control unit, the plug-in decoding module and the intelligent power consumption management module. Independent upgrading of the decoder is realized through plug-in hardware modular design, and the problems of high energy consumption, low expansibility, large synchronization delay and the like in a traditional scheme are solved by combining an intelligent task allocation strategy and a self-adaptive voltage regulation technology.
Owner:SHANDONG ARTAPLAY INTELLIGENT TECH CO LTD

Master station communication method, computing system and computing equipment

The invention relates to the technical field of industrial control, and discloses a master station communication method, a computing system and computing equipment. The master station communication method is applied to the computing device, the computing device comprises a multi-core processor and a network card, the multi-core processor comprises a plurality of processor cores, the plurality of processor cores comprise a first processor core and a second processor core, the first processor core is used for operating a non-real-time system, and the second processor core is used for operating a real-time system. A master station module runs on the real-time system. The method comprises the following steps: generating a target control instruction of the master station module to slave station equipment; the target control instruction is used for the master station module to control slave station equipment; the target control instruction is written into a sending buffer area of the real-time system, so that the network card reads the target control instruction and sends the target control instruction to the slave station equipment; wherein the sending buffer area is configured for a non-real-time system and a real-time system. According to the invention, real-time communication between the master station module and the slave station equipment can be realized through the real-time system.
Owner:HENAN KUNLUN TECH CO LTD

Multi-core processor AMP architecture real-time operating system starting method

The invention relates to the technical field of embedded operating systems, in particular to a multi-core processor AMP architecture real-time operating system starting method, which comprises the following steps: reserving a real-time operating system memory in U-Boot and Linux equipment trees by defining nodes, and setting specific attributes to prevent resource conflicts; a real-time operating system core is forbidden in a Linux device tree, and a node is defined to reserve an inter-core communication shared memory. After the related mirror image is solidified by utilizing a burning tool, the U-Boot firstly loads the mirror image of the real-time operating system to a reserved address, starts a corresponding core by virtue of a CPUON function of a power management interface specification, then loads a Linux kernel and a file system to start the Linux, and the dual systems communicate through a shared memory segment; the starting speed of a real-time operating system is increased, the high-real-time scene requirement is met, and the starting delay risk is reduced.
Owner:GUANGZHOU JINQILI INFORMATION TECH CO LTD

Top structure based on GPU multi-core processor and Cache consistency processing method

The invention is suitable for the technical field of GPUs, and provides a top layer structure based on a GPU multi-core processor and a Cache consistency processing method. According to the technical scheme, on the basis of a catalog type, information exchange and transmission between a catalog type total catalog controller and all Caches are simplified in combination with monitoring type transmission and management states, six states of an MESIPB protocol are designed, and the consistency of the Caches is improved. According to the method and the system, switching between Cache Line states is realized, the access times of a video memory are effectively reduced, the GPU structure is clear, the expansibility is good, the problem of Cache consistency during GPU multi-core processing can be solved with relatively low resource overhead, the GPU processing speed and the core utilization rate are well improved, and bus bandwidth, storage bandwidth and overhead caused by data access are effectively reduced.
Owner:WUHAN LINGJIU MICROELECTRONICS CO LTD