Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

280 results about "Multi-core processor" patented technology

A multi-core processor is a computer processor integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions, as if the computer had several processors. The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that don't even share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.

Cryptocurrency hardware wallet on monolithic chip with common physical countermeasures and secure memory

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.
Owner:CROSSBAR INC

Power consumption and performance balanced scheduling method and system for heterogeneous multi-core processor

The invention discloses a power consumption and performance balanced scheduling method and system for a heterogeneous multi-core processor, and belongs to the technical field of computers, and the method comprises the steps: obtaining historical load data and current system state parameters, generating a load sequence and carrying out load prediction analysis, generating a predicted load value for feature fusion and quantification, and generating a task feature vector; constructing a core capability portrait, calculating a matching degree between the task characteristic vector and the core capability portrait, and generating a scheduling strategy; and dynamically combining the physical cores into a logic calculation unit according to a scheduling strategy, configuring a power consumption state, and executing task allocation and migration. According to the method, the technical means of load prediction analysis, quantitative matching of tasks and cores and dynamic combination and configuration of physical cores are adopted, and pre-judgment and prospective distribution of system resources can be achieved, so that performance requirements are met, meanwhile, the system energy efficiency is effectively optimized, and deep balance of power consumption and performance of a processor is achieved.
Owner:BING TANG INTELLIGENT TECH (SHANGHAI) CO LTD

Chip simulation verification acceleration method and device, equipment and storage medium

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

AIREBO potential optimization method and system suitable for multi-core processor

The invention discloses an AIREBO potential optimization method and system suitable for a multi-core processor, and relates to the technical field of molecular dynamics simulation. The method comprises the steps that atomic information is acquired, and a layered adjacency list is constructed according to the truncation radius characteristic of the AIREBO potential and the atomic information; a key sequence network is pre-constructed according to connectivity information between atoms in the adjacency list, and the pre-constructed key sequence network is utilized when the FLJ function is calculated; classifying and grouping according to different types of interactions among atoms, calculating FREBO functions in batches according to a classifying and grouping result, splitting calculation tasks, and processing the split tasks by using a multi-core processor; and integrating the calculation results of the FLJ function and the FREBO function, and combining the calculation result of the FORRSION function to obtain the final AIREBO potential. According to the method, AIREBO potential efficient parallel computing is realized on the basis of a multi-core processor architecture, and the overall molecular dynamics simulation efficiency is improved.
Owner:SHANDONG UNIV

Method for inter-core communication mode of multi-core processor

The invention provides a method of an inter-core communication mode of a multi-core processor, which comprises the following steps of: S1, determining a processor module partition, performing inter-partition communication initialization, and configuring a corresponding virtual partition, a virtual port and a corresponding driving program; s2, calling an interface program for communication between corresponding partitions in each partition application needing communication; s3, providing a corresponding communication service by the partition application; and S4, when data messages are required to be continuously received in sequence, calling an interface for creating the queue ports, sending messages to a source port in the queue ports through the interface for sending the messages in the partition application, calling the interface in the partition application in the partition needing to receive the messages, and receiving the messages of a destination queue port in sequence. And finally, communication monitoring and maintenance are performed, ID and state information of queues and sampling ports are searched regularly or as required, communication conditions are judged according to results, and if the queues are jammed or no new messages exist in the sampling ports, strategies are adjusted in time, faults are eliminated in time, and stable and efficient communication is ensured.
Owner:SANXIA JINSHAJIANG YUNCHUAN HYDROPOWER DEV CO LTD +1

Data transmission optimization method and system in hybrid deployment of real-time and non-real-time systems based on Jailhouse

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.
Owner:HARBIN INST OF TECH

Network card drive optimization method and device, equipment and storage medium

The invention provides a network card drive optimization method and device, equipment and a storage medium, and the method comprises the steps: resetting a throttling counter in a drive interrupt path according to an interrupt merging factor and a throttling parameter of a hardware interrupt response determined by an interrupt behavior state model, and generating a merging control strategy; polling and reading the use state of the buffer area according to the combination control strategy, and updating an interrupt response state table; and determining an optimal interrupt processing core set according to the interrupt response state table and the original operation data, generating an interrupt affinity mapping strategy, grouping the to-be-processed data packets of the receiving queue, and performing batch scheduling on the soft interrupt threads of the corresponding groups based on different soft interrupt priority levels of each group. According to the scheme, the interrupt processing core is selected by constructing the dynamic interrupt affinity mapping strategy, adaptive allocation of interrupt scheduling is achieved, resource idling and core migration expenses are reduced, and the interrupt processing efficiency and the resource utilization rate of the multi-core processor are effectively improved.
Owner:SHENZHEN LIANBING TECHNOLOGY CO LTD

System-on-chip, system-on-chip configuration method and electronic equipment

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.
Owner:GOWIN SEMICON CORP LTD

Heterogeneous calculation and dynamic model updating method and device for brain-like chip and medium

The invention provides a brain-like chip heterogeneous calculation and dynamic model updating method, which comprises the following steps: constructing a neuron pulse coding and video feature parallel calculation model, carrying out heterogeneous integration on a brain-like chip supporting an SNN pulse neural network and a multi-core processor, and constructing a spatial-temporal feature dual-channel processing unit; developing a task load balancing algorithm based on synaptic weight dynamic allocation, including constructing a resource state matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment; a direct memory access channel is established between a brain-like chip and a video codec, a dedicated instruction set is expanded, and motion vector data of a video encoder is read through instruction level collaboration; carrying out binary differential coding on the key layer by adopting hierarchical parameter importance sorting, and compressing the update quantity of the key layer by combining a compression algorithm; and migrating a full-amount model to a lightweight model through dynamic knowledge distillation, and dynamically generating an adaptive model in combination with an attention migration loss function.
Owner:BEIJING ENGINEERING DIGITAL INTELLIGENCE (BEIJING) TECHNOLOGY CO LTD

Embedded system resource allocation method and system based on hardware virtualization

The invention discloses an embedded system resource allocation method and system based on hardware virtualization. The method comprises the following steps: deploying a Type-1 virtual machine monitor system on a multi-core processor hardware platform supporting virtualization extension; the Type-1 virtual machine monitor carries out virtualization, resource partitioning and security isolation on hardware resources, and creates operation system execution environment'domain 'partitions zoneG and zoneR. A universal operating system is deployed in a zoneG domain partition to take charge of a high-computing-power computing task, and a real-time operating system is deployed in a zoneR to take charge of a real-time computing task. Low-delay inter-core communication between a real-time operating system and a general operating system is realized based on an OpenAMP protocol, and data is transmitted through a shared memory and an interrupt mechanism; according to the requirements of real-time tasks and non-real-time tasks, a Type-1 virtual machine monitor dynamically adjusts a resource allocation strategy, and the priority and deadline of the real-time tasks are ensured.
Owner:NARI INFORMATION & COMM TECH

Spin lock optimization method and electronic equipment

The invention discloses a spin lock optimization method and electronic equipment, and the method comprises the steps: creating and initializing a spin lock structural body which comprises a lock holder pointer; when each thread obtains the spin lock, creating a corresponding request node structure body to form a waiting queue; in the waiting queue, determining spin lock holders in the plurality of threads based on the lock holder pointers; and after the processor core corresponding to the spin lock holder executes the critical zone code of the corresponding thread, traversing the waiting queue, reading the critical zone function pointer of each waiting node, and sequentially executing the critical zone code in each request node structure body on the current processor core based on the critical zone function pointer. According to the method, the performance bottleneck of a traditional spin lock in a multi-core environment is broken through, all-around optimization of cache consistency overhead, queue delay, energy efficiency ratio and multi-core expansibility is achieved, and the performance of the spin lock in the multi-core processor environment is remarkably improved.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD

Request processing method of multi-core processor, multi-core processor, product and server

The invention discloses a request processing method of a multi-core processor, the multi-core processor, a product and a server, and relates to the technical field of multi-core processors. In the method, a main node queries a directory according to a request and obtains a query result, and based on the query result, different request response strategies are adopted to respond to the request. According to the method, the consistency of the shared caches in the non-inclusion relation is maintained in a directory mode, the utilization rate of the shared caches is increased, and the chip area occupied by the caches is reduced under the condition that the cache capacity is fixed; secondly, based on the shared cache architecture of the non-inclusion relationship, the data is allowed to be stored in the private cache and the shared cache at the same time, so that the problem of excessive data exchange caused by cache position exchange in an exclusive architecture can be avoided, meanwhile, the private cache is allowed to reserve the data which does not exist in the shared cache, and the problem of reverse failure in an inclusion mode is avoided. According to the method, the utilization rate of the shared cache is improved, and the data exchange amount and the maintenance cost of cache consistency are reduced.
Owner:SHANDONG BOSUAN ZHIXIN INFORMATION TECHNOLOGY CO LTD

Instruction-level simulation and performance modeling system for parallel computing architecture

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.
Owner:YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD

Multi-core consistency dynamic synchronization method and system based on RISC-V architecture

The invention is suitable for the field of computer system structures, and provides a multi-core consistency dynamic synchronization method and system based on an RISC-V. The method comprises the steps that the core of a multi-core processor is spatially divided into n consistency domains, each consistency domain is configured with an independent area directory cache and an independent RCC, and transactions in the area are locally processed by the corresponding RCC; when a core in the consistency domain initiates a data operation request, the RCC to which the core belongs checks the state of target data in the consistency domain; according to the data state, the RCC carries out internal synchronization in the consistency domain by adopting an optimized broadcast protocol, or carries out directory type point-to-point communication with other consistency domains through the GDSA to realize cross-domain synchronization; on the premise of ensuring strict consistency, communication delay and energy consumption are remarkably reduced, the overall throughput and expandability of the system are improved, and an efficient consistency solution idea is provided for the RISC-V multi-core processor.
Owner:SHANDONG UNIV +1

Heterogeneous multi-core processor task scheduling method, system, equipment and medium

The invention discloses a heterogeneous multi-core processor task scheduling method, system and device and a medium, and mainly relates to the technical field of task scheduling. The method is used for solving the problems that a traditional scheduling algorithm cannot process task dependency and communication overhead of a heterogeneous multi-core processor, a heuristic algorithm is prone to falling into local optimum, and a basic sparrow search algorithm has premature convergence in task scheduling. Comprising the following steps: taking a task scheduling sequence related to a DAG task scheduling graph, a communication frequency sum corresponding to the task scheduling sequence and a cross-core communication overhead sum as input data of a sparrow search algorithm; a discoverer in the sparrow population is updated through a random fractal search mechanism, and an addresser in the sparrow population is updated through a topology adaptive mechanism; meanwhile, a minimum scheduling length calculation function is used as a target function, and constraint conditions are configured; and when a preset iteration stopping condition is reached, outputting an optimal task scheduling sequence meeting the target function and the constraint condition.
Owner:SHANDONG INSPUR SCI RES INST CO LTD

Master station communication method, computing system and computing equipment

The invention relates to the technical field of industrial control, and discloses a master station communication method, a computing system and computing equipment. The master station communication method is applied to the computing device, the computing device comprises a multi-core processor and a network card, the multi-core processor comprises a plurality of processor cores, the plurality of processor cores comprise a first processor core and a second processor core, the first processor core is used for operating a non-real-time system, and the second processor core is used for operating a real-time system. A master station module runs on the real-time system. The method comprises the following steps: generating a target control instruction of the master station module to slave station equipment; the target control instruction is used for the master station module to control slave station equipment; the target control instruction is written into a sending buffer area of the real-time system, so that the network card reads the target control instruction and sends the target control instruction to the slave station equipment; wherein the sending buffer area is configured for a non-real-time system and a real-time system. According to the invention, real-time communication between the master station module and the slave station equipment can be realized through the real-time system.
Owner:HENAN KUNLUN TECH CO LTD

Multi-core processor AMP architecture real-time operating system starting method

The invention relates to the technical field of embedded operating systems, in particular to a multi-core processor AMP architecture real-time operating system starting method, which comprises the following steps: reserving a real-time operating system memory in U-Boot and Linux equipment trees by defining nodes, and setting specific attributes to prevent resource conflicts; a real-time operating system core is forbidden in a Linux device tree, and a node is defined to reserve an inter-core communication shared memory. After the related mirror image is solidified by utilizing a burning tool, the U-Boot firstly loads the mirror image of the real-time operating system to a reserved address, starts a corresponding core by virtue of a CPUON function of a power management interface specification, then loads a Linux kernel and a file system to start the Linux, and the dual systems communicate through a shared memory segment; the starting speed of a real-time operating system is increased, the high-real-time scene requirement is met, and the starting delay risk is reduced.
Owner:GUANGZHOU JINQILI INFORMATION TECH CO LTD

Data cache access method and device of multi-core processor

The invention provides a data cache access method and device of a multi-core processor, and relates to the technical field of computer processors. The method comprises the following steps: accessing a data cache according to an access instruction, and responding to the access instruction to hit access data and write back the access data, or responding to the access instruction to not hit the access data, fetching back-filling data from a memory access failure queue and forwarding the back-filling data to the access queue. Accessing the data cache according to the data storage instruction, writing the stored data into the data cache in response to the access hit of the data cache, or calling a stored data retransmission unit in response to the access miss of the data cache; and sending a data storage failure request to the memory access failure queue, and taking back the backfill data and / or authority by the memory access failure queue. According to the method, the flexibility of the processing mode of the data cache access pipeline on the memory access instruction and the external consistency request can be improved, the access parallelism degree is improved, and the hardware resource utilization rate of the processor is increased.
Owner:BEIJING VCORE TECH CO LTD

Vehicle fault diagnosis method and device, electronic equipment and readable storage medium

The invention discloses a vehicle fault diagnosis method and device, electronic equipment and a readable storage medium, the method is applied to a vehicle fault diagnosis system, and the vehicle fault diagnosis system comprises a vehicle, a cloud server and terminal equipment; a vehicle collects vehicle data, determines fault data in the vehicle data based on parallel analysis of a multi-core processor, and generates common fault information and repair suggestions based on the fault data; the vehicle sends the fault data to a cloud server, the cloud server carries out deep diagnosis on the fault data through a multi-modal analysis system and generates a diagnosis report, and the diagnosis report comprises complete fault information and a solution of the vehicle; and the terminal equipment receives and displays the generated common fault information, repair suggestions and diagnosis reports, and provides technical guidance of vehicle fault maintenance for a user based on remote connection. Therefore, the method disclosed by the invention is based on local processing of the vehicle, the fault response speed is improved, the load of the cloud server is reduced, and the stability of the system is improved.
Owner:LAUNCH TECH CO LTD

Multi-core processor dynamic regulation and control method and system based on load and temperature sensing

The invention discloses a multi-core processor dynamic regulation and control method and system based on load and temperature sensing, and relates to the technical field of temperature control scheduling management, and the method comprises the steps: collecting and preprocessing load and temperature data in real time, and building a thermal sensing model to predict the temperature change; constructing a self-adaptive heuristic scheduling algorithm, and adjusting task distribution according to real-time data of the core load and the temperature; according to the load and temperature states, a dynamic voltage frequency adjustment strategy is adopted, and the frequency and the voltage are automatically adjusted when the load and the temperature are too high; and when the load and the temperature exceed set threshold values, a scheduling algorithm is optimized by adopting a self-learning mechanism, and a scheduling strategy and a temperature control scheme are automatically adjusted. According to the method, a more flexible and accurate dynamic regulation and control scheme is provided, the stability and high efficiency of the processor in a high-load and high-temperature environment can be ensured, performance reduction and hardware damage are avoided, and the obvious effects of saving energy and improving system stability are achieved.
Owner:KING BEST TECH CO LTD

Microprocessor dynamic power consumption optimization system based on deep learning

The invention discloses a microprocessor dynamic power consumption optimization system based on deep learning, which belongs to the technical field of microprocessor power consumption management, and comprises a working load feature extraction module, a neural network prediction module, a dynamic core distribution module and a particle size power supply management module, the working load feature extraction module extracts feature parameters of calculation intensity, memory access intensity and input and output intensity of an application program in real time through a hardware circuit; the neural network prediction module predicts future power consumption and performance requirements based on a deep reinforcement learning network; the dynamic core distribution module intelligently selects an optimal core combination; the particle size power supply management module independently executes dynamic voltage frequency regulation on each core; according to the invention, accurate power consumption optimization of the heterogeneous multi-core processor is realized through deep coupling and closed-loop cooperation of the four modules, and compared with the prior art, the energy efficiency ratio is improved by more than 40%, and the power consumption prediction error is reduced to be within 5%.
Owner:NANCHANG UNIV

Virtual power plant rapid frequency modulation control system and control method

The invention discloses a virtual power plant rapid frequency modulation control system and control method, and the method comprises the steps: adaptively adjusting a sampling period through a dynamic sampling algorithm based on a sliding window variance; low-delay calculation of high-frequency data is realized by adopting a multi-thread queue communication technology; a multi-core ARM processor running a real-time operating system is used for executing a multi-thread control model, and data acquisition, algorithm control, fault diagnosis and communication tasks are processed in parallel; according to the control algorithm, frequency prediction feedforward signals based on an AI model and SOC state feedback are fused, and dynamic optimization of PID parameters is achieved. According to the method, millisecond-level frequency modulation response can be realized, the instruction response delay is less than 80ms, the frequency adjustment error is less than + / -0.01 Hz, the frequency modulation performance of a virtual power plant and the stability of a power grid are remarkably improved, and meanwhile, the service life of energy storage equipment is prolonged through SOC collaborative optimization. The invention aims to solve the problems of slow response and low precision of the existing frequency modulation technology.
Owner:JIANGSU AURORA YUNNENG NEW ENERGY CO LTD

Electric power meter data real-time analysis and abnormity early warning method based on edge calculation

The invention provides an electric power meter data real-time analysis and abnormity early warning method based on edge calculation, and belongs to the technical field of data analysis and early warning, and the method comprises the steps: collecting the multi-modal data of an electric power meter based on a multi-channel analog-to-digital converter, employing a hardware filter circuit to eliminate high-frequency noise, and obtaining the data of the electric power meter; signal gain self-adaptive adjustment is carried out based on a reconfigurable amplifier; a digital signal processing accelerator is used to carry out Fourier transform on a matrix constructed by the standardized data stream, and a multi-core processor is combined to carry out analysis to generate a feature vector; the method comprises the following steps: acquiring environmental parameters in real time based on an environmental sensor, dynamically adjusting an anomaly detection threshold in combination with a machine learning model trained by historical data, and comparing a feature vector with the dynamic threshold to generate an anomaly signal; the relay control circuit triggers sound-light alarm, the physically isolated communication module sends an early warning instruction to the cloud platform, and meanwhile, the redundant power supply module is started to control the electric power meter to operate continuously. And the efficiency and accuracy of subsequent abnormity early warning are improved.
Owner:SHENZHEN ZHENMEI ELECTRIC POWER TECHNOLOGY CO LTD

Graph convolutional network accelerator and equipment based on dynamic compression and sparse reordering

The invention discloses a graph convolutional network accelerator and equipment based on dynamic compression and sparse reordering, the graph convolutional network accelerator comprises a combination engine, an aggregation engine, a controller and a storage unit, the aggregation engine comprises an ECSR decoder, a scheduler and a plurality of multi-core SIMD processors which are connected in sequence, the ECSR decoder is used for extracting side information from an adjacency matrix represented by a sparse compression format ECSR, the adjacency matrix represented by the sparse compression format ECSR comprises a row pointer array and a column index array, the row pointer array comprises row numbers containing non-zero elements in the adjacency matrix, the column index array stores column position indexes of all rows containing the non-zero elements, and the column position indexes of all the rows containing the non-zero elements are stored in the column index array. The column position index is generated by adopting differential coding and variable byte coding. The method aims at improving the effective data throughput rate and the memory access efficiency of graph convolutional network acceleration, improving the calculation performance during feature updating and accelerating the reasoning process of the graph convolutional network.
Owner:NAT UNIV OF DEFENSE TECH

Server multi-core computing processor load optimization test method, device and equipment and medium

The invention relates to the technical field of server testing, in particular to a server multi-core computing processor load optimization testing method, device and equipment and a medium, and the method comprises the following steps: automatically identifying hardware configuration information of a server; generating a multi-dimensional pressure test plan based on the hardware configuration information; executing the test plan, and monitoring the load rate, the memory bandwidth, the cache hit rate and the I / O performance index of each CPU core in real time; dynamically adjusting a task allocation strategy based on a set load difference threshold to realize task dynamic optimization, and if the difference between the maximum core load rate and the minimum core load rate is monitored to exceed the threshold, triggering a task migration operation; system performance data are collected again, performance indexes before and after optimization are compared and analyzed, and system performance bottlenecks are recognized; and automatically generating a performance test report. The utilization rate and the overall task throughput of the multi-core processor are improved, and the problem that a static task allocation strategy is difficult to adapt to dynamic load changes is solved.
Owner:SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD

Data classification processing method and system for parallel computing of multi-core processor

The invention discloses a data classification processing method and system for parallel computing of a multi-core processor, relates to the technical field of data classification processing, and effectively solves the problem of abnormal disturbance in multi-core parallel data classification through a confidence-driven heterogeneous pipeline architecture. According to dynamic grading processing based on data block confidence, high-confidence data is ensured to completely process a link, and meanwhile, rapid classification and cache isolation are performed on low-confidence data, so that an assembly line is prevented from being blocked by abnormal data; a self-adaptive window segmentation mechanism is linked with confidence coefficient fluctuation and calculation resource ratio, and inter-core load unbalance caused by sudden abnormity is relieved; a double-closed-loop control strategy combines a real-time queue state with a historical load mode, and the cache pollution risk caused by thread migration is reduced.
Owner:BEIJING SHULIAN TECHNOLOGY CO LTD

Online one-stop new energy power station rapid power regulation portable test system

The invention discloses an online one-stop new energy power station rapid power regulation portable test system. The system comprises a multi-core processor and a data acquisition device. The data acquisition equipment acquires three-phase voltage and three-phase current analog quantity, signal analog quantity and external trigger calibration signal input quantity of a power grid, and outputs AGC / AVC remote regulation signal output quantity; the multi-core processor comprises test software, an Ethernet communication interface and a USB (Universal Serial Bus) interface; the test software comprises a test function selection module, a data acquisition and storage module, a digital filtering module, a signal frequency measurement and amplitude measurement module, a power calculation module, an AGC / AVC communication module and a test result analysis and report automatic generation module. The system fully considers the diversity of field test schemes according to the high automation and portability requirements of the new energy power station rapid power regulation field test, has the characteristics of online one-stop, portability, high compatibility and the like, and provides an efficient and accurate test scheme for the new energy power station rapid power regulation.
Owner:QINGHAI ELECTRIC POWER RES TECH

Multi-core processor system and cache line locking control method

The embodiment of the invention provides a multi-core processor system and a cache line locking control method, and the multi-core processor system comprises a plurality of cores and a cache line locking control unit, each core comprises at least one level of cache; each level of cache is used for identifying a cache access request in the received monitoring information; when it is identified that the cache access request is a request for accessing the cache line locked by the cache at the same level and the locked cache behavior core has the cache line under the use condition, a delay signal is sent out, and processing of the monitoring information is paused; when the execution signal is obtained, processing of the monitoring information is recovered, and the locked cache line is released; the cache line locking control unit is used for receiving the delay signal and sending out an execution signal at a preset delay moment; the locked cache line is realized on the basis of a lock obtained by a core execution lock grabbing mechanism. According to the technical scheme provided by the embodiment of the invention, the efficiency of executing a lock grabbing mechanism can be improved, and the overall performance of a multi-core processor system is improved.
Owner:HYGON INFORMATION TECH CO LTD

System and method for a safety critical operating environment container architecture

A system for providing a safety critical operating environment container architecture, the system including a computing device having a memory communicatively connected to at least one multi-core processor, the memory containing instructions configuring the processer to receive at least a software module to be executed on the at least one multi-core processor, create a separate virtual environment for the at least a software module, wherein creating the virtual environment further includes generating a virtualization layer and allocating a dedicated private static memory space through the virtualization layer, wherein the separate virtual environment includes a dedicated operating system, integrate the at least a software module into the virtual environment by instantiating, the software module into at least one software container, wherein the at least one software container includes a plurality of dedicated software packages and execute the software module on each software container for each virtual environment.
Owner:PARRY LABS LLC

Method of performing atomic memory operations and multicore processor

The present disclosure provides an execution method of an atomic memory operation and a multi-core processor. The method comprises: a first node interacts with a master node to execute the atomic memory operation, wherein the first data is generated after the execution of the atomic memory operation; the first node sends a unique permission read request to the master node; the first node receives the first data returned by the master node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.
Owner:SANECHIPS TECH CO LTD