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23 results about "Multi-core processor" patented technology

A multi-core processor is a computer processor integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions, as if the computer had several processors. The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support multithreading or other parallel computing techniques. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar. Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have cores that are not identical (e.g. big.LITTLE have heterogeneous cores that share the same instruction set, while AMD Accelerated Processing Units have cores that don't even share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, vector, or multithreading.

A multi-core cache coherency debugging method based on multi-view access

The application discloses a multi-core cache consistency debugging method based on multi-view access and belongs to the field of multi-core processor debugging. The method is characterized in that a target address is specified in a main memory by a host computer through a JTAG debugging interface, five groups of data of CPU view, L1 data cache view, L1 instruction cache view, L2 view and real memory view corresponding to the address are read in turn, whether cache is invalid is judged by comparing data consistency, and a cache level inconsistent is marked. The debugging system comprises a built-in JTAG TAP controller, an enhanced debugging access module, a storage level access arbitrator and a data and state collector. The application realizes direct access of the JTAG interface to data of each level of cache, does not need to modify hardware or disable cache, does not interfere with system operation, can quickly locate cache consistency problems under a multi-core architecture, improves debugging efficiency and accuracy, and is suitable for debugging scenes of large-scale multi-core processors.
Owner:58TH RES INST OF CETC

A cache access method, system, medium and product

The application discloses a cache access method and system, a medium and a product, and applies to the technical field of processors, and comprises the following steps: monitoring the memory access behavior of each processor core to a shared cache, each cache line in the shared cache is divided into a preset number of data subsegments, for each processor core, a unique corresponding state identifier is arranged for each data subsegment; after any processor core performs data writing on a target data subsegment of a target cache line in the shared cache, the target data subsegment is written back to a memory, and is loaded from the memory to a private cache of the any processor core, the state identifier of the target data subsegment of the any processor core is determined as a shared state, and the state identifier of the target data subsegment of a first processor core is determined as an invalid state. In this way, unnecessary memory data loading can be reduced, and the overall performance of a multi-core processor is improved.
Owner:SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD

A resource dynamic cooperative scheduling method, architecture and chip of a heterogeneous multi-core processor

This disclosure relates to the field of artificial intelligence chip technology, specifically to a method, architecture, and chip for dynamic collaborative resource scheduling of heterogeneous multi-core processors. The method includes: processing the computation graph using a trained graph convolutional network to obtain corresponding task feature vectors; acquiring resource status information of a heterogeneous resource pool; establishing a weighted multi-objective optimization function with maximizing performance indicators and minimizing power consumption indicators as optimization objectives; determining an iterative greedy strategy for approximating the optimization objectives; in each iteration, selecting the optimal candidate resource from the heterogeneous resource pool to add to a virtual computing cluster; and calculating whether the computing resources, storage capacity, and transmission bandwidth provided by the updated virtual computing cluster meet the corresponding requirements, until the target virtual computing cluster is obtained. This disclosure achieves precise matching between task characteristics and hardware resources, dynamically generates optimal resource configuration schemes, and improves system-level energy efficiency while ensuring smooth task execution.
Owner:BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD +2

Thread synchronization methods and devices, chip simulation methods and platforms, and related equipment

ActiveCN115729627BComputer hardwareMulti-core processor
This invention provides a thread synchronization method and apparatus, a chip simulation method and platform, and related devices. The thread synchronization method, applied to a processor core in a multi-core processor, includes: acquiring lock state record information, wherein the lock state record information records the lock acquisition state of each processor core in the multi-core processor, the lock acquisition state including at least a first state and a second state; after the lock state record information indicates that the lock acquisition state of each processor core in the multi-core processor in the previous synchronization process is the second state, issuing a lock request to request lock permission to access the shared storage device of the multi-core processor. This method improves the task processing efficiency of the multi-core processor by controlling the issuance of lock requests.
Owner:HYGON INFORMATION TECH CO LTD

A supervision and report integrated machine system based on hardware and software integration

ActiveCN121996216BData streamCiphertext
The present application relates to the technical field of finance and banking, and discloses a supervision reporting integrated machine system based on software and hardware integration, which comprises a compiling module, an access module, a scheduling module and an aggregation module.The compiling module parses supervision specifications into a fixed-width compliance state bit string and binds the bit string to the physical core of a multi-core processor to establish a hardware verification topology path.The access module writes business flow data into a physical memory pool and allocates a data physical pointer and a compliance state bitmap.The scheduling module executes compliance verification logic by using the data physical pointer according to the hardware verification topology path, and updates the compliance state bitmap when the execution is passed.The aggregation module reorganizes business flow data into a huge physical memory page by using a data flow accelerator when the updated compliance state bitmap meets a mask condition.The sending module triggers an encryption accelerator card to generate ciphertext data based on the starting address of the huge physical memory page and sends the ciphertext data through a network interface card.The present application avoids cross-core copying of full data, reduces hardware bus communication delay, and improves the execution efficiency of concurrent verification.
Owner:YUSYS TECH CO LTD

Storage device and method of operating a storage device

A method of operating a storage device including a non-volatile memory and a multi-core processor having at least two cores and a storage device are disclosed. The method includes the steps of receiving, by a host interface of the storage device, a first memory command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, a first task and a second task from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution time of the at least two cores; assigning, by the task scheduler, the first task and the second task to the first core; and after the first core processes the assigned first task, loading, by the first core, code for processing the second task while the first core requests a subsequent task from the task scheduler.
Owner:SAMSUNG ELECTRONICS CO LTD

Reconfigurable interconnection circuit for multi-core processor, implementation method, and chip

The present application relates to the technical field of chips, and discloses a reconfigurable interconnection circuit for a multi-core processor, an implementation method, and a chip. The circuit comprises: a multi-master multi-slave routing arbitration architecture and an interconnection component, wherein a multi-core processor is connected to the multi-master multi-slave routing arbitration architecture, and the multi-master multi-slave routing arbitration architecture is connected to an embedded FPGA by means of the interconnection component. The multi-master multi-slave routing arbitration architecture is used for performing identification and routing arbitration on data transmission inside the multi-core processor or between the multi-core processor and the embedded FPGA, and allocating corresponding interconnection resources for the data transmission, wherein the interconnection resources are implemented on the basis of the interconnection component. The interconnection component is used for managing and transmitting communication between interfaces connected by the interconnection component, wherein the interfaces are interfaces on the multi-core processor side and / or interfaces on the embedded FPGA side. The present application realizes real-time, reliable and efficient interconnection between a multi-core processor and an embedded FPGA, and can reduce the requirements for hardware resources and reduce the size of a system on a chip.
Owner:BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD

A galvanometer laser control method and control device based on multi-core processor integration

The application discloses a galvanometer laser control method and device based on multi-core processor integration, which comprises the following steps: step one: the first core CPU0 initiates the second core CPU1, and opens up a dual-core shared memory area for both; step two: the CPU1 establishes a communication connection with the upper computer, and writes preset default running parameters into the board card; step three: the CPU1 receives and analyzes a graphic file sent by the upper computer, and stores the graphic file into the shared memory; after the CPU0 reads the data, the data is sent to a galvanometer driving module after interpolation preprocessing; and step four: the CPU0 controls a laser switch and a galvanometer deflection in real time, so that a laser beam scans and projects according to a graphic track. The method adopts a division structure of'main core focusing on real-time control and slave core bearing communication interaction', effectively solves the multi-task parallel bottleneck of the single-core scheme, significantly improves the control precision and response speed, and realizes high-precision and high-real-time laser projection control.
Owner:LIGHTVISION TECH LTD

Multi-core computing method and device for fusing column block TSQR and tile update QR decomposition

PendingCN122364620AComputational scienceBinary tree
This invention discloses a multi-core computing method and apparatus for QR decomposition that integrates column-block TSQR and tile update. The method includes: for a large-scale matrix to be decomposed, horizontally dividing it into blocks based on the number of cores in the multi-core processor, and further dividing the large-scale matrix into multiple layers according to the tile update method; constructing a multi-stage pipeline with a binary tree structure, performing parallel triangular decomposition on the initial layers of the large-scale matrix through the multi-core processor to obtain the corresponding upper triangular matrix and orthogonal matrix; replacing the original layer block matrix with the upper triangular matrix, performing conjugate transpose on the orthogonal matrix to obtain the update matrix, and implementing parallel updates for the remaining layers through the multi-core processor; based on the reflection vector implicitly stored by the multi-core processor during the parallel triangular decomposition process, solving for the overall orthogonal matrix corresponding to the large-scale matrix, and simultaneously outputting the overall upper triangular matrix obtained after layer update. This invention can realize QR decomposition of large-scale matrices.
Owner:10TH RES INST OF CETC

Multi-core processor and method for allocating system shared resources

A multi-core processor and a method for allocating system cache resources, which relate to the field of computers. The multi-core processor comprises a plurality of processor cores, a controller, and system shared resources, wherein the plurality of processor cores are used for respectively generating indication signals and transmitting the indication signals to the controller, each indication signal being used for indicating the degree of importance of a thread running in the respective processor core; and the controller is used for selectively allocating the system shared resources to the plurality of processor cores on the basis of the indication signals from the processor cores. The multi-core processor provided in the solution can reduce the power consumption of the multi-core processor and improve an operating rate.
Owner:HUAWEI TECH CO LTD

PXIe high-speed data zero-copy processing and real-time streaming disk method for domestic multi-core processor

PendingCN122450874ATerm memoryEmbedded system
The application discloses a PXIe high-speed data zero-copy processing and real-time streaming disk method for a domestic multi-core processor and relates to the technical field of PXIe bus data processing and storage. The VFIO technology is used to realize user space mapping of a DMA buffer, and zero-copy data transmission is completed in combination with 2MB large page memory; the AMP mode is used to divide multi-core control surfaces and data surfaces, and the multi-core scheduling is optimized by using a lock-free queue, core-interrupt affinity processing; the streaming disk link bypasses a file system through bare I / O, and massive data real-time parallel streaming disk is realized in combination with io_uring asynchronous I / O, a pre-allocated memory pool and a lock-free producer-consumer model. The application eliminates the performance bottleneck of each link of data processing, fully utilizes the parallel advantages of the 16GB / s high bandwidth of the PXIe bus and the domestic multi-core processor, adapts to the national production software and hardware system, and improves the real-time performance and throughput of data processing.
Owner:CHENGDU CHANGBO INSTR CO LTD

Method for task execution control in a processor system and task execution control

A processor system comprises a single-core processor having a single processor core or a multi-core processor having a plurality of processor cores and a real-time operating system, wherein the real-time operating system comprises a task system having tasks. The processor system has software components which are executable on one or more processor cores and by which functions associated with a control unit are implemented. In response to detection of an initialization request, the task system is switched to a delay mode such that at least the tasks having the lowest execution priority of the execution priorities are not executed for a subsequent predetermined initialization period. During the predetermined initialization period, a corresponding initialization task is executed on the single processor core or on selected or all processor cores (Core1, Core2), by means of which initialization task all or a substantial part of the program variables of the software components (SWC) of the affected processor core are converted to a predetermined state. After the end of the predetermined initialization period, the task system is switched back to a normal operating mode.
Owner:SCHAEFFLER TECHNOLOGIES AG & CO KG

Consistency test method, device, storage medium, test equipment and program instructions

The application provides a consistency test method and device, a storage medium, test equipment and program instructions, and relates to the field of chip testing. A plurality of operation units are allocated in the memory, and each operation unit is only allowed to be modified by a single core of a multi-core processor at the same time. On this basis, the numerical values in the operation units are iteratively updated according to the recursive relationship between the operation units, so that the multi-core processor loads the numerical values of different operation units into the corresponding cache lines during execution. After the iteration is completed, the actual numerical values in the operation units are compared with the theoretical numerical values calculated based on the general formula. In this way, since the recursive calculation relies on reading and writing across operation units, a data dependency relationship is formed between some cache lines, so that the test process is no longer limited to the inside of a single cache line, but covers the dependency relationship between a plurality of to-be-tested cache lines, effectively testing the data synchronization capability across cache lines in a multi-core environment.
Owner:广东鸿钧微电子科技有限公司

Retry mechanism verification system and method

This invention provides a verification system and method for a retry mechanism, relating to the field of multi-core processor interconnect bus protocol verification technology. The system includes: at least one master node monitoring device, a central coprocessor, and at least one request node agent. The master node monitoring device collects real-time operating status signals from within the master node and generates a retry prediction information packet containing the predicted retry event type and retry prediction value. The retry prediction value indicates the future time of the predicted retry event. The central coprocessor calculates the request sending delay based on the retry prediction value and generates a request policy packet containing the delay, which is sent to the request node agent. After the request sending delay, the request node agent sends a request sequence to its bound request node to trigger the retry event. This invention improves the efficiency and scenario coverage of the verification method by predicting the retry event occurrence time and precisely controlling the timing of stimulus transmission accordingly.
Owner:BEIJING VCORE TECH CO LTD

Method for Improving Efficiency of Multi-Core Processor Systems

PendingUS20260178111A1Digital data processing detailsConvertersMulti-core processor
A method includes configuring a plurality of power converters to provide power to a plurality of processor cores, wherein each power converter of the plurality of power converters is connected to a corresponding processor core, and in response to a system command, configuring at least one of the plurality of power converters to leave a first operating mode and enter a second operating mode to reduce a leakage current flowing through a processor core connected to the at least one of the plurality of power converters.
Owner:REED SEMICON CORP

Prefetch dynamic control based on prefetch accuracy in a computing system

Disclosed are prefetch dynamic control based on prefetch accuracy in a computing system, and related methods and computer-readable media. The computing system includes a processor including one or more central processing unit (CPU) cores each having an associated cache memory. The CPU cores are configured to generate a value indicative of a prefetch accuracy of the CPU cores, the prefetch accuracy being for prefetching data, instructions, or both data and instructions from a system memory external to the processor to store in the cache memory for the CPU cores, and to control the prefetching by the CPU cores based on the value indicative of the prefetch accuracy. In this way, when the prefetch accuracy is less than a particular threshold, the number of memory access requests for prefetching is reduced, which in turn relieves memory bandwidth contention, particularly in a multi-CPU core processor.
Owner:AMPERE COMPUTING LLC

A multi-core processor-based multi-mode industrial data acquisition method and system

This invention discloses a multi-mode industrial data acquisition method and system based on a multi-core processor; it relates to the field of industrial data acquisition technology; it effectively improves the multi-core allocation capability of a multi-core processor for acquiring multi-mode industrial data; this invention sets up acquisition multi-modality and obtains the modal multi-core requirement value of the acquisition multi-modality; then, based on the analysis of the modal multi-core requirement value, it groups the multi-core processor to obtain multi-core processing units; and sets up a multi-core allocation mechanism for the multi-core processing units; it obtains multi-mode acquisition instructions, and based on the multi-core allocation mechanism, the multi-core processing units acquire multi-mode industrial data through the multi-mode acquisition instructions; it performs time dimension alignment processing on the multi-mode industrial data to obtain a time dimension modal industrial data sequence; and then analyzes the time dimension model industrial data sequence to obtain abnormal industrial data.
Owner:LOGOSDATA

A queue-based control word output feedback control method

ActiveCN116701021BOutput in orderControllable outputOrder controlControl engineering
The application discloses a queue-based control word output feedback control method, relates to the technical field of multi-core processor task output management, and comprises the following steps: firstly, sequentially writing ordered control words output by a task scheduling unit into an Exit queue, determining the number of in-queue control words, secondly, sequentially outputting the control words in the Exit queue, recording the number of out-of-queue control words, recording and writing the control words into an auxiliary queue if the output fails, when the number of in-queue control words in the Exit queue is equal to the number of out-of-queue control words, performing the next step, sequentially outputting control words in a Subexit queue and a Waitexit queue, marking the loop output control words, writing the control words into an Interrupt queue if the number of marks reaches a set threshold, otherwise, continuously outputting the control words, finally, performing data protection, task revocation or remapping operation according to error feedback types, and completing the control word output work; the method makes the task output more orderly, controllable and efficient through a specific control word output mechanism, and further improves the system working efficiency.
Owner:HEFEI UNIV OF TECH

Sparse triangle decoupling parallel acceleration method and system for large-scale sparse linear equation set in chip simulation

The invention provides a sparse triangular decoupling parallel acceleration method and system for a large-scale sparse linear equation set in chip simulation, and the method comprises the steps: firstly constructing a directed dependency graph based on a non-zero structure, and completing the segmentation of an initial task; recursively applying nested subdivision to the sub-problems of which the scales exceed a preset threshold value; and meanwhile, a top-down greedy merging mechanism is introduced, and sub-problems with too small scales are aggregated. The generated sub-problems are completely decoupled and can be executed independently and parallelly, and the maximum sub-problem scale is far smaller than that of the original problem. In addition, all dependency analysis results and task division schemes can be reused across right-end terms, on the premise that the non-zero structure of the coefficient matrix is kept unchanged, one-time preprocessing can support any multiple solving tasks, and preprocessing overhead is obviously reduced. According to the scheme, on the basis that the solving precision of a direct method is completely reserved, the parallel computing potential of the multi-core processor is fully released, and the high-throughput and low-delay linear equation set solving capacity is provided for super-large-scale chip simulation.
Owner:SHANGHAI LIXIN SOFTWARE TECH CO LTD

I / O boards that meet the OpenVPX standard

PendingCN122285599ACoprocessorResource assignment
This invention belongs to the field of computer communication technology and discloses an I / O board conforming to the OpenVPX standard, including a baseboard, a processor module, a distributed monitoring module, and a management and scheduling module. The processor module is mounted on the baseboard and includes an FPGA coprocessor and a multi-core ARM processor connected to the FPGA coprocessor. The distributed monitoring module includes a baseboard management controller and multiple monitoring sensors connected to the baseboard management controller. The management and scheduling module runs on the multi-core ARM processor and is connected to the baseboard management controller, used to adjust task priorities, resource allocation, and task scheduling strategies based on the monitoring information transmitted by the baseboard management controller. This invention achieves significant technological advancements in three dimensions—task collaborative processing, system reliability, and intelligent health management—by introducing a management and scheduling module, a distributed monitoring module, and a task scheduling and health status linkage mechanism.
Owner:XIAN JUXIN WANHE ELECTRONIC INFORMATION TECH CO LTD

Virtualization method, device, board card and computer-readable storage medium

The present disclosure provides a virtualization method, a system, an electrical device and a computation apparatus based on a multi-core processor. The computation apparatus is included in a combined processing apparatus, which also includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computation operations specified by the user. The combined processing apparatus also includes a storage apparatus, which is respectively connected to the computation apparatus and other processing apparatuses and is used for storing data of the computation apparatus and other processing apparatuses.
Owner:ANHUI CAMBRICON INFORMATION TECH CO LTD