The invention provides a JTAG (joint test action group) debug method of a multi-core processor. A multichannel test interface controller is connected between a standard test access port controller and a simulator JTAG debug interface of every processor core. The debug method comprises the following steps that: firstly, a system is electrified, and the functional state machine of the multichannel test access port controller enters the state of test logic reset; secondly, a debug command is sent, and specific TCK (testing clock), TDI (testing data input) and TMS (testing method select) signals are output through the simulator JTAG debug interface, so that state control modules enter states in sequence; thirdly, selective signals are sent, and a control register is configured; fourthly, after one-clock cycle of delay, the information in the control register is loaded to a state register; and fifthly, after finishing the selection of the processor cores, the debug command is sent, and the debug procedure of a single-core processor is carried out. The invention effectively completes the selection and the control of every processor core and the storage and the feedback of debug information, so that the reliability is promoted.