205 results about "Single-core" patented technology

The invention discloses a method for improving deformation uniformity of a core wire of an NbTi superconducting wire, and belongs to the technical field of superconducting wire processing. The method comprises the following steps: performing deep hole drilling on an oxygen-free copper ingot rod, then assembling, welding and extruding the oxygen-free copper ingot rod and a single-core rod to obtain a composite rod, and performing multi-pass drawing on the composite rod to obtain the NbTi superconducting wire with high performance, low loss and high N value. The Jc of the prepared NbTi superconducting wire is 2880-3120 A / mm < 2 >, the loss is 450-550 mJ / cm < 3 >, the N value is 70-95, compared with a superconducting wire prepared through a conventional process, the N value is remarkably increased, the loss is remarkably reduced, the critical current density is increased, and the NbTi superconducting wire has wide application prospects in MRI magnets.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

According to the manufacturing method of the three-dimensional wound iron core and the three-dimensional wound iron core, the silicon steel material and the amorphous material for preparing the iron core are firstly obtained, then the two materials are cut to obtain the silicon steel strip-shaped material and the amorphous strip-shaped material, then the silicon steel iron core frame with the embedded structure is wound by the silicon steel strip-shaped material, and the silicon steel iron core frame with the embedded structure is manufactured. And the amorphous iron core frame is wound by the amorphous strip-shaped material, and the frame edge width of the amorphous iron core frame is matched with the width of the embedded structure. And then, the two iron core frames are subjected to annealing treatment, the annealed silicon steel iron core frame and amorphous iron core frame are spliced to obtain an iron core single frame, then the iron core single frame is spliced and cured, and the three-dimensional wound iron core is obtained. The characteristics of the silicon steel material and the amorphous material are combined, the advantages of the silicon steel material and the amorphous material are complementary, the three-dimensional wound core has good mechanical performance and no-load performance at the same time, and the overall performance of the transformer is improved.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

The invention provides a rapid calculation and prediction method, device, equipment and medium for a soft melting zone of a blast furnace, and the method comprises the following steps: collecting blast furnace operation data, carrying out standardization processing, dynamically establishing a geometric model, constructing simulation models of grids with different resolutions, and carrying out hierarchical solving based on a historical sample matching condition to realize efficient prediction. When the matching degree is insufficient, the first resolution grid is adopted to quickly calculate and generate first interpolation data, when the matching degree is between basic matching and complete matching, second interpolation data is acquired in real time through the matching sample, the first or second interpolation data is mapped to the second resolution grid to be initialized, accurate calculation is carried out, and the first interpolation data and the second interpolation data are obtained. Fast and accurate calculation adopts a gas-solid single-core interaction parallel partitioning strategy to accelerate solution, a matching working condition result is directly reused when the matching degree meets complete matching, a calculation result and a standardized parameter are synchronously stored in a historical sample library, and data clustering matching and visual output are realized; the method effectively supports blast furnace smelting state monitoring, operation optimization and stable and smooth operation.

The utility model relates to the technical field of cable installation and arrangement, and discloses a single-core indoor and outdoor cold shrinkage terminal head, which comprises an insulating tube, a supporting core rope is arranged in the middle of the insulating tube, a sealing ring is fixedly connected to the periphery of the insulating tube, a rubber sleeve is fixedly connected to the middle of the sealing ring, a sleeve is fixedly connected to the middle of the insulating tube, and the rubber sleeve is fixedly connected to the middle of the sleeve. A sealing film is fixedly connected to the middle of the sleeve, a sliding pipe is connected to the middle of the sleeve in a sliding mode, a clamping assembly is installed in the middle of the sleeve and comprises a supporting clamping ring, and the supporting clamping ring is fixedly connected to the middle of the sleeve. According to the utility model, firstly, the insulating tube is sleeved on the cable joint, and after the supporting core rope is pulled and drawn away, the rubber sleeve is pressed, so that the supporting ring is pushed, the sliding tube on the supporting ring can be inserted into the sleeve and the sealing film is punctured, and then the stability and the service life of the cold shrink terminal after installation are ensured under the filling and adhesion of glue.

The invention discloses a data processing method for cloud computing based on artificial intelligence, and relates to the technical field of cloud computing, and the method comprises the steps: 1, in each time slice, a gateway counts parameters of a new request, carries out the normalized entropy-density evaluation of the parameters, and records the maximum entropy-density of the new request; 2, the scheduler divides a new to-be-requested data stream into a plurality of fragments according to content boundaries, and fragment-node mapping pressure is calculated; 3, continuously monitoring the difference between the global request arrival rate and the single-core service rate, and predicting the completion time of the task corresponding to the fragment in combination with the peak computing power of the target node GPU, the bus bandwidth and the current queue depth; and step 4, dynamically adjusting the maximum inbound rate of the next time slice by the gateway so as to restrain the tail delay while keeping the throughput stable. According to the method, the processing quality and the system robustness of the complex data in the dynamic environment are remarkably improved.

The present invention provides: a MgB2 superconducting wire that has a barrier layer of highly uniform thickness covering a MgB2 core and that reduces MgB2 filament defects and is suitable for thinning and lengthening; a MgB2 superconducting wire manufacturing method for manufacturing the same; a superconducting coil using the same; and a magnetic generator including the superconducting coil. A MgB2 superconducting wire (200) comprises: a core material (210); a MgB2 filament (220) in which a MgB2 core (221) is covered with a barrier layer (222); and a metal sheath (230). The MgB2 filament (220) has a barrier layer (222) thickness on the outer peripheral side of the wire not more than three times the barrier layer (222) thickness on the core side of the wire. The method for manufacturing the MgB2 superconducting wire includes a step for forming a single core wire, a step for forming an embedded material, a surface reduction processing step, and a heat treatment step. The embedded material is formed by arranging the single core wire in a recess formed in the outer surface of the core material or by incorporating a spacer in a gap.

A technique for optimizing attention mechanism computations in transformer-based language models improves computational efficiency during both prefill and decode phases. The approach unequally partitions attention operations across multiple streaming multiprocessors of a hardware processing unit (e.g., such as a graphics processing unit, or GPU) to maximize hardware utilization. By leveraging the associative property of online softmax calculation as a reduction operation and employing stream-K style decomposition, the technique enables parallelization across all modes of the attention matrix, including the context length dimension. This allows for efficient distribution of computational workload across available GPU resources while ensuring equal total work allocation. The approach delivers significant speedup over existing methods, particularly for long context lengths, by maintaining near 100% GPU occupancy through optimal workload distribution and single-kernel execution.

An optical module capable of improving connection reliability is provided. [Solution] The optical module (10) includes an optical component (40) having a single core (51) and an optical waveguide (30) having multiple cores (32) optically coupled to the single core (51) by adiabatic coupling. The optical module (10) includes cladding layers (33, 52) that separate the single core (51) from the multiple cores (32) in the Z-axis direction. The optical component (40) is a separate component from the optical waveguide (30). The single core (51) and the multiple cores (32) are arranged so as to be optically coupled from the single core (51) to the multiple cores (32). The multiple cores (32) are arranged side by side along the X-axis direction. The single core (51) and the multiple cores (32) have overlapping regions in the Y-axis direction where they overlap. A first separation distance (L1) between two adjacent cores (32) along the X-axis direction is equal to or greater than a second separation distance (L2) between the single core (51) and the multiple cores (32) along the Z-axis direction.

The utility model provides a single iron core measures ac leakage current system, it has solved leakage current detection circuit cost higher problem, it includes power module, power module is connected with measurement circuit and MCU module, measurement circuit has two groups of operational amplifier follower, one group of operational amplifier follower is connected through sampling resistance R9 with the one end of the measurement coil that is wound on annular core, the other end of measurement coil is connected through another group of operational amplifier follower with the PWM pin of MCU module, the ADC pin of MCU module is connected on sampling resistance R9. The utility model has good leakage detection effect, lower cost and the like advantages.

Provided is a gateway device provided between a control device that controls at least one first user terminal that performs single-core bidirectional transmission and at least one second user terminal that performs two-core transmission. The gateway device comprises: a plurality of main signal control signal multiplexing / demultiplexing units that demultiplex an input optical signal into at least main signal light and control signal light; and a plurality of control signal transceivers that transmit and receive control signal light between the at least one user terminal and the at least one second user terminal via at least one of the plurality of main signal control signal multiplexing / demultiplexing units. Each of the plurality of control signal transceivers includes an output unit that outputs uplink control signal light transmitted from the at least one first user terminal or the at least one second user terminal to an optical reception unit.　

The invention relates to the technical field of electronic information, and discloses a task scheduling method, device and equipment for a pet necklace, a storage medium and a computer program product, the method is applied to the pet necklace with a dual-core processor, and the dual-core processor comprises a first core and a second core; according to the method, a Bluetooth protocol stack and a communication task are allocated to a first core, a timing acquisition task and an inference task are allocated to a second core, and compared with a mode that all tasks share one core in traditional single-core polling scheduling, the running conflict of the tasks on the same core is avoided from the hardware resource allocation level; meanwhile, an event group corresponding to a task is set, and a corresponding event bit in the event group is set through an interrupt service program when peripheral interrupt is triggered, so that task blockage is relieved; and through the technical means of querying the event bit state after setting in the task context and triggering the corresponding task scheduling, the accurate triggering and ordered execution of the task scheduling are realized.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

The utility model discloses a new energy automobile battery swap station's PCB board 4 pin film capacitor, including plastic shell and the capacitor body of encapsulation in plastic shell, capacitor body includes the capacitor core that is composed of multiple single core and the laminated busbar that is connected with capacitor core through soldering tin, and the laminated busbar is connected with two outgoing terminals, and each outgoing terminal has two parallel interval opposite pins and the connecting portion of connecting two pins, and the connecting portion is integrally formed with two pins and is combined into U shape, and the pin stretches out plastic shell outside, and the connecting portion of each outgoing terminal is welded and connects the laminated busbar. Through setting laminated busbar, U type outgoing terminal, multiple core combination arrangement capacitor core in the inside of plastic shell, the soldering connection process that laminated busbar is used with electric core, makes capacitor presents high stable ESL, ESR parameter on high frequency resonance road, and the current capacity of capacitor improves self heating little, and circuit output high quality steady voltage waveform.

This invention discloses an adaptive filtering method based on the multi-kernel Nystrom method, belonging to the field of kernel adaptive filtering. The multi-kernel Nystrom method combines multiple kernel functions, which can include not only Gaussian kernels but also other different kernel functions, mapping the original data to multiple different independent feature spaces. Compared with the traditional single-kernel Nystrom method, the multi-kernel Nystrom method has better filtering accuracy and becomes less sensitive to the choice of kernel parameters. Compared with other multi-kernel adaptive filtering methods, it can significantly reduce computational complexity, time, and memory consumption. Subsequently, this invention introduces the proposed multi-kernel Nystrom method into kernel adaptive filters for the first time. Experiments show that this algorithm can achieve better filtering accuracy than current state-of-the-art kernel adaptive filtering algorithms with relatively low computational complexity.

Embodiments disclosed herein provide for spatially tagged nuclei that are compatible with any genomic or multiomic single cell / nuclei assay to allow generation of a spatially resolved single cell sequencing library with single cell resolution.

The invention provides a method for improving cache refreshing efficiency in a neural network reasoning process. The method comprises the following steps: S1, judging whether a circular traversal operator ends or not; if yes, ending; if not, performing the step S2; s2, judging whether NPU operator is network input; if yes, refreshing a cache for operator input; performing the step S3; if not, performing the step S3; s3, determining whether an NPU operator is network output- If yes, performing the step S4; if not, the step S5 is further carried out; s4, performing cache refreshing on operator output, and further returning to the step S1; s5, judging whether an NPU operator is connected behind a CPU operator or not; if yes, returning to the step S4; if not, the step S6 is carried out; s6, judging whether a CPU operator is connected behind an NPU operator or not; if yes, returning to the step S4; and if not, returning to the step S1. The problem of memory consistency of a single-core processor structure and a neural network processor architecture in reasoning a neural network model is solved.

The invention discloses an IO cross-Die multi-core asynchronous processing method based on NVMeoverFabrics, and the method comprises the steps: building a CPU core resource pool under an NUMA architecture, carrying out the NUMA affiliation judgment in combination with a PCIe slot where a port is located, carrying out the sorting according to the number of CPU core binding queues during the queue creation, and selecting a target core, thereby achieving the balanced scheduling of the CPU cores and the reasonable allocation of the queues. Meanwhile, the NVMeIO processing process is divided into three stages of receiving, data transceiving and state sending which are asynchronously executed by different CPU cores respectively, so that the situation that a single core is occupied for a long time is avoided, and a plurality of queues are supported to share the same core so as to improve the resource utilization rate; and the threads in each stage are bound to the core in the NUMADie to which the port belongs, so that the performance loss caused by cross-Die memory access and PCIeDMA cross-node transmission is reduced.

The invention discloses an electromagnetic interference virtual simulation method for a core particle integrated chip and computer equipment, and the method comprises the steps: extracting the surface current density and electrical characteristic parameters of a certain position in a first core particle model under the working frequency of a first core particle; extracting the surface current density of the same position in the first core particle model under the working frequency of the second core particle; creating a virtual interference source device model of which the working frequency is the same as that of the first core particle outside the two-time distance of the distance between the first core particle and the second core particle, enabling the virtual interference source device model to be close to the surface current density extracted under the condition of the second core particle, and obtaining a corresponding size parameter; and creating a virtual interference source device model corresponding to the size parameter, extracting the surface current density and the electrical characteristic parameter under the working frequency of the first core particle, comparing the surface current density and the electrical characteristic parameter with the condition of a single core particle, and evaluating the performance influence of the first core particle caused by electromagnetic interference. According to the invention, more accurate simulation of performance influence caused by mutual electromagnetic interference of devices with different working frequencies can be realized.

The utility model relates to the field of APC single-core connecting structures, and discloses an APC single-core connecting structure which comprises a male head, the front side of the male head is fixedly connected with a first cavity, the front side of the first cavity is fixedly connected with an operation ring, the outer wall of the operation ring is provided with a plurality of anti-skid blocks, a female head is arranged in the operation ring, and the female head is connected with the first cavity. A second cavity is fixedly connected to the rear side of the female head, the interior of the first cavity is connected with the second cavity through a sealing assembly, a fixing ring is fixedly connected to the front end of the interior of the operation ring, a plurality of positioning grooves are formed in the front side of the fixing ring, and a mounting ring is fixedly connected to the rear end of the second cavity; and a plurality of positioning pins are fixedly connected to the rear side of the mounting ring. According to the sealing device, looseness or displacement in the using process is avoided, stable operation of equipment is guaranteed, external impurities, liquid and the like are prevented from entering the sealing device, and the working efficiency and safety of the equipment are effectively improved for working scenes needing a sealing environment, such as liquid conveying, gas conveying and the like.

The invention relates to the field of embedded systems, in particular to a multi-task shared resource negotiation using method under a single-core embedded processor platform. According to the method, a resource permission management module, a resource permission application module and a resource permission release module are designed, the resource permission management module is used for initializing a shared resource negotiation function, the resource permission application module is used for enabling a task to obtain shared resource use permission, and the resource permission release module is used for enabling the task to release the shared resource use permission. A section of DDR address space is occupied to record shared resource management information, and a timer hardware peripheral of a processor system is called to deal with the overtime abnormal problem. According to the method, management of negotiation conflict resources among the tasks is realized by calling function codes in the tasks, and exception processing is performed by using the timer hardware peripheral of the processor system, so that the sequence of accessing the same resource by a plurality of tasks is ensured, and behavior conflicts among the tasks are avoided.

The application discloses a kind of transmitter chip architecture of ultra-low area high output power, it is related to wireless communication circuit technical field.The architecture includes mutually coupled first single-core oscillator OSC1, second single-core oscillator OSC2, driving voltage synthesis transformer TFM1, power amplifier active core PA, output matching transformer TFM2 and parallel capacitor C1-C6.OSC1 and OSC2 are realized same frequency same phase oscillation by electrical or electromagnetic coupling, TFM1 is matched with C1-C4, and two-way oscillation voltage is superimposed in phase, generates amplitude doubling driving voltage, is directly input PA amplification, and is output after completing impedance matching by TFM2 and C5-C6 again.Compared with traditional oscillator, driving amplifier and power amplifier architecture, the application omits driving amplifier and interstage matching transformer, and the area of core circuit is ≤0.038mm 2 , output power reaches 13dBm, realizes the synergistic optimization of ultra-low area and high output power, and adapts miniaturization, high-performance communication demand.

The present application relates to the technical field of core transfer, in particular to a core storage and transfer box with geological information recording, which solves the problems of the core storage and transfer box, such as the single core adaptation of groove position fixation, the complexity of taking and placing, the damage of core due to transportation movement and collision, the simple concave-convex positioning without locking of stacking, the easy falling of transfer, the easy falling of information sticker outside, the low efficiency and error of checking, etc. The box body structure is internally provided with a lifting adjusting mechanism. The core sample is placed between two groups of limiting plates, the position of the limiting plate is locked by a locking screw, the lateral clamping and fixation of the core is realized, the flexible limiting and clamping of the two ends of the core sample are realized by a blocking plate, the storage of cores with different diameters and different length specifications can be adapted, the versatility is high, the core shaking, collision and damage due to knocking during the transfer process are effectively avoided, and the integrity of the geological core sample is fully protected.

The invention discloses an assembly structure and an assembly method of a split type multi-range pressure sensor, and the assembly structure comprises a connecting base for realizing communication and fixation with an external pipeline, and a housing is installed at the top of the connecting base in a communication manner, so as to ensure the installation, fixation and protection of all internal parts. The multi-range module is connected to the joint of the bottom of the shell and the top of the connecting base in a clamped mode so as to execute pressure detection operation on a medium in the communicating pipeline. Through the split design of the multi-range module, the three core bodies with different ranges are respectively mounted in the independent detection holes, and the independent control of the electromagnetic valve and the intelligent range switching logic of the control mainboard are matched, so that the automatic interval judgment and accurate detection of an unknown pressure medium are realized, the detection accuracy of each range section is ensured, and the detection accuracy of the pressure medium is ensured. And the error problem caused by wide-range adaptation of a single core body is avoided, and meanwhile, the single core body can be independently replaced when the single core body breaks down, so that the maintenance cost is reduced.

Methods and systems for automated double emulsion droplet library generators are described herein. Optimizing the geometry and composition of double emulsion droplets is essential for maximizing their utility in various scientific and industrial applications. The microfluidic method is effective to generate a droplet library, which is useful to optimize droplets. However, monitoring and intervention by a human are necessary to generate droplet library. The disclosure provided herein presents an automated double-droplet library generator that utilizes a fine-tuned object detector and feedback control. The system autonomously produces libraries of single-core double emulsion droplets tailored to user-defined sizes, shell thicknesses, and solute concentrations.

Disclosed in embodiments of the present application are a packet transmission method and a related device. A sending device performs ESP encapsulation on a first data stream to be sent, to obtain a first ESP packet, wherein the first data stream falls within an encryption scope of the first ESP packet, that is, payload and IP information of the first data stream are encrypted and hidden. The sending device generates a first hash value on the basis of the triple of the first data stream and designs a first ESP header of the first ESP packet, so that the first ESP header can carry the first hash value. The first ESP header does not fall within the encryption scope of the first ESP packet, and therefore, a receiving device can allocate the first ESP packet to a corresponding CPU core on the basis the first hash value in the first ESP header upon receiving the first ESP packet. On the basis of such a design method, the receiving device can distribute received ESP packets to corresponding CPU cores, thereby achieving multi-core payload balancing and enabling the overall performance not to be limited by a single-core performance bottleneck.

An optical connector includes an optical waveguide device with a first optical port and a fastening structure. The optical waveguide device is able to implement splitting, combining, demultiplexing, multiplexing, multi core-single core conversion, filtering, reflection, spot size conversion, optical path connection / disconnection, optical path direction conversion, or optical power adjustment. The fastening structure is configured to fasten an optical transmission medium. The first optical port is aligned with and connected to the optical transmission medium in the fastening structure. In this application, the optical connector combines functions such as splitting, combining, demultiplexing, multiplexing, multi core-single core conversion, filtering, reflection, spot size conversion, optical path connection / disconnection, optical path direction conversion, or optical power adjustment with a connector function without changing a size of an existing connector, to reduce a size of an optical module and reduce a board area occupied by the optical module.

The invention provides a priori knowledge-based cyclic redundancy check method, apparatus and device. The method comprises the steps of obtaining original to-be-checked data; performing period division on the original to-be-verified data, and determining the length of a to-be-complemented byte; performing preprocessing according to the original to-be-verified data and the to-be-complemented byte length to obtain intermediate data; obtaining a prior information value according to the length of the byte to be complemented and a preset prior information table; and performing cyclic redundancy check calculation on the intermediate data according to the prior information value to generate a target check result. According to the scheme, the cyclic redundancy check calculation is converted from multi-core to single-core, so that the chip area and logic resources can be saved, and the improvement of the cyclic redundancy check calculation rate and the reduction of power consumption and heat production are realized.

An inverter control device includes a first core configured to execute control calculation logic to calculate a switching pulse-width modulation (PWM) control value by using an analog-to-digital converter (ADC) sampling value for an inverter. The inverter control device further includes a second core configured to execute update logic to store the switching PWM control value in a buffer-data variable; store a value of the buffer-data variable in a previous-data variable; and update a register with the value of the buffer-data variable or the previous-data variable according to an execution state of the control calculation logic. The inverter control device further includes a PWM control circuit configured to output a switching PWM signal to control the inverter, by using a value within the register.