329 results about "Single-core" patented technology

The invention provides a multi-core heterogeneous system-oriented startup deployment and cooperative processing method, which comprises the following steps of: when the system runs, obtaining startup codes after a master core and a slave core are electrified, respectively obtaining mirror image files of Linux and RTOS (Real Time Operating System) on the basis of synchronous running and storage partition, and running the mirror image files on the master core and the slave core after moving the mirror image files; and after the heterogeneous operating system is loaded, generating an interrupt signal based on inter-core interrupt and a corresponding register through a CLINT module in the main core, and realizing data communication between the main core and each slave core based on the interrupt signal and the shared memory. By means of the method, after the system is powered on, the multiple cores can synchronously run the starting codes, and time delay and uncertainty possibly caused by one-by-one starting of the single cores are avoided; communication and data transmission among multiple cores are realized through interruption and memory sharing, the synchronism and consistency of data are ensured, and misjudgment and decision errors caused by data delay and inconsistency are avoided, so that the real-time performance of the system is remarkably improved.

The invention discloses a method for improving deformation uniformity of a core wire of an NbTi superconducting wire, and belongs to the technical field of superconducting wire processing. The method comprises the following steps: performing deep hole drilling on an oxygen-free copper ingot rod, then assembling, welding and extruding the oxygen-free copper ingot rod and a single-core rod to obtain a composite rod, and performing multi-pass drawing on the composite rod to obtain the NbTi superconducting wire with high performance, low loss and high N value. The Jc of the prepared NbTi superconducting wire is 2880-3120 A / mm < 2 >, the loss is 450-550 mJ / cm < 3 >, the N value is 70-95, compared with a superconducting wire prepared through a conventional process, the N value is remarkably increased, the loss is remarkably reduced, the critical current density is increased, and the NbTi superconducting wire has wide application prospects in MRI magnets.

The invention discloses a preparation method of an MgB2 superconducting wire rod and the MgB2 superconducting wire rod, and relates to the technical field of superconduction, and the method comprises the steps: drilling a plurality of installation holes in an oxygen-free copper ingot, and obtaining a porous copper ingot; the Mg foil is arranged in the Nb tube; an Mg rod is inserted into the Nb tube; filling B powder between the Mg rod and the Mg foil to obtain a single-core rod; inserting the single-core rod into the mounting hole to obtain a multi-core composite ingot; carrying out rolling and cold drawing on the multi-core composite ingot to obtain a multi-core MgB2 wire rod; and carrying out heat treatment on the multi-core MgB2 wire rod to obtain the MgB2 superconducting wire rod. The Mg foil is coated between the Nb tube and the B powder, double-area Mg diffusion is formed between the Mg foil and the central Mg rod, preparation of the high-Jc MgB2 wire is facilitated, drilling is conducted on the oxygen-free copper ingot to assemble the multi-core MgB2 wire, and the problem that during secondary assembly, due to the fact that cold combination of all subcomponents is not coordinated, wire core wires deform unevenly is solved.

The invention discloses a preparation method of a multi-core Nb3Sn composite wire and the composite wire. The method comprises the following steps: loading an Nb rod into an oxygen-free copper pipe to obtain a CuNb single-core rod; the CuNb single-core rods and the hexagonal copper core rods are sequentially arranged in a CuMn alloy pipe at intervals to obtain a multi-core CuNb composite sheath, and then the multi-core CuNb composite sheath is machined into a CuNb composite rod; the CuNb composite rod is machined into a CuNb composite pipe; the SnTi alloy bar is loaded into the CuNb composite tube to obtain a sub-component; a hexagonal CuMn subcomponent is obtained through machining; the hexagonal CuMn subcomponent and the SnCu alloy bar are assembled into a Ta tube and then integrally assembled into an oxygen-free copper tube to obtain a composite wire, and the composite wire is processed to obtain the Nb3Sn superconducting wire. CuNb single core rods on the outermost layer are adjusted to be in discontinuous close arrangement, the problem that machining cracking is prone to occurring in the subcomponent preparation stage due to the fact that Cu on the outer portions of the single core rods is little is solved, the deformation consistency of the wire in the composite wire machining stage is further enhanced by using the CuMn alloy on the outer portions of the subcomponents, it is also guaranteed that the wire cannot crack when stretched, and the service life of the wire is prolonged. The fan-shaped SnCu alloy bars are additionally arranged, so that sufficient Sn is ensured when the wire Nb generates Nb3Sn.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

According to the manufacturing method of the three-dimensional wound iron core and the three-dimensional wound iron core, the silicon steel material and the amorphous material for preparing the iron core are firstly obtained, then the two materials are cut to obtain the silicon steel strip-shaped material and the amorphous strip-shaped material, then the silicon steel iron core frame with the embedded structure is wound by the silicon steel strip-shaped material, and the silicon steel iron core frame with the embedded structure is manufactured. And the amorphous iron core frame is wound by the amorphous strip-shaped material, and the frame edge width of the amorphous iron core frame is matched with the width of the embedded structure. And then, the two iron core frames are subjected to annealing treatment, the annealed silicon steel iron core frame and amorphous iron core frame are spliced to obtain an iron core single frame, then the iron core single frame is spliced and cured, and the three-dimensional wound iron core is obtained. The characteristics of the silicon steel material and the amorphous material are combined, the advantages of the silicon steel material and the amorphous material are complementary, the three-dimensional wound core has good mechanical performance and no-load performance at the same time, and the overall performance of the transformer is improved.

Provided in the present application are a method and apparatus for solving an IPSec elephant flow on the basis of a DPDK. The method comprises: on the basis of a configuration file, initializing a CPU0 and a CPU1 into PMD thread cores, and initializing CPU2-CPU4 into encryption / decryption engine operation cores, creating lock-free rings for communication between the PMD thread cores and the encryption / decryption engine operation cores, and establishing a network card sending queue and a network card receiving queue; the PMD thread cores regularly executing polling operations, acquiring messages, detecting an elephant flow and a common flow, performing load balancing on the elephant flow, and distributing the messages to the encryption / decryption engine operation cores; and encrypting / decrypting the messages in the encryption / decryption engine operation cores, then sending the messages to the CPU1 for sorting, and then sending the messages to the network card sending queue. In this way, the detection of an elephant flow is realized, and multi-core IPSec encryption / decryption is performed on the elephant flow to solve the performance bottleneck of a single-core processor. The present application can be applied to wider application scenarios.

The invention discloses a superconductive single-core rod surface quality optimization and rapid forming process. The superconductive single-core rod surface quality optimization and rapid forming process comprises the steps that a superconductive single-core rod is straightened through a horizontal straightening roller and a vertical straightening roller; the laser detection equipment carries out straightening detection on the superconducting single core rod; the laser meter counter and the fixed-length cutting equipment are used for carrying out fixed-length cutting on the superconducting single-core rod; the stripping die is used for stripping the superconducting single-core rod; and polishing equipment arranged in the same axial direction of the production line is used for polishing and repairing the superconducting single-core rod. By improving straightening and automatic fixed-length cutting-off, the non-straightness of the single core rod is improved, the scaling procedure is facilitated, meanwhile, the procedure of manual straightening after fixed-length cutting-off in the original process is avoided, the surface quality of the single core rod is improved, impurities brought into the surface of the single core rod and the defects caused by slight collision are basically eliminated, and the production efficiency is improved. The production efficiency is improved, and the good surface quality of the single core rod can be guaranteed.

The invention discloses a method and device for calling a kernel function by a Triton operator and electronic equipment, and relates to the technical field of artificial intelligence. The method comprises the steps that a runtime structure of a Triton operator is constructed, if a kernel function is called for the first time and is a single core, the kernel function is compiled through JITFunction, if the kernel function is called for the first time and is a multi-core, compiling parameters with the best overall performance are obtained through overall adjustment, if the kernel function is not called for the first time, the kernel function is obtained through a mapping table in LibEntry, and if the kernel function is called for the second time, the kernel function is called for the first time and is a multi-core. Compilation parameters and corresponding kernel functions or optimal compilation parameters and corresponding kernel functions are written in the mapping table. Practice shows that according to the scheme provided by the invention, the end-to-end time overhead can be reduced by about 70% in small-scale function calling. Moreover, the parameter tuning space of the multi-core operator is expanded through a global tuning mode, the degree of freedom of configuration parameters is improved, and the calculation efficiency of reduction operators is improved.

The invention discloses a composite busbar type flexible direct current capacitor, and relates to the field of capacitors. A vibration reduction connecting piece is arranged between a busbar and a capacitor core, so that the impact resistance and vibration resistance of the capacitor core are improved, impact force can be dispersed to part of the core or a single core, the impact force is eliminated through the vibration reduction connecting piece, and the service life of the capacitor is prolonged. And the risk of displacement, fracture or capacitance loss of the core is reduced. A current-conducting plate is changed into the busbar arranged at the edge of the shell, and the capacitor cores are divided into a plurality of groups through the extended connecting plates, so that impact force is dispersed and eliminated. The arc-shaped groove is arranged at the joint of the connecting plate and the busbar, so that the breaking risk is reduced, and the reliability of the busbar and the connecting plate is improved. The first thrust elastic piece and the second thrust elastic piece are used for counteracting impact force, and then part of the force is transmitted to the supporting plate and is further counteracted through the external damping device, so that the impact resistance of the capacitor is enhanced. And the adjacent capacitor cores on the connecting plate are connected with other cores through the elastic ropes, so that the impact resistance of the capacitor is enhanced.

To provide high-throughput single-nucleus and single-cell libraries, and methods of production and use.SOLUTION: Provided herein are methods for preparing a sequencing library that includes nucleic acids from a plurality of single cells. In one embodiment, the method includes nuclear or cellular hashing which permits increased sample throughput and increased doublet detection at high collision rates. In one embodiment, the method includes normalization hashing, which aids in estimating and removing technical noise in cell-to-cell variation and increases sensitivity and specificity.SELECTED DRAWING: None

The invention relates to the technical field of processors, and discloses a multi-head attention calculation adaptive allocation method and device for a Transform model, and adaptive allocation is carried out according to obtained key parameters of the model and structural parameters of a target processor. Furthermore, the number of attention heads of a single core group is split by adopting a preset two-power allocation method, and the parallel computing core characteristics of a processor and the specific condition of a model are fully considered, so that the problem of idle computing resources caused by mismatching of the number of attention heads and the number of computing cores in a conventional allocation mode is avoided; the efficient utilization of computing resources is realized, so that the models with different configurations can exert the computing power as much as possible on the target processor. Furthermore, through self-adaptive distribution, calculation of multiple attention heads can be reasonably distributed to each calculation core for parallel execution, the parallel calculation advantage of the processor is fully played, and then the speed of model multi-head attention calculation is effectively improved.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

The invention relates to the technical field of transformers, in particular to a production process of an intelligent on-load voltage regulation three-dimensional wound core transformer, the transformer comprises an oil tank, a three-dimensional wound core, a high-voltage coil, a low-voltage coil and an intelligent on-load voltage regulation switch, the three-dimensional wound core, the high-voltage coil and the low-voltage coil are all arranged in the oil tank, and the three-dimensional wound core is arranged in the three-dimensional wound core. The production process comprises the steps that a three-dimensional wound core is prepared, the three-dimensional wound core is formed by combining three same iron core frames, each iron core frame is formed by stacking multi-stage and multi-layer amorphous alloy belt materials, a core column and a lower iron yoke of each iron core frame are of a closed structure, and an upper iron yoke of each iron core frame is of an open structure; through the arrangement of the opening structure of the three-dimensional wound core, a special three-dimensional wound core winding machine, an argon arc welding machine, a gear mold, a winding framework insulating cylinder and other equipment are not needed in the production process.

The invention provides a rapid calculation and prediction method, device, equipment and medium for a soft melting zone of a blast furnace, and the method comprises the following steps: collecting blast furnace operation data, carrying out standardization processing, dynamically establishing a geometric model, constructing simulation models of grids with different resolutions, and carrying out hierarchical solving based on a historical sample matching condition to realize efficient prediction. When the matching degree is insufficient, the first resolution grid is adopted to quickly calculate and generate first interpolation data, when the matching degree is between basic matching and complete matching, second interpolation data is acquired in real time through the matching sample, the first or second interpolation data is mapped to the second resolution grid to be initialized, accurate calculation is carried out, and the first interpolation data and the second interpolation data are obtained. Fast and accurate calculation adopts a gas-solid single-core interaction parallel partitioning strategy to accelerate solution, a matching working condition result is directly reused when the matching degree meets complete matching, a calculation result and a standardized parameter are synchronously stored in a historical sample library, and data clustering matching and visual output are realized; the method effectively supports blast furnace smelting state monitoring, operation optimization and stable and smooth operation.

The invention discloses an ultra-wideband voltage-controlled oscillator circuit, relates to the technical field of semiconductor integrated circuits, and is used for solving the problems of electromagnetic interference risk, narrow frequency regulation range and relatively high power consumption of a voltage-controlled oscillator in the prior art. Comprising a switched capacitor array, a transformer load switch inductor, a variable capacitor and a cross coupling tube, two ends of the transformer load switch inductor are respectively connected with two ends of the switch capacitor array, and the transformer load switch inductor is connected with the switch capacitor array in parallel; the two ends of the switched capacitor array are respectively connected with a variable capacitor, and the variable capacitors are connected with the cross coupling tube. By adopting the 8-shaped transformer load switch inductor, the output frequency regulation range of the single-core voltage-controlled oscillator is expanded, and the problem of serious frequency disturbance caused by electromagnetic interference to an external circuit module is solved. Compared with other single-core LCVCOs, the multi-core multi-mode LCVCOs have a wider frequency regulation range, and compared with other multi-core multi-mode LCVCOs, the multi-core multi-mode LCVCOs have a smaller area and lower power consumption.

Disclosed in the present application are a preparation method for a bronze-process Nb3Sn superconducting wire, and a superconducting wire. The preparation method comprises: placing a bronze rod into an Nb tube, placing the Nb tube into a bronze tube, and performing rotary swaging, drawing and annealing to prepare a bronze / Nb single core rod; bundling up hundreds of bronze / Nb single core rods in a hexagonal close-packed manner and then coating same with a barrier layer, and then placing the bronze / Nb single core rods into a copper tube to form a final billet; and heating the final billet and then sequentially performing extruding, drawing and intermediate annealing thereon, so as to obtain a bronze-process Nb3Sn superconducting wire having ring-shaped core filaments. By means of the present application, an Nb core filament changes from a solid columnar shape to a hollow tubular shape, thereby increasing the interaction area between Nb and a bronze matrix, increasing the reaction rate of Nb with Sn in the bronze matrix during a phase-formation heat treatment, and shortening the reaction time.

The utility model relates to the technical field of cable installation and arrangement, and discloses a single-core indoor and outdoor cold shrinkage terminal head, which comprises an insulating tube, a supporting core rope is arranged in the middle of the insulating tube, a sealing ring is fixedly connected to the periphery of the insulating tube, a rubber sleeve is fixedly connected to the middle of the sealing ring, a sleeve is fixedly connected to the middle of the insulating tube, and the rubber sleeve is fixedly connected to the middle of the sleeve. A sealing film is fixedly connected to the middle of the sleeve, a sliding pipe is connected to the middle of the sleeve in a sliding mode, a clamping assembly is installed in the middle of the sleeve and comprises a supporting clamping ring, and the supporting clamping ring is fixedly connected to the middle of the sleeve. According to the utility model, firstly, the insulating tube is sleeved on the cable joint, and after the supporting core rope is pulled and drawn away, the rubber sleeve is pressed, so that the supporting ring is pushed, the sliding tube on the supporting ring can be inserted into the sleeve and the sealing film is punctured, and then the stability and the service life of the cold shrink terminal after installation are ensured under the filling and adhesion of glue.

The invention discloses a data processing method for cloud computing based on artificial intelligence, and relates to the technical field of cloud computing, and the method comprises the steps: 1, in each time slice, a gateway counts parameters of a new request, carries out the normalized entropy-density evaluation of the parameters, and records the maximum entropy-density of the new request; 2, the scheduler divides a new to-be-requested data stream into a plurality of fragments according to content boundaries, and fragment-node mapping pressure is calculated; 3, continuously monitoring the difference between the global request arrival rate and the single-core service rate, and predicting the completion time of the task corresponding to the fragment in combination with the peak computing power of the target node GPU, the bus bandwidth and the current queue depth; and step 4, dynamically adjusting the maximum inbound rate of the next time slice by the gateway so as to restrain the tail delay while keeping the throughput stable. According to the method, the processing quality and the system robustness of the complex data in the dynamic environment are remarkably improved.

The invention discloses a wafer cutting method, and relates to the technical field of wafer cutting processing. The wafer comprises a front face and a back face which are oppositely arranged, the front face is provided with a plurality of chip function areas and cutting channel areas located between every two adjacent chip function areas, and the wafer cutting method comprises the steps that a front face protection film is attached to the front face of the wafer; carrying out thinning processing on the back surface of the wafer so that the wafer is thinned to a preset thickness; removing the protective film on the front surface, and pasting a through cutting film on the back surface of the wafer; performing laser grooving treatment on the front surface of the wafer corresponding to the cutting channel region; performing back laser transmission invisible cutting on the wafer subjected to the laser slotting treatment corresponding to the cutting channel region, so that the wafer is divided into a plurality of core particles; and stretching the through cutting film so as to enable two adjacent core particles in the wafer to generate an interval, and carrying out material taking treatment on the core particles. According to the method, the steps are few, the film reversing process from grooving to hidden cutting is omitted, the wafer cutting efficiency can be improved, the fragment rate is reduced, the number of core particles is increased, and the machining cost of a single core particle is reduced.

The embodiment of the invention provides attack detection equipment, method and device and a medium, which are used for solving the problems that a single CPU core cannot be expanded, more computing resources are occupied and the processing efficiency is low in the prior art. For each NetFlow flow, sending the NetFlow flow to a corresponding target flow statistics CPU core according to the source IP and the destination IP in the quintuple of the NetFlow flow and the stored IP address range processed by each flow statistics CPU core; each flow statistics CPU core counts the message number and the byte number of the NetFlow flow of each IP address in the IP address range, carries out DDoS detection, directly completes NetFlow flow summarization and DDoS detection of the same IP address in the flow statistics CPU core, does not need to be transmitted to a single CPU core for summarization, reduces the occupation of computing resources, improves the processing efficiency, and can also carry out core expansion.

The invention discloses a system level event detection and control method of a library operating system, Unikernel is used as a single-core operating system, a traditional monitoring mode needs to use a thread, a monitoring thread and a main thread can perform resource preemption, and execution of a main program is greatly influenced. According to the method, a wireless monitoring mode is adopted, the running state of the Unikernel can be collected and analyzed in real time under the condition that the main thread is not interfered, and the monitoring efficiency and accuracy are improved. An existing stack monitoring mode is not flexible enough, and if an important event exists on a stack, the important event can be monitored through continuous polling. No automatic triggering mechanism is used for informing behaviors on a stack, and controllability is not high. According to the method, a stack monitoring mode based on event driving is constructed, the corresponding callback function can be automatically triggered when the stack changes, the events on the stack can be responded and processed in time, and the flexibility and controllability of stack monitoring are improved.

The invention discloses a single-core cable contact resistance inversion method and system. The method comprises the following steps: acquiring first temperature data and second temperature data of a target cable; establishing a first mapping relation between the second temperature data and the first temperature data to obtain a first inversion model; obtaining first joint equivalent thermal resistance based on the first inversion model; and presetting a first constraint condition, and obtaining the contact resistance of the target cable joint in combination with the first joint equivalent thermal resistance. The contact resistance state of the cable joint can be effectively monitored and evaluated, so that the real-time monitoring of the operation state of the cable is realized. Through accurate temperature data acquisition and establishment of an inversion model, the system can carry out early warning on potential faults of the cable joint, and the problem of overheating caused by overlarge contact resistance is avoided, so that the safety and reliability of cable operation are improved. The method provides powerful technical support for healthy operation of the cable, and has remarkable practical value and market application prospect.

The present invention provides: a MgB2 superconducting wire that has a barrier layer of highly uniform thickness covering a MgB2 core and that reduces MgB2 filament defects and is suitable for thinning and lengthening; a MgB2 superconducting wire manufacturing method for manufacturing the same; a superconducting coil using the same; and a magnetic generator including the superconducting coil. A MgB2 superconducting wire (200) comprises: a core material (210); a MgB2 filament (220) in which a MgB2 core (221) is covered with a barrier layer (222); and a metal sheath (230). The MgB2 filament (220) has a barrier layer (222) thickness on the outer peripheral side of the wire not more than three times the barrier layer (222) thickness on the core side of the wire. The method for manufacturing the MgB2 superconducting wire includes a step for forming a single core wire, a step for forming an embedded material, a surface reduction processing step, and a heat treatment step. The embedded material is formed by arranging the single core wire in a recess formed in the outer surface of the core material or by incorporating a spacer in a gap.

The utility model relates to the technical field of ultrafiltration membrane shells, and discloses an ultrafiltration membrane shell structure of a single-branch-core filter, which comprises an ultrafiltration membrane shell, a first circular through hole is formed in the top end of one side of the ultrafiltration membrane shell, and a water inlet pipe is fixedly connected in the first circular through hole in the top end of one side of the ultrafiltration membrane shell. A second circular through hole is formed in the bottom end of one side of the ultrafiltration membrane shell, and a water outlet pipe is fixedly connected into the second circular through hole in the bottom end of one side of the ultrafiltration membrane shell. The bottom of the driving shaft is fixedly connected with the top of the ultrafiltration membrane assembly, the driving shaft can drive the ultrafiltration membrane assembly to rotate, one side of an inner cavity of the ultrafiltration membrane shell is connected with a sweeping brush, the ultrafiltration membrane assembly can rotate on the surface of the sweeping brush, and the sweeping brush can sweep the surface of the rotating ultrafiltration membrane assembly. Surface impurities are removed, and the service life is prolonged.

Disclosed is a dual-mode single-core oscillator, comprising a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a first capacitor C1, a second capacitor C2, a first inductor L1 to a fifth inductor L5, a first capacitor C1, and a first varactor Var1 to a fourth varactor Var4. The source of the third MOS transistor M3 is connected to the drain of the first MOS transistor, the drain of the third MOS transistor M3 is connected to the drain of the second MOS transistor, and the gate of the third MOS transistor M3 is connected to a third bias voltage input port. According to the oscillator of the present invention, switching between a differential mode and a common mode is achieved in only one oscillator core by means of a switch, and frequency tuning in differential mode and common mode states can be achieved.

The invention provides a man-machine and object multi-core communication method and system based on 5G RedCap and a medium. The method comprises the following steps: monitoring a target man-machine-object multi-core communication system, processing to obtain a communication load capacity index, a data priority index and an equipment performance index corresponding to each single core, further processing to obtain task allocation proportion data corresponding to each single core, and performing performance optimization on the target man-machine-object multi-core communication system to obtain a task allocation proportion data corresponding to each single core. Extracting equipment connection state data and inter-core cooperation characteristic data of the optimized man-machine and object multi-core communication system, processing to obtain a system stability index, processing to obtain a communication quality inspection index according to communication quality characteristic data, processing to obtain a data transmission efficiency index according to data transmission characteristic data, and performing data transmission on the data transmission efficiency index. The method comprises the following steps of: obtaining a system optimization effect evaluation index by combining a system stability index and a communication quality inspection index for processing, and correspondingly adjusting a performance optimization scheme, thereby realizing a 5G RedCap-based man-machine-object multi-core communication technology.

The invention provides a resource scheduling method and device for a data center, and the method comprises the steps: carrying out the initial resource division after an application is started; periodically measuring the number of single-core cycle instructions of the application; calculating a real-time parallelizable proportion value of the application according to the current single-core cycle instruction number and the number of processor cores; according to the real-time parallelizable proportion value, calculating a period instruction number increment value after the application distributes the processor core; and preferentially distributing the processor core to the application with the maximum increment value of the cycle instruction number. Correspondingly, the invention further provides a storage medium and electronic equipment. Therefore, resource management and throughput improvement of the application in the data center can be realized.

The invention provides a heterogeneous multi-core sealing microsystem for satellite-borne on-orbit intelligent calculation and a fusion method, belongs to the field of electrical data processing, and aims at data processing, intelligent reasoning and decision control requirements in a satellite-borne intelligent application scene, a multi-core / single-core scalar, vector and tensor intelligent calculation unit is integrated on a single chip, and the multi-core scalar, vector and tensor intelligent calculation unit is integrated on the single chip. Meanwhile, a real-time efficient calculation scheduling unit is arranged, parallel heterogeneous calculation can be carried out on the premise of a high energy efficiency ratio, and hot backup and protection reinforcement treatment are set at the same time according to the requirements of radiation prevention, cosmic ray prevention and high-energy particle prevention of a satellite-borne scene. The scheme of high performance, small size and small mass is adopted, and the antenna is suitable for satellite-borne application scenes.

A technique for optimizing attention mechanism computations in transformer-based language models improves computational efficiency during both prefill and decode phases. The approach unequally partitions attention operations across multiple streaming multiprocessors of a hardware processing unit (e.g., such as a graphics processing unit, or GPU) to maximize hardware utilization. By leveraging the associative property of online softmax calculation as a reduction operation and employing stream-K style decomposition, the technique enables parallelization across all modes of the attention matrix, including the context length dimension. This allows for efficient distribution of computational workload across available GPU resources while ensuring equal total work allocation. The approach delivers significant speedup over existing methods, particularly for long context lengths, by maintaining near 100% GPU occupancy through optimal workload distribution and single-kernel execution.