254 results about "Single-core" patented technology

The invention discloses a method for improving deformation uniformity of a core wire of an NbTi superconducting wire, and belongs to the technical field of superconducting wire processing. The method comprises the following steps: performing deep hole drilling on an oxygen-free copper ingot rod, then assembling, welding and extruding the oxygen-free copper ingot rod and a single-core rod to obtain a composite rod, and performing multi-pass drawing on the composite rod to obtain the NbTi superconducting wire with high performance, low loss and high N value. The Jc of the prepared NbTi superconducting wire is 2880-3120 A / mm < 2 >, the loss is 450-550 mJ / cm < 3 >, the N value is 70-95, compared with a superconducting wire prepared through a conventional process, the N value is remarkably increased, the loss is remarkably reduced, the critical current density is increased, and the NbTi superconducting wire has wide application prospects in MRI magnets.

The invention discloses a preparation method of a multi-core Nb3Sn composite wire and the composite wire. The method comprises the following steps: loading an Nb rod into an oxygen-free copper pipe to obtain a CuNb single-core rod; the CuNb single-core rods and the hexagonal copper core rods are sequentially arranged in a CuMn alloy pipe at intervals to obtain a multi-core CuNb composite sheath, and then the multi-core CuNb composite sheath is machined into a CuNb composite rod; the CuNb composite rod is machined into a CuNb composite pipe; the SnTi alloy bar is loaded into the CuNb composite tube to obtain a sub-component; a hexagonal CuMn subcomponent is obtained through machining; the hexagonal CuMn subcomponent and the SnCu alloy bar are assembled into a Ta tube and then integrally assembled into an oxygen-free copper tube to obtain a composite wire, and the composite wire is processed to obtain the Nb3Sn superconducting wire. CuNb single core rods on the outermost layer are adjusted to be in discontinuous close arrangement, the problem that machining cracking is prone to occurring in the subcomponent preparation stage due to the fact that Cu on the outer portions of the single core rods is little is solved, the deformation consistency of the wire in the composite wire machining stage is further enhanced by using the CuMn alloy on the outer portions of the subcomponents, it is also guaranteed that the wire cannot crack when stretched, and the service life of the wire is prolonged. The fan-shaped SnCu alloy bars are additionally arranged, so that sufficient Sn is ensured when the wire Nb generates Nb3Sn.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

According to the manufacturing method of the three-dimensional wound iron core and the three-dimensional wound iron core, the silicon steel material and the amorphous material for preparing the iron core are firstly obtained, then the two materials are cut to obtain the silicon steel strip-shaped material and the amorphous strip-shaped material, then the silicon steel iron core frame with the embedded structure is wound by the silicon steel strip-shaped material, and the silicon steel iron core frame with the embedded structure is manufactured. And the amorphous iron core frame is wound by the amorphous strip-shaped material, and the frame edge width of the amorphous iron core frame is matched with the width of the embedded structure. And then, the two iron core frames are subjected to annealing treatment, the annealed silicon steel iron core frame and amorphous iron core frame are spliced to obtain an iron core single frame, then the iron core single frame is spliced and cured, and the three-dimensional wound iron core is obtained. The characteristics of the silicon steel material and the amorphous material are combined, the advantages of the silicon steel material and the amorphous material are complementary, the three-dimensional wound core has good mechanical performance and no-load performance at the same time, and the overall performance of the transformer is improved.

Provided in the present application are a method and apparatus for solving an IPSec elephant flow on the basis of a DPDK. The method comprises: on the basis of a configuration file, initializing a CPU0 and a CPU1 into PMD thread cores, and initializing CPU2-CPU4 into encryption / decryption engine operation cores, creating lock-free rings for communication between the PMD thread cores and the encryption / decryption engine operation cores, and establishing a network card sending queue and a network card receiving queue; the PMD thread cores regularly executing polling operations, acquiring messages, detecting an elephant flow and a common flow, performing load balancing on the elephant flow, and distributing the messages to the encryption / decryption engine operation cores; and encrypting / decrypting the messages in the encryption / decryption engine operation cores, then sending the messages to the CPU1 for sorting, and then sending the messages to the network card sending queue. In this way, the detection of an elephant flow is realized, and multi-core IPSec encryption / decryption is performed on the elephant flow to solve the performance bottleneck of a single-core processor. The present application can be applied to wider application scenarios.

The invention discloses a composite busbar type flexible direct current capacitor, and relates to the field of capacitors. A vibration reduction connecting piece is arranged between a busbar and a capacitor core, so that the impact resistance and vibration resistance of the capacitor core are improved, impact force can be dispersed to part of the core or a single core, the impact force is eliminated through the vibration reduction connecting piece, and the service life of the capacitor is prolonged. And the risk of displacement, fracture or capacitance loss of the core is reduced. A current-conducting plate is changed into the busbar arranged at the edge of the shell, and the capacitor cores are divided into a plurality of groups through the extended connecting plates, so that impact force is dispersed and eliminated. The arc-shaped groove is arranged at the joint of the connecting plate and the busbar, so that the breaking risk is reduced, and the reliability of the busbar and the connecting plate is improved. The first thrust elastic piece and the second thrust elastic piece are used for counteracting impact force, and then part of the force is transmitted to the supporting plate and is further counteracted through the external damping device, so that the impact resistance of the capacitor is enhanced. And the adjacent capacitor cores on the connecting plate are connected with other cores through the elastic ropes, so that the impact resistance of the capacitor is enhanced.

The invention relates to the technical field of processors, and discloses a multi-head attention calculation adaptive allocation method and device for a Transform model, and adaptive allocation is carried out according to obtained key parameters of the model and structural parameters of a target processor. Furthermore, the number of attention heads of a single core group is split by adopting a preset two-power allocation method, and the parallel computing core characteristics of a processor and the specific condition of a model are fully considered, so that the problem of idle computing resources caused by mismatching of the number of attention heads and the number of computing cores in a conventional allocation mode is avoided; the efficient utilization of computing resources is realized, so that the models with different configurations can exert the computing power as much as possible on the target processor. Furthermore, through self-adaptive distribution, calculation of multiple attention heads can be reasonably distributed to each calculation core for parallel execution, the parallel calculation advantage of the processor is fully played, and then the speed of model multi-head attention calculation is effectively improved.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

The invention relates to the technical field of transformers, in particular to a production process of an intelligent on-load voltage regulation three-dimensional wound core transformer, the transformer comprises an oil tank, a three-dimensional wound core, a high-voltage coil, a low-voltage coil and an intelligent on-load voltage regulation switch, the three-dimensional wound core, the high-voltage coil and the low-voltage coil are all arranged in the oil tank, and the three-dimensional wound core is arranged in the three-dimensional wound core. The production process comprises the steps that a three-dimensional wound core is prepared, the three-dimensional wound core is formed by combining three same iron core frames, each iron core frame is formed by stacking multi-stage and multi-layer amorphous alloy belt materials, a core column and a lower iron yoke of each iron core frame are of a closed structure, and an upper iron yoke of each iron core frame is of an open structure; through the arrangement of the opening structure of the three-dimensional wound core, a special three-dimensional wound core winding machine, an argon arc welding machine, a gear mold, a winding framework insulating cylinder and other equipment are not needed in the production process.

The invention provides a rapid calculation and prediction method, device, equipment and medium for a soft melting zone of a blast furnace, and the method comprises the following steps: collecting blast furnace operation data, carrying out standardization processing, dynamically establishing a geometric model, constructing simulation models of grids with different resolutions, and carrying out hierarchical solving based on a historical sample matching condition to realize efficient prediction. When the matching degree is insufficient, the first resolution grid is adopted to quickly calculate and generate first interpolation data, when the matching degree is between basic matching and complete matching, second interpolation data is acquired in real time through the matching sample, the first or second interpolation data is mapped to the second resolution grid to be initialized, accurate calculation is carried out, and the first interpolation data and the second interpolation data are obtained. Fast and accurate calculation adopts a gas-solid single-core interaction parallel partitioning strategy to accelerate solution, a matching working condition result is directly reused when the matching degree meets complete matching, a calculation result and a standardized parameter are synchronously stored in a historical sample library, and data clustering matching and visual output are realized; the method effectively supports blast furnace smelting state monitoring, operation optimization and stable and smooth operation.

Disclosed in the present application are a preparation method for a bronze-process Nb3Sn superconducting wire, and a superconducting wire. The preparation method comprises: placing a bronze rod into an Nb tube, placing the Nb tube into a bronze tube, and performing rotary swaging, drawing and annealing to prepare a bronze / Nb single core rod; bundling up hundreds of bronze / Nb single core rods in a hexagonal close-packed manner and then coating same with a barrier layer, and then placing the bronze / Nb single core rods into a copper tube to form a final billet; and heating the final billet and then sequentially performing extruding, drawing and intermediate annealing thereon, so as to obtain a bronze-process Nb3Sn superconducting wire having ring-shaped core filaments. By means of the present application, an Nb core filament changes from a solid columnar shape to a hollow tubular shape, thereby increasing the interaction area between Nb and a bronze matrix, increasing the reaction rate of Nb with Sn in the bronze matrix during a phase-formation heat treatment, and shortening the reaction time.

The utility model relates to the technical field of cable installation and arrangement, and discloses a single-core indoor and outdoor cold shrinkage terminal head, which comprises an insulating tube, a supporting core rope is arranged in the middle of the insulating tube, a sealing ring is fixedly connected to the periphery of the insulating tube, a rubber sleeve is fixedly connected to the middle of the sealing ring, a sleeve is fixedly connected to the middle of the insulating tube, and the rubber sleeve is fixedly connected to the middle of the sleeve. A sealing film is fixedly connected to the middle of the sleeve, a sliding pipe is connected to the middle of the sleeve in a sliding mode, a clamping assembly is installed in the middle of the sleeve and comprises a supporting clamping ring, and the supporting clamping ring is fixedly connected to the middle of the sleeve. According to the utility model, firstly, the insulating tube is sleeved on the cable joint, and after the supporting core rope is pulled and drawn away, the rubber sleeve is pressed, so that the supporting ring is pushed, the sliding tube on the supporting ring can be inserted into the sleeve and the sealing film is punctured, and then the stability and the service life of the cold shrink terminal after installation are ensured under the filling and adhesion of glue.

The invention discloses a data processing method for cloud computing based on artificial intelligence, and relates to the technical field of cloud computing, and the method comprises the steps: 1, in each time slice, a gateway counts parameters of a new request, carries out the normalized entropy-density evaluation of the parameters, and records the maximum entropy-density of the new request; 2, the scheduler divides a new to-be-requested data stream into a plurality of fragments according to content boundaries, and fragment-node mapping pressure is calculated; 3, continuously monitoring the difference between the global request arrival rate and the single-core service rate, and predicting the completion time of the task corresponding to the fragment in combination with the peak computing power of the target node GPU, the bus bandwidth and the current queue depth; and step 4, dynamically adjusting the maximum inbound rate of the next time slice by the gateway so as to restrain the tail delay while keeping the throughput stable. According to the method, the processing quality and the system robustness of the complex data in the dynamic environment are remarkably improved.

The invention discloses a single-core cable contact resistance inversion method and system. The method comprises the following steps: acquiring first temperature data and second temperature data of a target cable; establishing a first mapping relation between the second temperature data and the first temperature data to obtain a first inversion model; obtaining first joint equivalent thermal resistance based on the first inversion model; and presetting a first constraint condition, and obtaining the contact resistance of the target cable joint in combination with the first joint equivalent thermal resistance. The contact resistance state of the cable joint can be effectively monitored and evaluated, so that the real-time monitoring of the operation state of the cable is realized. Through accurate temperature data acquisition and establishment of an inversion model, the system can carry out early warning on potential faults of the cable joint, and the problem of overheating caused by overlarge contact resistance is avoided, so that the safety and reliability of cable operation are improved. The method provides powerful technical support for healthy operation of the cable, and has remarkable practical value and market application prospect.

The present invention provides: a MgB2 superconducting wire that has a barrier layer of highly uniform thickness covering a MgB2 core and that reduces MgB2 filament defects and is suitable for thinning and lengthening; a MgB2 superconducting wire manufacturing method for manufacturing the same; a superconducting coil using the same; and a magnetic generator including the superconducting coil. A MgB2 superconducting wire (200) comprises: a core material (210); a MgB2 filament (220) in which a MgB2 core (221) is covered with a barrier layer (222); and a metal sheath (230). The MgB2 filament (220) has a barrier layer (222) thickness on the outer peripheral side of the wire not more than three times the barrier layer (222) thickness on the core side of the wire. The method for manufacturing the MgB2 superconducting wire includes a step for forming a single core wire, a step for forming an embedded material, a surface reduction processing step, and a heat treatment step. The embedded material is formed by arranging the single core wire in a recess formed in the outer surface of the core material or by incorporating a spacer in a gap.

The invention provides a resource scheduling method and device for a data center, and the method comprises the steps: carrying out the initial resource division after an application is started; periodically measuring the number of single-core cycle instructions of the application; calculating a real-time parallelizable proportion value of the application according to the current single-core cycle instruction number and the number of processor cores; according to the real-time parallelizable proportion value, calculating a period instruction number increment value after the application distributes the processor core; and preferentially distributing the processor core to the application with the maximum increment value of the cycle instruction number. Correspondingly, the invention further provides a storage medium and electronic equipment. Therefore, resource management and throughput improvement of the application in the data center can be realized.

The invention provides a heterogeneous multi-core sealing microsystem for satellite-borne on-orbit intelligent calculation and a fusion method, belongs to the field of electrical data processing, and aims at data processing, intelligent reasoning and decision control requirements in a satellite-borne intelligent application scene, a multi-core / single-core scalar, vector and tensor intelligent calculation unit is integrated on a single chip, and the multi-core scalar, vector and tensor intelligent calculation unit is integrated on the single chip. Meanwhile, a real-time efficient calculation scheduling unit is arranged, parallel heterogeneous calculation can be carried out on the premise of a high energy efficiency ratio, and hot backup and protection reinforcement treatment are set at the same time according to the requirements of radiation prevention, cosmic ray prevention and high-energy particle prevention of a satellite-borne scene. The scheme of high performance, small size and small mass is adopted, and the antenna is suitable for satellite-borne application scenes.

A technique for optimizing attention mechanism computations in transformer-based language models improves computational efficiency during both prefill and decode phases. The approach unequally partitions attention operations across multiple streaming multiprocessors of a hardware processing unit (e.g., such as a graphics processing unit, or GPU) to maximize hardware utilization. By leveraging the associative property of online softmax calculation as a reduction operation and employing stream-K style decomposition, the technique enables parallelization across all modes of the attention matrix, including the context length dimension. This allows for efficient distribution of computational workload across available GPU resources while ensuring equal total work allocation. The approach delivers significant speedup over existing methods, particularly for long context lengths, by maintaining near 100% GPU occupancy through optimal workload distribution and single-kernel execution.

An optical module capable of improving connection reliability is provided. [Solution] The optical module (10) includes an optical component (40) having a single core (51) and an optical waveguide (30) having multiple cores (32) optically coupled to the single core (51) by adiabatic coupling. The optical module (10) includes cladding layers (33, 52) that separate the single core (51) from the multiple cores (32) in the Z-axis direction. The optical component (40) is a separate component from the optical waveguide (30). The single core (51) and the multiple cores (32) are arranged so as to be optically coupled from the single core (51) to the multiple cores (32). The multiple cores (32) are arranged side by side along the X-axis direction. The single core (51) and the multiple cores (32) have overlapping regions in the Y-axis direction where they overlap. A first separation distance (L1) between two adjacent cores (32) along the X-axis direction is equal to or greater than a second separation distance (L2) between the single core (51) and the multiple cores (32) along the Z-axis direction.

The utility model provides a single iron core measures ac leakage current system, it has solved leakage current detection circuit cost higher problem, it includes power module, power module is connected with measurement circuit and MCU module, measurement circuit has two groups of operational amplifier follower, one group of operational amplifier follower is connected through sampling resistance R9 with the one end of the measurement coil that is wound on annular core, the other end of measurement coil is connected through another group of operational amplifier follower with the PWM pin of MCU module, the ADC pin of MCU module is connected on sampling resistance R9. The utility model has good leakage detection effect, lower cost and the like advantages.

Provided is a gateway device provided between a control device that controls at least one first user terminal that performs single-core bidirectional transmission and at least one second user terminal that performs two-core transmission. The gateway device comprises: a plurality of main signal control signal multiplexing / demultiplexing units that demultiplex an input optical signal into at least main signal light and control signal light; and a plurality of control signal transceivers that transmit and receive control signal light between the at least one user terminal and the at least one second user terminal via at least one of the plurality of main signal control signal multiplexing / demultiplexing units. Each of the plurality of control signal transceivers includes an output unit that outputs uplink control signal light transmitted from the at least one first user terminal or the at least one second user terminal to an optical reception unit.　

The invention relates to the technical field of electronic information, and discloses a task scheduling method, device and equipment for a pet necklace, a storage medium and a computer program product, the method is applied to the pet necklace with a dual-core processor, and the dual-core processor comprises a first core and a second core; according to the method, a Bluetooth protocol stack and a communication task are allocated to a first core, a timing acquisition task and an inference task are allocated to a second core, and compared with a mode that all tasks share one core in traditional single-core polling scheduling, the running conflict of the tasks on the same core is avoided from the hardware resource allocation level; meanwhile, an event group corresponding to a task is set, and a corresponding event bit in the event group is set through an interrupt service program when peripheral interrupt is triggered, so that task blockage is relieved; and through the technical means of querying the event bit state after setting in the task context and triggering the corresponding task scheduling, the accurate triggering and ordered execution of the task scheduling are realized.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

The utility model discloses a new energy automobile battery swap station's PCB board 4 pin film capacitor, including plastic shell and the capacitor body of encapsulation in plastic shell, capacitor body includes the capacitor core that is composed of multiple single core and the laminated busbar that is connected with capacitor core through soldering tin, and the laminated busbar is connected with two outgoing terminals, and each outgoing terminal has two parallel interval opposite pins and the connecting portion of connecting two pins, and the connecting portion is integrally formed with two pins and is combined into U shape, and the pin stretches out plastic shell outside, and the connecting portion of each outgoing terminal is welded and connects the laminated busbar. Through setting laminated busbar, U type outgoing terminal, multiple core combination arrangement capacitor core in the inside of plastic shell, the soldering connection process that laminated busbar is used with electric core, makes capacitor presents high stable ESL, ESR parameter on high frequency resonance road, and the current capacity of capacitor improves self heating little, and circuit output high quality steady voltage waveform.

This invention discloses an adaptive filtering method based on the multi-kernel Nystrom method, belonging to the field of kernel adaptive filtering. The multi-kernel Nystrom method combines multiple kernel functions, which can include not only Gaussian kernels but also other different kernel functions, mapping the original data to multiple different independent feature spaces. Compared with the traditional single-kernel Nystrom method, the multi-kernel Nystrom method has better filtering accuracy and becomes less sensitive to the choice of kernel parameters. Compared with other multi-kernel adaptive filtering methods, it can significantly reduce computational complexity, time, and memory consumption. Subsequently, this invention introduces the proposed multi-kernel Nystrom method into kernel adaptive filters for the first time. Experiments show that this algorithm can achieve better filtering accuracy than current state-of-the-art kernel adaptive filtering algorithms with relatively low computational complexity.

Embodiments disclosed herein provide for spatially tagged nuclei that are compatible with any genomic or multiomic single cell / nuclei assay to allow generation of a spatially resolved single cell sequencing library with single cell resolution.

The invention provides a method for improving cache refreshing efficiency in a neural network reasoning process. The method comprises the following steps: S1, judging whether a circular traversal operator ends or not; if yes, ending; if not, performing the step S2; s2, judging whether NPU operator is network input; if yes, refreshing a cache for operator input; performing the step S3; if not, performing the step S3; s3, determining whether an NPU operator is network output- If yes, performing the step S4; if not, the step S5 is further carried out; s4, performing cache refreshing on operator output, and further returning to the step S1; s5, judging whether an NPU operator is connected behind a CPU operator or not; if yes, returning to the step S4; if not, the step S6 is carried out; s6, judging whether a CPU operator is connected behind an NPU operator or not; if yes, returning to the step S4; and if not, returning to the step S1. The problem of memory consistency of a single-core processor structure and a neural network processor architecture in reasoning a neural network model is solved.

The invention provides an inverse F-type and three-point dual-mode operated voltage-controlled oscillator, which is a single-core oscillator and comprises an active negative resistance transistor pair, a passive inductor group, a frequency regulation module, a first switch group and a second switch group, the passive inductor group and the frequency adjusting module form a passive resonant cavity; when the first switch group is switched on and the second switch group is switched off, the active negative resistance transistor pair is connected with the passive inductor group in a differential form to form an inverse F-type oscillator; and when the first switch group is switched off and the second switch group is switched on, the active negative resistance transistor pair is connected with the passive inductor group in a common-mode parallel mode to form a three-point oscillator. According to the technical scheme provided by the invention, the problem that the impedance peak of the resonant cavity deviates from the preset value due to mismatching between cores in the existing multi-core oscillator is avoided, and the frequency adjustment range of the single-core oscillator is further widened on the basis of low phase noise.

The invention discloses an IO cross-Die multi-core asynchronous processing method based on NVMeoverFabrics, and the method comprises the steps: building a CPU core resource pool under an NUMA architecture, carrying out the NUMA affiliation judgment in combination with a PCIe slot where a port is located, carrying out the sorting according to the number of CPU core binding queues during the queue creation, and selecting a target core, thereby achieving the balanced scheduling of the CPU cores and the reasonable allocation of the queues. Meanwhile, the NVMeIO processing process is divided into three stages of receiving, data transceiving and state sending which are asynchronously executed by different CPU cores respectively, so that the situation that a single core is occupied for a long time is avoided, and a plurality of queues are supported to share the same core so as to improve the resource utilization rate; and the threads in each stage are bound to the core in the NUMADie to which the port belongs, so that the performance loss caused by cross-Die memory access and PCIeDMA cross-node transmission is reduced.

The invention discloses an electromagnetic interference virtual simulation method for a core particle integrated chip and computer equipment, and the method comprises the steps: extracting the surface current density and electrical characteristic parameters of a certain position in a first core particle model under the working frequency of a first core particle; extracting the surface current density of the same position in the first core particle model under the working frequency of the second core particle; creating a virtual interference source device model of which the working frequency is the same as that of the first core particle outside the two-time distance of the distance between the first core particle and the second core particle, enabling the virtual interference source device model to be close to the surface current density extracted under the condition of the second core particle, and obtaining a corresponding size parameter; and creating a virtual interference source device model corresponding to the size parameter, extracting the surface current density and the electrical characteristic parameter under the working frequency of the first core particle, comparing the surface current density and the electrical characteristic parameter with the condition of a single core particle, and evaluating the performance influence of the first core particle caused by electromagnetic interference. According to the invention, more accurate simulation of performance influence caused by mutual electromagnetic interference of devices with different working frequencies can be realized.