31 results about "Single-core" patented technology

The utility model provides a single iron core measures ac leakage current system, it has solved leakage current detection circuit cost higher problem, it includes power module, power module is connected with measurement circuit and MCU module, measurement circuit has two groups of operational amplifier follower, one group of operational amplifier follower is connected through sampling resistance R9 with the one end of the measurement coil that is wound on annular core, the other end of measurement coil is connected through another group of operational amplifier follower with the PWM pin of MCU module, the ADC pin of MCU module is connected on sampling resistance R9. The utility model has good leakage detection effect, lower cost and the like advantages.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

The utility model discloses a new energy automobile battery swap station's PCB board 4 pin film capacitor, including plastic shell and the capacitor body of encapsulation in plastic shell, capacitor body includes the capacitor core that is composed of multiple single core and the laminated busbar that is connected with capacitor core through soldering tin, and the laminated busbar is connected with two outgoing terminals, and each outgoing terminal has two parallel interval opposite pins and the connecting portion of connecting two pins, and the connecting portion is integrally formed with two pins and is combined into U shape, and the pin stretches out plastic shell outside, and the connecting portion of each outgoing terminal is welded and connects the laminated busbar. Through setting laminated busbar, U type outgoing terminal, multiple core combination arrangement capacitor core in the inside of plastic shell, the soldering connection process that laminated busbar is used with electric core, makes capacitor presents high stable ESL, ESR parameter on high frequency resonance road, and the current capacity of capacitor improves self heating little, and circuit output high quality steady voltage waveform.

This invention discloses an adaptive filtering method based on the multi-kernel Nystrom method, belonging to the field of kernel adaptive filtering. The multi-kernel Nystrom method combines multiple kernel functions, which can include not only Gaussian kernels but also other different kernel functions, mapping the original data to multiple different independent feature spaces. Compared with the traditional single-kernel Nystrom method, the multi-kernel Nystrom method has better filtering accuracy and becomes less sensitive to the choice of kernel parameters. Compared with other multi-kernel adaptive filtering methods, it can significantly reduce computational complexity, time, and memory consumption. Subsequently, this invention introduces the proposed multi-kernel Nystrom method into kernel adaptive filters for the first time. Experiments show that this algorithm can achieve better filtering accuracy than current state-of-the-art kernel adaptive filtering algorithms with relatively low computational complexity.

The application discloses a kind of transmitter chip architecture of ultra-low area high output power, it is related to wireless communication circuit technical field.The architecture includes mutually coupled first single-core oscillator OSC1, second single-core oscillator OSC2, driving voltage synthesis transformer TFM1, power amplifier active core PA, output matching transformer TFM2 and parallel capacitor C1-C6.OSC1 and OSC2 are realized same frequency same phase oscillation by electrical or electromagnetic coupling, TFM1 is matched with C1-C4, and two-way oscillation voltage is superimposed in phase, generates amplitude doubling driving voltage, is directly input PA amplification, and is output after completing impedance matching by TFM2 and C5-C6 again.Compared with traditional oscillator, driving amplifier and power amplifier architecture, the application omits driving amplifier and interstage matching transformer, and the area of core circuit is ≤0.038mm 2 , output power reaches 13dBm, realizes the synergistic optimization of ultra-low area and high output power, and adapts miniaturization, high-performance communication demand.

The application provides a concurrent memory database splitting method and relates to the technical field of databases. The ART index is improved to obtain an IART index, and an IARTC algorithm is proposed based on the IART index. The IARTC algorithm uses the IART index as a splitting index to drive database splitting. Meanwhile, a new database splitting concurrent algorithm PIARTC is obtained based on the IARTC algorithm. The PIARTC algorithm controls locking and unlocking of nodes on the IART index through an optimistic lock coupling concurrent strategy to realize concurrent splitting and index updating, so that small locking granularity is maintained in the concurrent execution process. Compared with existing algorithms, the two adaptive indexes proposed by the application have good query performance in single-core and multi-core systems in the case of facing dynamic environments and large-scale data set queries, and still maintain the lightweight characteristics of the original database splitting algorithm.

This invention discloses a fine-grinding device for soft magnetic ferrite cores, relating to the field of soft magnetic ferrite processing technology. The invention includes a cabinet with two symmetrically arranged fixed columns at the top. Two support platforms are fixedly mounted through the outer walls of the tops of the fixed columns. A drive mechanism is mounted on the top of each support platform. An outer grinding wheel is located at the top edge of the cabinet. An electric slide rail is mounted on the top of the inner wall of the cabinet, and a rotating mechanism is slidably mounted inside the electric slide rail. An inner grinding wheel is fixedly mounted at the output end of the rotating mechanism. This invention, through the interaction of the inner and outer grinding wheels, enables magnetic cores of different sizes to automatically complete the grinding of their inner and outer walls during revolution, avoiding the need for multiple grinding and adjustments for a single core, effectively improving the grinding efficiency of the core. Simultaneously, the negative pressure mechanism prevents grinding debris residue and adhesion, avoiding scratches caused by debris.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

The application provides a multi-core chip, an attention processing method and an electronic device. The chip includes a plurality of core particles packaged together, each core particle including a dynamic random access memory, a static random access memory and a computing engine. The computing engine is used to identify the identity of the core particle in the outer loop and load the corresponding local query matrix block. In the inner loop, the key matrix block and the value matrix block in the target core particle are loaded, the attention calculation is performed, and the local calculation result is accumulated to obtain the global result. After the end of the inner loop, the global result is written back to the dynamic random access memory. The application realizes the expansion of attention calculation from a single core particle to a multi-core chip level, aggregates hardware resources of multiple core particles, and improves the calculation efficiency of the attention mechanism in a long context scenario and the utilization rate of chip hardware resources.

This invention relates to the field of 5G NR technology, specifically disclosing a neural network signal processing method and system for 5G NR SDR systems. Addressing the problems of USRP FIFO overflow, difficulty in real-time neural network deployment, and low efficiency of multi-GPU collaboration in existing SDR systems, this invention constructs a multi-threaded PHY processing architecture. The PHY layer is decomposed into independent threads bound to CPU cores, with each thread independently processing all physical channels in a time slot. A GPU task scheduler and GPU pool are designed to achieve asynchronous task submission and intelligent load balancing. Weight preloading, task encapsulation, and a double-buffered weight update mechanism are employed, and asynchronous online training is performed through an asynchronous execution framework. This invention overcomes the single-core CPU bottleneck through time-slot-level parallel PHY processing, reduces multi-threaded concurrency overhead through GPU collaborative scheduling, and achieves uninterrupted real-time inference and continuous adaptation of the neural network through double buffering and asynchronous training, significantly improving channel estimation accuracy and system throughput.

This invention discloses an instruction stacking execution method and a digital signal processor. The method includes the following steps: First, executing a stacked instruction containing an immediate value in the program running on the DSP core; second, during the decoding of the instruction, identifying and marking multiple subsequent instructions as a stack group based on its immediate value; finally, triggering the stacked execution mode, scheduling the instructions within the stack group within a single DSP core, so that their fetch, decode, and execute operations overlap in time. This invention effectively improves the execution efficiency of a single-core DSP for multi-cycle instructions by flexibly triggering the pipeline parallelism of multiple instructions with a single instruction, solving the problem of fixed parallel instructions and inability to adapt to flexible parallel scheduling of batch instructions in existing technologies.

The utility model discloses an iron core distributing device, which belongs to the technical field of sealing ring greasing and comprises a conveying component and a distributing component. The conveying assembly comprises a support and a conveying belt arranged on the support. The conveying belt comprises a feeding end and a discharging end, and a conveying groove used for conveying iron cores is formed in the top of the conveying belt in the conveying direction of the conveying belt. The material distributing assembly is located at the discharging end and comprises a material distributing bottom plate, a material distributing driving assembly arranged on the material distributing bottom plate and a material distributing plate arranged on the material distributing driving assembly. The material distributing plate is located above the discharging end and close to an outlet of the conveying groove, the material distributing plate is provided with a containing groove, the containing groove extends to the side wall, close to the conveying groove, of the material distributing plate, and the two sides of the containing groove are each provided with a clamping groove communicated with the containing groove; the material distributing driving assembly drives the material distributing plate to do reciprocating motion in the transverse direction of the conveying belt. According to the iron core distributing device, iron cores can be conveyed in an end-to-end connection mode, automatic distributing of single iron cores can be achieved, and the iron cores can be clamped automatically and conveniently.

The application discloses a galvanometer laser control method and device based on multi-core processor integration, which comprises the following steps: step one: the first core CPU0 initiates the second core CPU1, and opens up a dual-core shared memory area for both; step two: the CPU1 establishes a communication connection with the upper computer, and writes preset default running parameters into the board card; step three: the CPU1 receives and analyzes a graphic file sent by the upper computer, and stores the graphic file into the shared memory; after the CPU0 reads the data, the data is sent to a galvanometer driving module after interpolation preprocessing; and step four: the CPU0 controls a laser switch and a galvanometer deflection in real time, so that a laser beam scans and projects according to a graphic track. The method adopts a division structure of'main core focusing on real-time control and slave core bearing communication interaction', effectively solves the multi-task parallel bottleneck of the single-core scheme, significantly improves the control precision and response speed, and realizes high-precision and high-real-time laser projection control.

The application relates to the technical field of optical elements, systems or instruments, and more particularly to a multi-core optical fiber cable for a data center, which comprises a central carrier, the outer surface of the central carrier is slidably provided with a plurality of T-shaped sliding blocks, the outer surface of each T-shaped sliding block is symmetrically provided with a clamping structure, the inside of each T-shaped sliding block is provided with a core unit, the outer surface of the central carrier is provided with an elastic buffer layer, a glass cladding layer is arranged between the elastic buffer layer and the central carrier, the outer surface of the glass cladding layer is provided with air holes, the outer surface of the elastic buffer layer is provided with a composite layer, the inside of the composite layer is provided with microcapsules, the outer surface of the composite layer is provided with a water-blocking layer, and the outer surface of the water-blocking layer is provided with an outer sheath. Through the T-shaped sliding block and the clamping structure, independent plugging and 360-degree free rotation of the core unit are realized; when a certain core unit is damaged, only the clamping block needs to be pressed to complete the replacement of the single core unit.

This invention proposes a multi-level optimization execution method and system for a smart contract virtual machine based on the Go language. By constructing a three-level collaborative optimization architecture, it significantly improves execution efficiency and resource utilization. The intermediate code optimization layer integrates automatic vectorization technology with a dynamic profile-guided optimization recompilation mechanism driven by production environment configuration, breaking through the performance bottleneck of the core algorithm. The memory management optimization layer expands the underlying memory pool of the Go language and introduces an application-layer automated pooling mechanism, effectively reducing memory pressure and connection overhead. The instruction scheduling optimization layer combines dynamic time slice adjustment for computationally intensive tasks at the single-core level with optimistic locking concurrent execution technology for multi-core multi-version concurrency control, achieving efficient task collaboration. Through static compilation optimization, dynamic resource adaptation, and a full-process collaborative mechanism, a dynamic balance between high performance and low latency is achieved in scenarios such as encrypted computing and multi-core concurrency, providing a high-performance and highly scalable execution solution for the Go language smart contract virtual machine.

A control / data processor architecture is disclosed which merges data flow with control-flow into a unified control / data flow, enabling thread-level program execution—traditionally bound to a single-core hardware context—to transcend thread, task, and processor boundaries. The architecture supports software-pipelining of entire high-performance computing (HPC) kernels of arbitrary size and complexity, achieving high throughput and instruction-level parallelism. Additionally, the architecture accelerates sparse artificial intelligence workloads with very high sustained throughput and performance per watt.

Accelerating and improved fairness for semaphores is described. In one or more implementations, a computing device includes a plurality of cores and one or more computing resources, exclusive access to which is limited, e.g., to a single core at a time. In one or more implementations, the computing device also includes core selection circuitry configured to identify a first core from the plurality of cores exclusively accessing the one or more limited computing resources and configured to instruct a second core from the plurality of cores to release the exclusive access of the first core to the one or more computing resources.

Accelerating and improved fairness for semaphores is described. In one or more implementations, a computing device includes a plurality of cores and one or more computing resources, exclusive access to which is limited, e.g., to a single core at a time. In one or more implementations, the computing device also includes core selection circuitry configured to identify a first core from the plurality of cores exclusively accessing the one or more limited computing resources and configured to instruct a second core from the plurality of cores to release the exclusive access of the first core to the one or more computing resources.

The utility model relates to the field of injection mold discloses a mold structure of secondary core-pulling of row position, including mutually coordinated front mould and back mould. The front mould includes A board and the inclined guide pillar fixed in A board, the back mould includes B board, male die, row position seat, row position backing plate, shaft shoulder screw, deep hole insert, limit block, reset piece. The structure through shaft shoulder screw, limit block and reset piece cooperation, realize the secondary core-pulling of " first abstracting deep hole insert, later driving row position backing plate to separate", solve the product pull bad problem of traditional single core-pulling because of the big deep hole and insert holding force, improve the qualified rate of deep hole product ejection, and the stable and durable structure reduces the mold maintenance cost.

An operator acceleration method is applied to a computing card, which includes multiple artificial intelligence (AI) cores and global memory. The method includes: acquiring a computational task to be executed, the task information including input data for a scattering operator, at least one source data, and index data corresponding to at least one source data; determining the target core corresponding to each index from the multiple AI cores; and ensuring that indices indicating the same position in the index data correspond to the same target core. Then, the source data corresponding to each index is moved into the target core. A first computational task is executed within the target core based on the moved source data and input data. Subsequently, a second computational task is executed between the target cores based on intermediate results to obtain the operator execution result. This method introduces a core-sharing scheme where the same index corresponds to the same core, ensuring that source data corresponding to indices indicating the same position are preferentially moved to the same AI core for computation, preventing the computing card from degenerating into using a single core, improving multi-core parallelism, and enhancing end-to-end performance.

The application discloses a very light neural network structure for real-time colorectal polyp segmentation of a single-core CPU and a construction method thereof, the structure comprising a five-stage encoder, a five-stage decoder and a skip connection connecting the corresponding level encoder and the decoder; the channel width of the encoder and the decoder is in a trumpet shape from narrow in front to wide in back, and is 8, 16, 48, 64 and 96 in sequence, two enhanced hollow convolution modules are arranged in series in the third stage of the encoder, and a group shuffling fusion module is connected after each stage of the decoder. The overall parameter quantity of the neural network is less than 0.3M, and the typical value is 0.108M or 0.130M. The application can effectively overcome the defects that the existing mainstream model cannot realize real-time high-precision segmentation on a resource-limited single-core CPU platform due to the large volume and complex calculation.

The application relates to the technical field of vehicles and provides a firmware flashing method and system of a vehicle single-core microcontroller and a vehicle-mounted controller. The method comprises the following steps: in response to an upgrade starting instruction sent by an upper computer, performing a background pre-erasing operation on a temporary buffer area, so that all storage units of the temporary buffer area are set to a logic high level state; receiving new firmware data blocks sent by the upper computer in the same sub-sector granularity, and directly writing the data blocks into corresponding positions of the temporary buffer area; after all the data blocks are written, performing a full-amount check on the complete new firmware in the temporary buffer area, and if the check is passed, instructing the MCU to load the new firmware in the temporary buffer area at the next restart; after the new firmware is successfully started and runs, erasing the old firmware in the original firmware running area in the background, and converting the original firmware running area into a new temporary buffer area for next upgrade. The method, system and vehicle-mounted controller provided by the application greatly shorten the user-perceived flashing waiting time.

A processor system comprises a single-core processor having a single processor core or a multi-core processor having a plurality of processor cores and a real-time operating system, wherein the real-time operating system comprises a task system having tasks. The processor system has software components which are executable on one or more processor cores and by which functions associated with a control unit are implemented. In response to detection of an initialization request, the task system is switched to a delay mode such that at least the tasks having the lowest execution priority of the execution priorities are not executed for a subsequent predetermined initialization period. During the predetermined initialization period, a corresponding initialization task is executed on the single processor core or on selected or all processor cores (Core1, Core2), by means of which initialization task all or a substantial part of the program variables of the software components (SWC) of the affected processor core are converted to a predetermined state. After the end of the predetermined initialization period, the task system is switched back to a normal operating mode.

The application provides a consistency test method and device, a storage medium, test equipment and program instructions, and relates to the field of chip testing. A plurality of operation units are allocated in the memory, and each operation unit is only allowed to be modified by a single core of a multi-core processor at the same time. On this basis, the numerical values in the operation units are iteratively updated according to the recursive relationship between the operation units, so that the multi-core processor loads the numerical values of different operation units into the corresponding cache lines during execution. After the iteration is completed, the actual numerical values in the operation units are compared with the theoretical numerical values calculated based on the general formula. In this way, since the recursive calculation relies on reading and writing across operation units, a data dependency relationship is formed between some cache lines, so that the test process is no longer limited to the inside of a single cache line, but covers the dependency relationship between a plurality of to-be-tested cache lines, effectively testing the data synchronization capability across cache lines in a multi-core environment.

This invention provides a BeiDou-based V1200 electric-driven precision seeding monitoring terminal platform, belonging to the field of agricultural intelligent equipment technology. The platform adopts a five-layer architecture of "sensing-control-execution-display interaction-cloud platform." Its core innovation lies in using a BeiDou satellite positioning speed measurement unit as the single core speed measurement source, replacing traditional ground wheel transmission and redundant millimeter-wave radar. Non-contact, precise speed measurement is achieved through location information noise reduction calculations. Integrated photoelectric sensor components support independent seed placement monitoring for up to 48 rows of seeding units. The terminal platform automates the entire process of "BeiDou speed measurement-electric drive control-seed placement monitoring-cloud data synchronization," controlling plant spacing deviation within ±3%, increasing seed utilization by 8%-12%, and reducing equipment procurement costs by more than 30%. It is suitable for various crops such as corn, soybeans, rapeseed, and vegetables, has a low operating threshold, and is applicable to precision seeding operations in both large-scale and fragmented plots.

The utility model discloses a high temperature downhole power supply device, including output interface, upper shell, lower shell, main drive power supply, spare drive power supply, control board power supply, main control board, drive board, single core cable input interface, main drive power supply, spare drive power supply all are arranged in the middle of upper shell and lower shell, single core cable input interface electricity is connected control board power supply, and power supply supplies power to main control board, and main control board controls drive board drive, and drive board controls the switch of main drive power supply, spare drive power supply respectively. The utility model discloses dual power module parallel operation and possesses the redundancy switching function, eliminates the single point failure risk, sets up main control unit, real -time monitoring battery voltage, current, temperature, prevents overcharge, overdischarge, overcurrent, short circuit, effectively overcomes the performance degradation and failure risk under the severe working condition such as high temperature, high pressure and strong vibration.

This invention discloses a method for adjacency layout of multi-core chips, comprising the following steps: S1 Signal line grouping: analyzing the input and output port signal lines of each single core and grouping them according to functional design and topology; S2 Topology transformation: performing topology transformation on the internal and top-level connections of a single core and adding decoding logic; S3 Inserting buffers and low-power units: adding buffers and low-power units according to constraints including timing and low power consumption; S4 Physical implementation: implementing the adjacency layout and hierarchical physical implementation method. This invention achieves the effect of adjacency layout by transforming the topology of single cores and top-level signal lines, eliminating most inter-core connections, reducing congestion of inter-core connections and corresponding area, power consumption, and timing overhead. Since the transformed cores can be directly instantiated and reused multiple times, the physical implementation time is reduced; the more cores there are, the more physical implementation time is saved.

A hybrid bonding structure includes a local transmission line and a global transmission line each connecting a memory chip to a logic chip. During a read operation, data is directly transmitted from the memory chip to the logic chip through the local transmission line. During a write operation, data is transmitted from the logic chip to the memory chip through the global transmission line. A control signal is transmitted from the logic chip to the memory chip through the global transmission line. Accordingly, a plurality of banks implemented in the memory chip can be simultaneously controlled and a plurality of Processor Element s (Pes) implemented in the logic chip may operate as a single core. The hybrid bonding structure may be used to implement a machine learning accelerator.

Embodiments of the present application provide an attack detection device, method, and apparatus, which are used for solving the problems in the existing technology of the inability to scale a single CPU core to multiple cores, occupation of a large quantity of computing resources, and low processing efficiency. For each piece of NetFlow traffic, on the basis of a source IP and a destination IP in a five-tuple of the NetFlow traffic as well as a stored IP address range processed by each traffic-statistics CPU core, the NetFlow traffic is sent to a corresponding target traffic-statistics CPU core. Each traffic-statistics CPU core counts the number of packets and the number of bytes of NetFlow traffic for each IP address within the IP address range, and performs DDoS detection. The aggregation of NetFlow traffic for the same IP address and DDoS detection are directly completed in the traffic-statistics CPU core, so that there is no need to transmit the NetFlow traffic to a single CPU core for aggregation, thereby reducing the occupation of computing resources, improving processing efficiency, and further enabling core scaling.

Disclosed in the present application are a preparation method for a bronze-process Nb3Sn superconducting wire, and a superconducting wire. The preparation method comprises: placing a bronze rod into an Nb tube, placing the Nb tube into a bronze tube, and performing rotary swaging, drawing and annealing to prepare a bronze / Nb single core rod; bundling up hundreds of bronze / Nb single core rods in a hexagonal close-packed manner and then coating same with a barrier layer, and then placing the bronze / Nb single core rods into a copper tube to form a final billet; and heating the final billet and then sequentially performing extruding, drawing and intermediate annealing thereon, so as to obtain a bronze-process Nb3Sn superconducting wire having ring-shaped core filaments. By means of the present application, an Nb core filament changes from a solid columnar shape to a hollow tubular shape, thereby increasing the interaction area between Nb and a bronze matrix, increasing the reaction rate of Nb with Sn in the bronze matrix during a phase-formation heat treatment, and shortening the reaction time.