268 results about "SIMD" patented technology

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

An end-to-end rendering system enforces policy-constrained, symbolic presentation of artificial-intelligence (AI) outputs prior to any pixel emission. An AI accelerator emits inference tokens as (token identifier, confidence, domain tag) tuples into an output FIFO. A graphics processor with a command processor and SIMD co-processor executes a policy engine that runs a deterministic finite automaton (DFA) stored in non-transitory memory. The DFA consumes the tuples and produces, before any frame-buffer writes, a permit / deny decision and a visibility mask that constrain presentation attributes. A glyph selector maps permitted tuples to entries in a constrained glyph dictionary specifying a glyph identifier, semantic class, and allowed substitutions. A provenance tagger computes a cryptographic hash over at least the glyph identifier, a DFA-state policy identifier, a session nonce, and a checksum of the tuples to create an evidence capsule bound to the glyph. A device-aware renderer, consulting a device profile registry and a rendering grammar, emits a renderable asset for the glyph only when permitted by the visibility mask and grammar. A justification ledger records, for each displayed glyph, the evidence capsule and a monotonic timestamp. Executed entirely within the graphics processor, the pipeline prevents unauthorized tokens from entering the display path, enables cryptographically verifiable traceability of visible content, and reduces bandwidth by representing outputs as glyph identifiers rather than text or raster imagery, while allowing runtime policy updates without modifying the underlying inference model.

A method, apparatus and computer program product for homomorphic computation enables secure computation of determinants of a matrix under Fully Homomorphic Encryption (FHE). According to this disclosure, encrypted data that contains the values of a matrix is received at a server. The matrix is separated into at least a first portion, and a second portion. Each portion is configured as a square. A first data vector of ciphertext is computed for the first portion, and a second data vector of ciphertext is computed for the second portion. Under FHE, determinants of the first and second data vectors are computed as Single Instruction Multiple Data (SIMD) operations to generate a set of results. The set of results are then used to compute a determinant of the matrix. The determinant may then be used for FHE-based analytics.

The invention relates to the technical field of meteorological short-term and imminent forecasting, in particular to a meteorological short-term and imminent forecasting method based on multi-source data fusion and real-time modeling, and the meteorological short-term and imminent forecasting method based on multi-source data fusion and real-time modeling performs spatio-temporal interpolation through a time sliding filling method in combination with a DEM-containing trust propagation algorithm. And complementing the missing data and expanding meteorological data of other non-automatic station monitoring areas in the target area at the same time so as to obtain complete high-precision ground three-dimensional meteorological data (10 minutes per 10 minutes, 1 kilometer-level forecast precision) used for representing meteorological data in a three-dimensional space of the target area, and updating the UNet model in real time through an incremental learning strategy so as to realize real-time prediction of the meteorological data in the three-dimensional space of the target area. And secondly, a physical constraint module of an output layer of the UNet model ensures that a forecast result accords with a meteorological dynamics rule, and SIMD instruction optimization enables the fusion efficiency to be improved by 8 times, so that the real-time service requirement is met.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

The invention provides a compiling automatic vectorization method, a terminal and a medium, and the method comprises the steps: extracting each seed instruction group in a program block, and constructing an instruction group queue based on each extracted seed instruction group; sequentially executing SIMD (Single Instruction Multiple Data) judgment on each instruction group in the instruction group queue, and executing a corresponding vectorization design according to an SIMD judgment result to obtain an initial vectorization scheme; performing redundant structure rewriting on the initial vectorization scheme to obtain a simplified vectorization scheme; respectively calculating a scalar total execution cost and a vector total execution cost corresponding to the simplified vectorization scheme by using a preset cost model; when it is detected that the scalar total execution cost is larger than the vector total execution cost, setting the simplified vectorization scheme as a final vectorization scheme, and conducting vectorization compiling on the program block based on the final vectorization scheme; according to the method, the compiling efficiency of program vectorization compiling can be effectively improved.

The present disclosure relates to a vector processor implemented on programmable hardware (e.g., a field programmable gate array (FPGA) device). The vector processor includes a plurality of vector processor lanes, where each vector processor lane includes a vector register file with a plurality of register file banks and a plurality of execution units. Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD).

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses a data processing device, a data processing method, a chip and electronic equipment, and relates to the technical field of data processing. The data processing device comprises a storage module which is configured to store x groups of original data vectors, the original data vectors comprise m data elements, and x and m are positive integers; the calculation module is configured to access the original data vectors stored in the storage module, and reconstruct the x groups of original data vectors into one or more intermediate matrixes according to the parallel processing capability of the single-instruction multi-data execution unit and a target value k of a Top-k operator; loading the intermediate matrix into a vector register block according to columns, carrying out odd-even merging sorting by utilizing a single-instruction multi-data execution unit, and realizing in-line sorting on the intermediate matrix; and loading the intermediate matrix subjected to in-line sorting into a vector register block according to columns, and performing one or more rounds of merging sorting by utilizing a single-instruction multi-data execution unit to obtain top-k data elements in x groups of original data vectors.

The invention discloses an LLM reasoning acceleration method and device based on RISC-V vector extension, and belongs to the field of large language model design. The objective of the invention is to solve the problem of performance bottleneck in a large-scale language model (LLM) reasoning process, especially deployment on edge computing equipment. The method comprises the following steps: analyzing an inference process through a performance analysis tool, identifying bottleneck operators, and reconstructing the bottleneck operators by using an RISC-V vector extension RVV instruction set to improve the calculation efficiency. And the reconstructed operator can realize parallel calculation of SIMD, and the utilization of hardware resources is maximized by dynamically adjusting the length of a vector register. The method is further based on a dynamic vector length adaptation mechanism of RVV, it is ensured that the optimized operator can be automatically adapted according to different hardware platforms, and therefore efficient migration and execution of the reasoning task among multiple platforms are achieved, and the real-time performance of LLM reasoning and the system efficiency are effectively improved.

A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and / or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog / digital compute-in-memory arrays.

The invention provides an SM3 and SM4 fusion optimization method and system based on an SIMD register, and belongs to the technical field of data encryption and hash optimization. Executing SM3 message extension, writing an extension result into a stack area according to the determined mapping relation, and then reading extension data from the stack area by a compression function according to the mapping relation and executing a previous round operation of the SM3 compression function; reading a parameter pointer address of the SM4 from a stack area, loading a data block to be encrypted into an SIMD register, and performing format conversion from a large end sequence to a small end sequence on data; inserting a round function of the SM4 realized by using an SIMD instruction into a post-set round compression function of the SM3, so that a compression function instruction of the SM3 and a round function instruction of the SM4 are alternately executed, and post-set round calculation after merging is completed; after all round function calculation of the SM3 and the SM4 is completed, the encryption result of the SM4 is stored in the memory, then the parameter pointer of the SM3 is read from the stack area, and the hash result of the SM3 is written in the memory.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple, replicated compute circuits. Each compute circuit includes a cache that stores temporary data. A control circuit that identifies an instruction of the in-fight wavefronts as a long-latency vector memory access instruction with an indication specifying that a destination targets data storage in the cache, rather than a vector register file. The control circuit assigns a cache line for the vector memory access instruction while foregoing vector register assignment. The control circuit sends a data retrieval request to one or more higher levels of a cache memory subsystem. When the requested data has arrived, the control circuit stores the requested data in the assigned cache line and sends a notification to the corresponding SIMD circuit.

The invention provides a block cipher implementation method, device and equipment based on a lightweight algorithm structure. The method comprises the steps that cache equipment or a data interface obtains a plaintext needing cipher implementation; loading plaintexts by the register or the cache, and grouping the plaintexts into four branches for parallel processing by using the SIMD register; generating a round key by designing a key scheduling algorithm, and storing the round key in a special register; designing a lightweight algorithm structure for performing password implementation on the four branches stored in the SIMD register; and performing I-round encryption / decryption iteration on four branches of initial input of the plaintext / ciphertext by using a lightweight algorithm structure to generate the ciphertext / plaintext. According to the method disclosed by the invention, the cryptographic algorithm based on the lightweight algorithm structure is designed to encrypt and decrypt the data transmitted by the network or the communication, so that the software and hardware implementation cost in the application process is reduced while the requirement of easily implementing the lightweight password application is met, and the security is good.

The invention is suitable for the technical field of data processing, and provides a data sorting method and device, electronic equipment and a storage medium, and the data sorting method comprises the steps: converting a to-be-sorted one-dimensional array into a matrix; dividing the matrix into a plurality of sub-matrixes, and determining reference elements in each sub-matrix; performing partition operation on each sub-matrix based on a single instruction multiple data stream (SIMD) instruction set to obtain a first partition and a second partition of each sub-matrix; sorting the data elements in the first partition and the second partition of each sub-matrix to obtain a target sub-matrix after sorting of each sub-matrix is completed; and recombining the target sub-matrixes of the plurality of sub-matrixes, and converting the recombined target matrix into an ordered target one-dimensional array. The large-scale data sets can be efficiently sorted, and the processing efficiency of the large-scale data sets is improved.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a lookup table (LUT) according to a fused single instruction stream, multiple data stream (SIMD) instruction. The LUT may include segment entries corresponding to a result of evaluating a function using corresponding index values ​​representing an independent variable of the function. The index values ​​are used to map data sample values ​​in a data array configured to be interpolated to the segment entries.By using an iterative process of mapping data samples to valid segment entries contained in each LUT section, the architecture advantageously facilitates scaling to support larger LUTs and can thus be extended to enable linear interpolation on multiple dimensions.

A processor or other device, such as a programmable and / or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range ("LPHDR arithmetic"). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

The present disclosure relates to a vector processor implemented on programmable hardware (e.g., a field programmable gate array (FPGA) device). The vector processor includes a plurality of vector processor lanes, where each vector processor lane includes a vector register file with a plurality of register file banks and a plurality of execution units. Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD).

This invention discloses a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, comprising the following steps: S1. Based on the processor architecture description, a lexical analysis and syntax analysis part of the assembler is constructed to realize the parsing of special assembly instructions; S2. Taking the parsed instruction data or instruction binary code as input, dynamic encoding and decoding of instructions are implemented according to the instruction definition, thereby realizing the conversion between the object file and the assembly file. This DSP assembler porting method further improves the performance of the assembler and automates the porting process, adapting it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction words, and instruction validity checks. While ensuring that the program execution result meets expectations, it greatly reduces the number of clock cycles required for execution, possesses universality, and meets the needs of rapid processor architecture updates.

A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

The present invention discloses a C++ vector programming method based on a domestic heterogeneous platform, and the programming method comprises the following steps: S1, obtaining support for vector data types and vector programming interfaces by introducing header file simd.h; S2, the compiler performs front-end processing on the C++ vector program to generate intermediate representation code; S3, the compiler mid-end optimizes the intermediate representation code generated in S25 to generate a new intermediate representation; S4, the compiler mid-end generates instructions for the optimized intermediate code in step S3 to form vector assembly code; S5, generates machine code; S6, the linker mixes and links all the master core and slave core machine codes generated above into an executable code; S7, runs the executable code on a heterogeneous multi-core platform. The present invention provides a new programming method for the application development of the domestic heterogeneous multi-core architecture, which is conducive to maximizing the advantages of the architecture and improving application performance.

The application discloses a trigonometric function window generating method based on DSP, which comprises the following steps: converting the cosine term of the trigonometric function window into the n-th power form of the complex exponential fixed value based on the Euler formula; after the program initializes the calculation of the fixed value, generating the complex exponential term of each point sequence by recursive multiplication and storing the complex exponential term in the first-level storage space of the DSP; then, the SIMD parallel operation is realized by using the in-line function of the DSP, the first half of the window function values are calculated and stored; the first half of the window function values are inversely symmetrical copied to generate the second half of the window function values; finally, the hardware adaptive memory allocation is completed by combining the hierarchical storage architecture of the DSP, the stack is allocated to the first-level storage space, and the window function generation is completed by summarizing the data. The application greatly reduces the operation amount and the storage occupation, guarantees the calculation precision, deeply adapts to the hardware characteristics of the DSP, can efficiently generate the Hanning, Hamming and Blackman trigonometric function windows, and meets the real-time and high-precision requirements of the signal processing with large bandwidth and high sampling rate.

The invention relates to a processor and a memory access method. The processor comprises a UAV instruction sending unit, a UAV register management unit, a general register unit, a UAV data caching unit and a loading storage unit; the loading storage unit is configured to receive an SIMD instruction; reading resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; under the condition that the SIMD instruction is determined to be a loading instruction according to the operation code, reading channel logic address information of each channel from the general register unit; under the condition that the memory addresses to be accessed by the multiple channels of the SIMD instruction are judged to be continuous, calculating the memory access address of the first channel, and calculating the memory access addresses of the other channels based on the memory access address of the first channel; and generating a memory access request based on the memory access address of each channel. According to the method, the throughput rate of the loading storage instruction of the continuous address is improved, the number of ALUs calculated by the memory address is reduced, and meanwhile, the power consumption is reduced.