150 results about "SIMD" patented technology

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

The invention provides a compiling automatic vectorization method, a terminal and a medium, and the method comprises the steps: extracting each seed instruction group in a program block, and constructing an instruction group queue based on each extracted seed instruction group; sequentially executing SIMD (Single Instruction Multiple Data) judgment on each instruction group in the instruction group queue, and executing a corresponding vectorization design according to an SIMD judgment result to obtain an initial vectorization scheme; performing redundant structure rewriting on the initial vectorization scheme to obtain a simplified vectorization scheme; respectively calculating a scalar total execution cost and a vector total execution cost corresponding to the simplified vectorization scheme by using a preset cost model; when it is detected that the scalar total execution cost is larger than the vector total execution cost, setting the simplified vectorization scheme as a final vectorization scheme, and conducting vectorization compiling on the program block based on the final vectorization scheme; according to the method, the compiling efficiency of program vectorization compiling can be effectively improved.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses a data processing device, a data processing method, a chip and electronic equipment, and relates to the technical field of data processing. The data processing device comprises a storage module which is configured to store x groups of original data vectors, the original data vectors comprise m data elements, and x and m are positive integers; the calculation module is configured to access the original data vectors stored in the storage module, and reconstruct the x groups of original data vectors into one or more intermediate matrixes according to the parallel processing capability of the single-instruction multi-data execution unit and a target value k of a Top-k operator; loading the intermediate matrix into a vector register block according to columns, carrying out odd-even merging sorting by utilizing a single-instruction multi-data execution unit, and realizing in-line sorting on the intermediate matrix; and loading the intermediate matrix subjected to in-line sorting into a vector register block according to columns, and performing one or more rounds of merging sorting by utilizing a single-instruction multi-data execution unit to obtain top-k data elements in x groups of original data vectors.

A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and / or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog / digital compute-in-memory arrays.

The invention provides an SM3 and SM4 fusion optimization method and system based on an SIMD register, and belongs to the technical field of data encryption and hash optimization. Executing SM3 message extension, writing an extension result into a stack area according to the determined mapping relation, and then reading extension data from the stack area by a compression function according to the mapping relation and executing a previous round operation of the SM3 compression function; reading a parameter pointer address of the SM4 from a stack area, loading a data block to be encrypted into an SIMD register, and performing format conversion from a large end sequence to a small end sequence on data; inserting a round function of the SM4 realized by using an SIMD instruction into a post-set round compression function of the SM3, so that a compression function instruction of the SM3 and a round function instruction of the SM4 are alternately executed, and post-set round calculation after merging is completed; after all round function calculation of the SM3 and the SM4 is completed, the encryption result of the SM4 is stored in the memory, then the parameter pointer of the SM3 is read from the stack area, and the hash result of the SM3 is written in the memory.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

This invention discloses a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, comprising the following steps: S1. Based on the processor architecture description, a lexical analysis and syntax analysis part of the assembler is constructed to realize the parsing of special assembly instructions; S2. Taking the parsed instruction data or instruction binary code as input, dynamic encoding and decoding of instructions are implemented according to the instruction definition, thereby realizing the conversion between the object file and the assembly file. This DSP assembler porting method further improves the performance of the assembler and automates the porting process, adapting it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction words, and instruction validity checks. While ensuring that the program execution result meets expectations, it greatly reduces the number of clock cycles required for execution, possesses universality, and meets the needs of rapid processor architecture updates.

A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

The application discloses a trigonometric function window generating method based on DSP, which comprises the following steps: converting the cosine term of the trigonometric function window into the n-th power form of the complex exponential fixed value based on the Euler formula; after the program initializes the calculation of the fixed value, generating the complex exponential term of each point sequence by recursive multiplication and storing the complex exponential term in the first-level storage space of the DSP; then, the SIMD parallel operation is realized by using the in-line function of the DSP, the first half of the window function values are calculated and stored; the first half of the window function values are inversely symmetrical copied to generate the second half of the window function values; finally, the hardware adaptive memory allocation is completed by combining the hierarchical storage architecture of the DSP, the stack is allocated to the first-level storage space, and the window function generation is completed by summarizing the data. The application greatly reduces the operation amount and the storage occupation, guarantees the calculation precision, deeply adapts to the hardware characteristics of the DSP, can efficiently generate the Hanning, Hamming and Blackman trigonometric function windows, and meets the real-time and high-precision requirements of the signal processing with large bandwidth and high sampling rate.

The invention relates to a processor and a memory access method. The processor comprises a UAV instruction sending unit, a UAV register management unit, a general register unit, a UAV data caching unit and a loading storage unit; the loading storage unit is configured to receive an SIMD instruction; reading resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; under the condition that the SIMD instruction is determined to be a loading instruction according to the operation code, reading channel logic address information of each channel from the general register unit; under the condition that the memory addresses to be accessed by the multiple channels of the SIMD instruction are judged to be continuous, calculating the memory access address of the first channel, and calculating the memory access addresses of the other channels based on the memory access address of the first channel; and generating a memory access request based on the memory access address of each channel. According to the method, the throughput rate of the loading storage instruction of the continuous address is improved, the number of ALUs calculated by the memory address is reduced, and meanwhile, the power consumption is reduced.

Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.

The invention discloses a method and a system for generating SQL (Structured Query Language) statements in a template configuration manner, and belongs to the technical field of database access. The method comprises the following steps: firstly, solidifying four tuples of stmttype, field,: tbl and where on a template side by using XML / JSON, locking one of four styles of% s,-, {} and: name at one time by using a placeholder style arbiter, and generating a golden sequence vector after DOM / JSON double analysis and regular global scanning; then, parameters are obtained on the data side through db / file / API three-state routing, a single quotation is automatically added to string / data class values through a silicon-level quotation hardening circuit, number class values are directly transmitted in an unvarnished mode, and object-by-object fusing check is conducted through a key integrity sniffer in a batch scene; and finally, performing mmap original text re-loading on each record by a template hot loading isolator on a generation side, and realizing page-level isolation and zero-residue output by combining SIMD replacement and cache line scouring. The method is suitable for high-security, high-concurrency and high-real-time scenes such as cloud, edges and production lines.

The invention discloses a hardware-friendly Transform column balance pruning model compression and efficient deployment method. A model compression algorithm, a lightweight parameter storage format, an operation data buffer, a systolic array operation block, a vector operation unit, a nonlinear operator unit, a data flow controller and a DMA unit are included. A model compression algorithm and an efficient deployment architecture are explored according to Transform network software and hardware collaborative reasoning requirements: in a software level, the scale calculation complexity of model parameter quantities is reduced through a fine-grained column balance structured pruning strategy, and parameters are stored in a single-instruction multi-data-stream format and the parameter storage efficiency is optimized through mask code storage; according to the hardware level, an edge computing-oriented Transform special accelerator architecture is designed, so that the architecture can support column balance structured pruning characteristics and a lightweight parameter storage scheme in an original manner. According to the Transform model compression and efficient deployment method, the parameter sparsity after structured pruning is fully utilized, so that the parameter storage pressure of a hardware architecture is reduced, the complex balance of an arithmetic unit is ensured, the operation efficiency of an accelerator is improved, and load balance and efficient reasoning during software and hardware collaborative optimization are realized; the method is widely applicable to efficient deployment scenes of Transform models for edge calculation.

The invention provides a simd-based floating point transpose logic implementation method, which comprises the following steps of: S1, respectively reading four rows of data of a matrix A by using an mx512laq2w instruction, respectively storing the four rows of data into an I0 register, an I1 register, an I2 register and an I3 register, and simultaneously reserving a space with the same size as the previous element behind each element for splicing operation; the method comprises the following steps: S1, respectively storing 64-bit low-order 32-bit data of an I1 register into 64-bit middle-high-order 32-bit data of an I0 register by using two ilvew instructions, and storing 64-bit low-order 32-bit data of an I3 register into 64-bit middle-high-order 32-bit data of an I2 register, and S3, respectively storing ab and cd at adjacent positions of the registers and storing a1b1 and c1d1 at adjacent positions of the registers for the I0 register and the I2 register by using an ilved instruction and an ilvod instruction; and S4, by using four data storage instructions saq instructions, storing front 128 bit data of the register I1 into the first row of the matrix A1, storing rear 128 bit data of the register I1 into the third row of the matrix A1, storing front 128 bit data of the register I1 into the second row of the matrix A1, and storing rear 128 bit data of the register I1 into the fourth row of the matrix A1 to obtain a matrix A transposed matrix A1.

The invention relates to a software simulation method for vector multiplication. The core of the method is to select a bounded or non-bounded instruction to efficiently read data according to the alignment condition of a data access address, and intelligently select different simulation schemes according to the condition that a multiplier is a constant or a variable: for the constant, the constant is decomposed into a power combination of 2, and multiplication is simulated through a shift and addition instruction; for variables, an iteration process is adopted, and multiplication is achieved through least significant bit group extraction, number head zero calculation, shifting and conditional accumulation operation; and finally, selecting a storage instruction according to a destination address alignment condition. According to the method, an existing SIMD instruction set is fully utilized, the hardware vector multiplication function is efficiently simulated in a software mode, the word integer vector operation performance can reach eight times of that of standard quantity operation, and the performance and competitiveness of a domestic processor in the field of data processing are remarkably improved.

Embodiments of the present application provide a vector matrix multiplication acceleration method, unit, acceleration unit and system on chip, the method is applied to a fifth generation reduced instruction set processor, the method comprises the following steps: obtaining the number N of elements of a first matrix stored in a vector register according to the data length of the elements of the first matrix and the length of the vector register, N is a positive integer; performing rearrangement processing on the first matrix according to the number N to obtain a third matrix which can process N data in parallel; and performing multiplication calculation on the vector and the third matrix by using a single instruction multiple data stream instruction. The present scheme can improve the operation speed of vector matrix multiplication.

In various examples, systems and methods are disclosed that relate to programming multi-dimensional single instruction, multiple data (SIMD) processors (also referred to as an accelerator). In one example, a processor can obtain instructions to be performed by the accelerator. The processor can determine one or more operations to be performed by the accelerator based at least on the instructions and generate a set of accelerator instructions. In examples, the processor can then provide data associated with the accelerator instructions to cause the accelerator to perform at least a portion of the one or more operations.

An example device includes a first latch configured to receive data and a half-clock signal and a second latch in parallel with the first latch, The second latch is configured to receive the data and an inverted half-clock signal. The device further includes an output circuit connected to data outputs of the first and second latches. The output circuit provides the data alternately from the first latch and the second latch according to the half-clock signal. The device may be used in a processing element of a single instruction, multiple data (SIMD) computing device to save power.

The application discloses a kind of marine observation data gridding multi-level parallel acceleration calculation method and system.The application is based on the coarse-grained parallel implementation of climate model between MPI parallel architecture and parallel computing acceleration of ocean depth data, mainly includes the IO parallel reading of data, the calculation and distribution of climate model data, the synchronization of gridding data etc.;Based on the fine-grained parallel computing of OpenMP parallel architecture, the parallel computing of algorithm level between CPU core in node is realized, mainly includes the data gridding of each grid point in grid;For the gridding calculation of data in grid point, the distribution of data structure in memory is adjusted, and the specific calculation operation is accelerated using SIMD.The application can flexibly configure parallel scale according to specific hardware resources, realize the maximization of computing power utilization, and can provide computing power support for the construction of long-time sequence complete and reliable ocean grid data.

The disclosed method for rendering graphic images includes, for each lane contained in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane contained in the plurality of lanes, computing a filtered value based on a plurality of the texel samples read from a corresponding plurality of lanes, based on a footprint associated with the lane; and rendering at least one section of a graphic image based on the filtered values ​​computed for the plurality of lanes.

Techniques relating to graphics processing units (GPUs) that support ray tracing are disclosed. Specifically, shader switching logic can be configured to adjust the scheduling priority of a single-instruction multiple-data (SIMD) group of a shader program based on an indication that the SIMD group has an upcoming ray-cutting instruction for the ray-cutting accelerator switching logic, and based on a resource consumption indicator from the ray-cutting accelerator switching logic. This can be advantageous for reducing cache thrashing, for example, when shaders allocate memory for ray-cutting instructions and fill a shared cache faster than the ray-cutting accelerator switching logic can process the rays.

An example system includes a processor that can receive a number of complex packed tensors, wherein each of the complex packed tensors include real numbers encoded as imaginary parts of complex numbers. The processor can execute a single instruction, multiple data (SIMD) operation on the complex packed tensors using an integrated circuit of real and complex packed tensors in a complex domain to generate a result.

A multipart encoded representation or data type may be particularly useful for limited-capacity processors, such as those used in at-memory or single-instruction, multiple data (SIMD) devices. To encode a source number, the source number is quantized as a first binary representation defined by a first set of exponent bits and a first set of mantissa bits to obtain a first encoded part. A difference between the source number and a nearest dequantization of the first encoded part is computed. The difference is quantized as a second binary representation defined by a second set of exponent bits and a second set of mantissa bits to obtain a second encoded part. The first encoded part and the second encoded part are stored as an encoded representation of the source number. A computational operation may be performed using the encoded representation. The encoded representation may be decoded using an inverse process.

The application discloses an Internet of Things identity authentication method based on a lightweight Falcon signature, and the Internet of Things comprises a device, an edge gateway and a cloud platform, and comprises the following steps: initializing the device to generate a Falcon-512 key pair, performing sparse compression on the Falcon-512 key pair, and performing fragmented encryption storage; the Falcon-512 key pair comprises a private key sk and a public key pk; sending a registration request CSR to a cloud certificate authority CA through the device to obtain a device certificate Cert; collecting communication data Data through the device, calculating a hash value H(Data||Timestamp) of the communication data Data, wherein Timestamp is a time stamp; inputting the hash value H into an iterative FFT, mapping and storing the hash value H through a plurality of butterfly operations in the iterative FFT to obtain an intermediate result C in the FFT; wherein, based on the independence of the butterfly operation in the iterative FFT, a plurality of butterfly operations are processed in parallel through the SIMD instruction of the ARM Cortex-M processor; and a random integer z conforming to a discrete Gaussian distribution is generated through Gaussian sampling.

An apparatus and method for efficient dynamic scheduling of contexts in a processing circuit. In various implementations, a computing system includes a first processing circuit and a second processing circuit that uses multiple single instruction multiple data (SIMD) circuits, each with multiple parallel lanes of execution. When executing the operating system, the first processing circuit divides a workload into multiple contexts and assigns contexts to the second processing circuit. Rather than evenly allocate shared resources of the second processing circuit, the second processing circuit dynamically updates the allocations of shared resources for the multiple contexts based on the dynamic differences of forward progress of the multiple contexts. By performing dynamic allocation updates, the second processing circuit removes the burden of manually updating the allocation and increases throughput of the workload.