1490results about "Image memory management" patented technology

The invention discloses a method for automatically drawing an OpenGL (Open Graphics Library) program by using Vulkan. The method comprises the following steps of: creating a context used by the Vulkan, initializing each module, processing an OpenGL instruction related to texture and data buffering, and managing storage of texture and data buffering resources in a video memory; a shader program used by the OpenGL is preprocessed into a format acceptable to Vulkan, and an OpenGL shader program instruction is created and destroyed; processing an OpenGL (Open Graphics Library) instruction related to frame buffering to generate structural body information required by Vulkan dynamic rendering; an OpenGL instruction of the sampler is also created; processing an OpenGL (Open Graphics Library) instruction for creating a vertex input format and managing a vertex data buffer area, and maintaining vertex input information, a vertex buffer area and an index buffer area required by Vulkan; and finally, drawing or calculating, distributing and calling Vulkan on the basis of all the instructions.

The invention discloses a Direct3D memory model compatible method based on adaptive placeholder resources, which comprises the following steps: establishing resource metadata, accessing a scene library, checking an instruction template and double sandboxes when a DXVK is started, describing related resources by the DXVK through the metadata after a D3D application is started, completing resource mapping and metadata dynamic updating, and allocating the resources to the corresponding sandboxes; the DXVK compiles an application shader code, identifies a resource access instruction, matches an access scene and a check template by combining a pipeline stage and binding slot query metadata, instantiates the check instruction and adds the check instruction to the front of a target instruction; according to the unbound resources, adaptive generation of corresponding occupied resources is carried out, the authority and the state are configured, the unbound resources are bound to a Vulkan descriptor set to replace VKNULLHANDLE, and adaptation of the shader interface and the pipeline state parameters is completed to create PSO (Particle Swarm Optimization); and intercepting an application rendering instruction analysis parameter to construct a command buffer area, submitting the command buffer area to a Vulkan queue to trigger a GPU (Graphic Processing Unit) to execute rendering, and finally completing complete conversion and adaptation from the D3D rendering logic to the Vulkan.

The invention discloses a GPU Box hardware decoupling system based on a Retimer card and a PCIe Switch chip, and belongs to the technical field of computer hardware architecture and high-speed interconnection. According to the system, a Retimer card and a PCIe Switch chip are integrated in an independent GPU Box, and a decoupling link of a CPU server and a GPU acceleration card is constructed; the Retimer card realizes 30-meter long-distance PCIe signal transmission and breaks through physical distance limitation; the PCIe Switch chip pools GPU resources through a dynamic routing and MRIOV technology, supports flexible allocation of computing power by multiple servers, and realizes Peer-to-Peer direct connection communication between GPUs. Aiming at a large model reasoning scene, the system optimizes KV cache bandwidth allocation and video memory and memory cooperative scheduling, so that the 100B parameter model reasoning throughput is greatly improved; and meanwhile, the usability of the system is greatly improved through fault isolation and hot plug design. According to the method, the problems of physical binding of the CPU and the GPU, limited transmission distance, rigid resource allocation and the like in a traditional architecture are solved, and the method is suitable for large-scale AI calculation and distributed GPU cluster deployment.

The invention aims to provide a SiamFC-pytorch tracking model pre-processing and post-processing acceleration method and a SiamFC-pytorch tracking model pre-processing and post-processing acceleration system based on an NPU (Network Processing Unit). The system is realized based on a Yulong810SOC, and comprises a video input module (1), a hardware decoding module (2), a detection module (3), a tracking module (4) and a turntable control module (5), the method comprises the following steps: a, a video input module receives a video stream, and the video stream is decoded into an original image in a YUV format through a hardware decoding module; b, the detection module runs a YOLOv5 model through a neural network engine of the NPU; c, an NPU pre-processing and post-processing unit of the tracking module executes template branch pre-processing, search branch pre-processing and search branch post-processing on the YUV image and the target initial bounding box; and d, the turntable control module adjusts the posture of the camera turntable according to the real-time coordinates of the target. The method is applied to the technical field of computer vision and artificial intelligence hardware acceleration.

The invention relates to a memory shader. The programmable atomic memory shader execution circuitry is a seamless component of the hierarchical memory system, and can receive and execute programmable atomic operation calls from any number of processors. Programmable atomic memory shader execution circuitry close to memory allows execution circuitry to access shader programs stored in memory, thereby eliminating latency that may occur when an upstream processor exchanges shader instructions, data, and memory lock / unlock commands with the execution circuitry. The locked / unlocked state of the programmable atomic memory shader execution circuitry (e.g., in the L2 or L3 cache memory) allows the system to quickly lock the memory resources, perform one or more operations in an atomic manner over one or more cycles, and then quickly unlock the memory resources.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

The invention provides a memory access optimization method and device for an aggregate communication operator and computing equipment, and relates to the technical field of graphics processor computing. The method comprises the following steps: identifying a memory access instruction sequence in a to-be-optimized set communication operator, wherein the memory access instruction sequence comprises a standard loading instruction and a standard storage instruction; replacing the standard loading instruction with a batch loading instruction, and replacing the standard storage instruction with a batch storage instruction; the batch loading instruction and the batch storage instruction are configured to execute batch operation on the continuous memory address space at the thread beam level and finally execute the batch loading instruction and the batch storage instruction, so that the emission number of memory access instructions can be reduced, the scheduling burden of a thread beam scheduler is relieved, and the scheduling efficiency is improved. And the execution efficiency and the bandwidth utilization rate of the ensemble communication operator in the distributed training of the graphics processor are effectively improved.

The invention is suitable for the technical field of terminals, and particularly relates to a memory management method, electronic equipment and a computer readable storage medium. According to the method, when it is detected that the first application is switched to the background state, the electronic device can determine that the first application does not need to display an image and does not need to carry out graphic rendering, that is, it can be determined that the first application does not need to use a GPU physical memory currently. At the moment, the electronic equipment can store the first content stored in the first GPU physical memory corresponding to the first application to a disk, and can release the first GPU physical memory, so that the occupation of the GPU physical memory is reduced, the remaining available physical memory of the electronic equipment can be increased, the response speed of the electronic equipment to user operation is increased, the fluency of the system is improved, and the user experience is improved. And user experience is improved.

The invention discloses a thread group scheduling method and device for a GPU (Graphics Processing Unit), the GPU and equipment. The method comprises the following steps of: 1) receiving a scheduling request of a thread group; 2) task type priority scheduling; according to a thread group weight value set by a user, obtaining execution priorities of the vertex thread group and the fragment thread group in the current scheduling period; 3) instruction type priority scheduling; pre-analyzing to-be-executed instructions of the thread group, and determining a priority sequence of schedulable instruction types; and 4) priority scheduling of the thread groups: selecting the thread group with the highest priority for scheduling according to the specified task type priority and instruction type priority in combination with the thread group generation time. The invention provides a thread group three-level scheduling strategy so as to improve the instruction throughput rate and the key task response speed of the GPU under the complex load.

There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

The invention provides a tensor memory access verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design and manufacture. Based on the test parameters, controlling a tensor memory access unit in the first processor to execute actual data carrying operation to obtain an actual result that the source data is stored in a second memory associated with the first processor; based on the test parameters, controlling the second processor to execute behavior-level simulation to obtain an expected result of carrying the source data from the first memory to the second memory; and comparing an actual result with an expected result, and determining the function correctness of the tensor memory access unit under the test parameters. According to the method and the device provided by the invention, comprehensive and efficient function correctness verification can be automatically carried out on the tensor memory access unit, the technical problems of insufficient coverage rate and low pertinence of a verification method in related technologies are solved, and the verification efficiency and quality of the tensor memory access unit are remarkably improved.

The invention discloses an image processing method based on an FPGA, a storage medium and a computer program product, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: dividing and expanding a wafer image in a memory of an FPGA according to a convolution effective size and an edge effect size, and determining a target effective matrix and a target reading range of the target effective matrix; and obtaining read data according to the target reading range, and obtaining filling data for filling the target effective matrix located at the edge of the wafer image while obtaining the read data. And performing convolution preprocessing on the acquired data according to the pixel data groups corresponding to the target effective matrixes to obtain target data for executing image processing. Based on the pipeline design of caching the wafer image in the memory, positioning the target reading range and obtaining the filling data during reading, the occupation of the cache space of the memory is reduced, the processing delay of the wafer image is reduced, and the overall image processing efficiency is improved.

The invention discloses a non-intrusive image capturing and storing device and a non-intrusive image capturing and storing method. Relates to the technical field of security data storage, and solves the problems of acquisition blind areas, low data credibility and invalid data redundancy caused by a traditional software-level screenshot technology. The video conversion processing module is directly connected with a target host video output link through a standard video interface, the whole device is independent of a host system, does not depend on host permission, does not perform data interaction or protocol communication with a host, and avoids a collection blind area caused by insufficient permission or protection interception; the control processing module encrypts the frame-cut image to protect data security; the control processing module only triggers frame interception when detecting that the image is obviously changed, so that undifferentiated acquisition is avoided, redundant data irrelevant to auditing is reduced from the source, and the storage and operation cost of subsequent auditing analysis is reduced; the protection operation of the safety protection module is executed through a hardware interface and does not depend on host software logic, so that protection failure caused by remote control of a host is avoided.

The invention provides a loading storage circuit and a graphics processor, and relates to the technical field of graphics processing. The loading storage circuit comprises an instruction scheduling module, an address generation module and a data service module, and is provided with a buffer area module which comprises an operand buffer area and an effective data buffer area and is used for caching information required by address calculation and data access; the instruction scheduling module is used for collecting a data access instruction and outputting instruction information; the address generation module calculates a target access address according to the instruction information and the operand; and the data service module executes corresponding data loading or storage operation on the target cache unit. According to the scheme, the operands and the valid data are pre-cached, so that overflow and stagnation caused by inconsistent processing rhythms among modules can be avoided, and the parallel processing capability of an assembly line is improved; through the independent address calculation and data access process, the stability of the access time sequence and the data processing efficiency can be improved.

The invention relates to the technical field of industrial visual inspection, and discloses a surface defect detection method for a copper-aluminum composite board. The method comprises the following steps: acquiring an original plate surface image through image acquisition equipment, and preprocessing to obtain a standardized image; performing texture field decomposition on the standardized image, separating out independent texture components of the copper layer and the aluminum layer, and calculating a coherence graph among the components; inputting the texture component and the coherence graph into a composite structure discrimination network, guiding feature fusion by the network according to the coherence graph, performing anomaly judgment, and outputting a pixel-level initial defect graph; and performing morphological and topological rule processing on the initial defect graph, generating a final defect contour, and performing superposition labeling on the final defect contour and the original graph. According to the method, the single material layer defect and the composite interface defect can be distinguished by separating the texture of the material layer and utilizing coherence guide analysis, and the detection precision is improved.

The invention relates to the technical field of high-performance computing, and provides an inter-thread data sharing method, electronic equipment, a storage medium and a program product.The method comprises the steps that a plurality of threads in a thread block are divided into at least one cooperative thread group, and the threads in each cooperative thread group are from at least two different thread bundle groups; when a write operation of a first thread in any cooperative thread group is received, writing target data into a shared register resource associated with any cooperative thread group; and when a read operation of a second thread in any cooperative thread group for the target data is received, executing a synchronous operation, and reading the target data from the shared register resource after the execution is completed. According to the method, the cooperative thread group spanning different thread beam groups is constructed, and the shared register resources are utilized for data exchange, so that efficient data sharing is directly carried out among the threads spanning the thread beam groups through the register, and the method has the advantages of low delay, high bandwidth and capability of remarkably improving parallel computing performance.

Apparatuses, systems, and techniques to perform multi-threaded memory allocation in parallel by one or more software programs being performed on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, one or more software programs expressed in part by code using an application programming interface for parallel computing, such as CUDA, perform allocation, search, and deallocation of memory efficiently and in parallel on a GPU.

The invention discloses a Direct3D12 sampler addressing mode compatible method based on double buffer preprocessing, which comprises the following steps of: establishing a preprocessing parameter cache pool, a first association table, a second association table and a resource management linked list in a system initialization and starting stage, and registering a Vulkan expansion structure body for expanding a texture coordinate range and marking MSAA sampling point offset; when the textures are created, the VKD3D judges whether the textures are MIRROONCE related textures or not, allocates resource marks to the related textures, sets dependency marks, allocates double buffers and expands a coordinate range, and executes standard conversion if the textures are not related; when a sampler is created, marking an analog sampler, constructing and configuring a Vulkan sampler structural body, and updating an association table and a resource management linked list; when a pipeline is created, the D3D12 shader is converted into SPIR-V to update the second association table; and when the recording command list is applied, generating a command buffer, and submitting the command buffer to complete rendering.

The invention provides a Gaussian data tree index construction method and device supporting incremental updating and a rendering method.The Gaussian data tree index construction method comprises the steps that firstly, normalization processing and integer format conversion are conducted on original Gaussian data, spatial index key values are generated based on coordinates of an integer format, and the spatial index key values serve as coded values corresponding to the original Gaussian data; segmenting the original Gaussian data into a plurality of data blocks according to the coded values; then constructing a local octree; then, generating a global octree; a storage offset is distributed to each node of the global octree, and a byte range corresponding to each node is determined based on the storage offset; each data block stores the original Gaussian data according to the corresponding storage offset and the sequence of the coded values. The subsequent query efficiency can be improved by storing the data blocks according to the coded value sequence, meanwhile, the memory mapping technology is adopted to process the oversized node data so as to reduce IO overhead, and the storage layout and the output mode effectively improve the data writing efficiency and the subsequent reading performance.

A building security system includes computer-readable storage media having instructions stored thereon that, when executed by processors, cause the processors to: receive, from cameras communicably coupled to the building security system, video data, wherein the video data includes one or more video recordings, retrieve contextual information associated with the video data, analyze, using one or more artificial intelligence models, the video data, wherein the analysis of the video data includes detecting one or more details, determine, using the one or more AI models, based on the contextual information and the one or more details detected within the video data, a relevance of the one or more video recordings, and, based on the relevance of the one or more video recordings, automatically implement, using the one or more AI models, an action to delete or reduce a storage size of at least one of the one or more video recordings.

A machine learning system is provided to enhance various aspects of machine learning models. In some aspects, a substantially photorealistic three-dimensional (3D) graphical model of an object is accessed and a set of training images of the 3D graphical mode are generated, the set of training images generated to add imperfections and degrade photorealistic quality of the training images. The set of training images are provided as training data to train an artificial neural network.

The invention discloses an illumination scene rendering method and device, a computer readable storage medium and a computer program product, and the method comprises the steps: setting a plurality of illumination probes in a three-dimensional Gaussian splashing scene, and determining a first spherical harmonic coefficient of each illumination probe based on the light field data of the three-dimensional Gaussian splashing scene, the illumination probe is used for collecting omnidirectional illumination information of a spatial point of a three-dimensional Gaussian splashing scene; for each unshielded pixel of the to-be-rendered object, determining indirect diffuse reflection light for the to-be-rendered object based on a target spherical harmonic coefficient of a target illumination probe determined by the unshielded pixel, the to-be-rendered object being an object placed in the three-dimensional Gaussian splash scene; for each unshielded pixel, based on the normal direction of the unshielded pixel and the constructed hierarchical Z buffer, indirect specular reflection light for the to-be-rendered object is determined through screen space reflection and a reflection ball; and fusing the indirect diffuse reflection light, the indirect specular reflection light and the direct light to generate an illumination rendering result for the to-be-rendered object.

A vehicle includes multiple storage zones. A set of imaging sensors defines fields of view and each storage zone is included in at least one defined field of view. A controller is in communication with the set of imaging sensors and includes a set of processing modules configured to cooperatively implement a smart storage tracking system including a person recognition processing module and an object recognition processing module. The person recognition processing module includes a process for identifying unique persons using image analysis and the object recognition module includes a process for identifying unique objects using image analysis. The smart storage tracking system defines an object to person and location data entry in a database using the person recognition processing module and the object recognition processing module. The database is in communication with the controller and storing each defined object to person and location data entry.

The invention provides a graphics processor, a texture loading method, a texture processing unit, equipment and a medium, and relates to the technical field of image texture loading. The method comprises the following steps: uniformly distributing texture loading instructions to a texture processing unit for execution, wherein the texture loading instructions comprise texture cache loading instructions; analyzing and executing the texture loading instruction through the texture processing unit; wherein the texture state information of the texture loading instruction is obtained through hardware analysis of the texture processing unit, the texture loading instruction completes address calculation and data reading in an independent texture loading pipeline, and the texture loading pipeline is started in the texture processing unit. According to the technical scheme, the scheduling logic of the texture loading instruction can be simplified, the compatibility of dynamic resources is improved, meanwhile, the hardware utilization rate is increased, and the reliability and execution efficiency of texture data access are improved.

The invention discloses a primitive result output method and device, a processor, equipment, a medium and a product, the primitive result output method is applied to a graphics processor, the graphics processor comprises at least two cores, and the at least two cores are parallel to subtasks of an original rendering task. The method comprises the steps that subtasks corresponding to the cores are executed in parallel through the two cores, and primitive results corresponding to the subtasks are output to temporary storage spaces corresponding to the cores; and copying the primitive result corresponding to each subtask to a primitive storage space in the temporary storage space corresponding to each core to obtain a target primitive result of the original rendering task.

The invention provides an image processing method and device, electronic equipment, a storage medium and a program product, the method is applied to an image processing module running in target equipment, the target equipment further comprises a virtual machine, and the method comprises the steps that in response to starting of the virtual machine in the target equipment, according to a physical address corresponding to a virtual frame buffer area, the virtual frame buffer area is obtained; determining a physical storage area corresponding to the virtual frame buffer area; the physical storage area is determined as an image storage area, and the image storage area is a storage area which can be accessed by the image processing module; and under the condition that the virtual machine stores image frame data to the virtual frame buffer area, reading the image frame data from the image storage area so as to render and display the image frame data. According to the embodiment of the invention, the efficiency of displaying the image frame data can be improved.

A processing system captures raw ray traversal data from a real-time ray tracing application and generates tokens that are compact representations of various aspects of the ray tracing data from which the ray traversal data can be reconstructed and analyzed. For example, a token stream includes tokens having identifiers to uniquely identify a ray in a ray dispatch, a call site within a shader, traversal iteration and parent traversal. Other tokens in the stream may include associated ray and top level and bottom level acceleration structure data, intersection result, function call, hits, and ray user payload data. An analysis and visualization application accesses the stored tokens, parses the tokens, and reconstructs the ray traversal data represented by the tokens for subsequent analysis.

The invention relates to the technical field of computer graphics, sensor simulation and real-time rendering, in particular to a panoramic laser radar simulation method and system based on a single GPU calculation shader, and the method comprises the steps: receiving simulation parameters of a laser radar sensor, assembling the simulation parameters into a constant buffer area object, and carrying out the simulation of the laser radar sensor on the constant buffer area object; the method comprises the following steps: allocating a structured point cloud buffer area and binding shader resources in a rendering dependency graph framework, scheduling and calculating a shader to generate a two-dimensional thread index, calculating a light beam direction vector corresponding to each thread and constructing a ray descriptor based on the two-dimensional thread index, and obtaining hit information; the method comprises the steps of calculating echo intensity based on hit information according to a preset intensity model, simulating noise, writing point cloud attributes into a structured point cloud buffer area, and asynchronously looking back point cloud data for consumption through the structured point cloud buffer area. And the throughput and the data consistency are improved.

The invention relates to the technical field of chip design, in particular to a cross-cache-line data acquisition method, electronic equipment and a storage medium, and the method comprises the following steps: acquiring a maximum unit total amount M corresponding to a graph drawing command to which a current subtask belongs; reading and splicing data corresponding to continuous (M-1) subunits at the tail of the first cache line address range and data corresponding to continuous (M-1) subunits at the starting end of the second cache line address range to obtain continuous data covering the complete access range of the current subtask, and storing the continuous data in a preset buffer area; the target data is extracted from the buffer area according to the initial address of the current sub-task and the first target number of the first target sub-unit in which the current sub-task falls in the first cache line to which the first target sub-unit belongs, and the target data is used as the input of the distribution operation, so that the logic complexity and the calculation complexity are reduced.