3044results about "Image memory management" patented technology

The invention discloses a method for automatically drawing an OpenGL (Open Graphics Library) program by using Vulkan. The method comprises the following steps of: creating a context used by the Vulkan, initializing each module, processing an OpenGL instruction related to texture and data buffering, and managing storage of texture and data buffering resources in a video memory; a shader program used by the OpenGL is preprocessed into a format acceptable to Vulkan, and an OpenGL shader program instruction is created and destroyed; processing an OpenGL (Open Graphics Library) instruction related to frame buffering to generate structural body information required by Vulkan dynamic rendering; an OpenGL instruction of the sampler is also created; processing an OpenGL (Open Graphics Library) instruction for creating a vertex input format and managing a vertex data buffer area, and maintaining vertex input information, a vertex buffer area and an index buffer area required by Vulkan; and finally, drawing or calculating, distributing and calling Vulkan on the basis of all the instructions.

The invention discloses a Direct3D memory model compatible method based on adaptive placeholder resources, which comprises the following steps: establishing resource metadata, accessing a scene library, checking an instruction template and double sandboxes when a DXVK is started, describing related resources by the DXVK through the metadata after a D3D application is started, completing resource mapping and metadata dynamic updating, and allocating the resources to the corresponding sandboxes; the DXVK compiles an application shader code, identifies a resource access instruction, matches an access scene and a check template by combining a pipeline stage and binding slot query metadata, instantiates the check instruction and adds the check instruction to the front of a target instruction; according to the unbound resources, adaptive generation of corresponding occupied resources is carried out, the authority and the state are configured, the unbound resources are bound to a Vulkan descriptor set to replace VKNULLHANDLE, and adaptation of the shader interface and the pipeline state parameters is completed to create PSO (Particle Swarm Optimization); and intercepting an application rendering instruction analysis parameter to construct a command buffer area, submitting the command buffer area to a Vulkan queue to trigger a GPU (Graphic Processing Unit) to execute rendering, and finally completing complete conversion and adaptation from the D3D rendering logic to the Vulkan.

An apparatus to facilitate lossless and lossy automatic hardware compression in graphics-to-graphics network links is disclosed. The apparatus includes compressor / decompressor circuitry (CDC) integrated with physical layer (PHY) intellectual property (IP) hardware circuitry for a graphics processor unit (GPU)-to-GPU communication link communicably coupling a first GPU to one or more other GPUs, the CDC to: receive a data message from the first GPU, wherein the data message is in an uncompressed format; determine that a compression process is to be applied to the data message; apply the compression process to the data message to generate a compressed data message; and cause a GPU link IP hardware circuitry that comprises the PHY IP hardware circuitry to transmit the compressed data message over the GPU-to-GPU communication link.

Provided in the present disclosure are a data processor, a data processing method, an electronic device and a non-transitory computer-readable storage medium. The data processor comprises a tensor operation unit and N compute units, wherein the tensor operation unit is configured to execute tensor computation on input data, so as to obtain tensor computation results; and the N compute units are configured to execute at least one of a vector operation of the tensor computation results and the generation of input data, wherein first data transmission channels are provided between the tensor operation unit and at least some compute units among the N compute units, and the first data transmission channels are used for directly providing the tensor computation results to the compute units, and directly providing the input data from the compute units to the tensor operation unit. By means of the data processor, access to a global memory can be reduced, the waste of resources is reduced, the data transmission delay is shortened, the overall efficiency of operators is significantly improved, the strong computing power of a tensor operation unit itself is effectively used, and the computation efficiency of the data processor is improved.

The invention discloses an image processing data analysis platform based on a memristor storage and calculation integrated architecture, and relates to the technical field of data identification, and the platform comprises an XC7Z020 FPGA control module which is connected with an OV5640 camera image acquisition module, a memristor array calculation module and an Internet of Things module. According to the image processing data analysis platform based on the memristor storage and calculation integrated architecture, through deep fusion of the memristor storage and calculation integrated architecture and a dynamic optimization technology, the speed, energy efficiency and reliability of image processing are remarkably improved. The data handling bottleneck of the traditional von Neumann architecture is eliminated, the processing speed is improved compared with that of the traditional GPU scheme, and meanwhile, the system energy consumption is reduced. Weight distribution and fragmentation processing strategies are adjusted through real-time feature feedback, so that the recognition accuracy in a complex industrial scene is improved, the throughput is broken through, and the real-time processing requirement of a high-resolution image is met.

One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

Apparatuses, systems, and techniques to perform one or more operations using a tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to perform one or more operations using one or more tensors based on at least one or more indications of the plurality of operations by the API, one or more compiler options indicated by the API, and / or one of one or more indications of an amount of storage to be used to perform the one or more operations.

The invention discloses rendering equipment based on three-dimensional Gaussian sputtering. The hardware architecture includes a memory interface, a pre-processing engine, a cardinality ordering engine, a rasterization engine, and the like. The preprocessing engine converts the three-dimensional Gaussian point into a two-dimensional representation and generates a key value pair containing a tile identifier and depth information; the cardinal number sorting engine performs staged efficient sorting through a parallel processing mechanism and a BRAM alternate working mode; and the rasterization engine performs rendering processing by adopting a full-pipeline design and an early-stage stopping mechanism. According to the method, parallel execution of depth sequencing and rasterization is achieved, memory access and calculation redundancy are reduced through optimized data flow design, an efficient and low-power-consumption hardware acceleration solution is provided for three-dimensional Gaussian sputtering rendering, and the method is particularly suitable for application scenes such as virtual reality, games and scientific visualization requiring real-time rendering.

Apparatus and method for efficient storage of BVH nodes in blocks. For example, one embodiment of an apparatus comprises: bounding volume hierarchy (BVH) construction circuitry to construct a BVH based on primitives of a graphics scene; and block allocation hardware logic coupled to or integral to the BVH construction circuitry, the block allocation hardware logic to allocate a plurality of nodes of the BVH into a plurality of blocks for storage in a cache or memory subsystem, the block allocation hardware logic to maximize a number of blocks which include a leading parent node and one or more corresponding child nodes of the plurality of nodes.

The invention relates to a digital twin platform GPU rendering resource dynamic scheduling method and system, and the method comprises the steps: S1, collecting a rendering task feature signal of a current frame in real time, and collecting a GPU multi-dimensional resource consumption signal; s2, based on the rendering task feature signal, the historical resource consumption signal and the scene dynamic change signal, generating a GPU resource demand prediction signal and a load fluctuation trend signal of a future frame; s3, predicting a signal, a task dependency relationship signal, a user priority signal and a real-time resource bottleneck type signal according to the GPU resource demand; s4, executing the dynamic resource allocation instruction signal; and S5, generating a parameter self-optimization signal for updating the prediction and scheduling logic of a subsequent frame according to the actual resource consumption signal of the current frame and the scheduling effect evaluation signal. According to the dynamic scheduling method and system for the GPU rendering resources of the digital twin platform, the problem that the GPU resource utilization rate is low and the real-time performance is difficult to consider at the same time under the dynamic load can be solved.

Systems and methods for efficient memory management during ray tracing are described. A ray tracing system assigns a memory stack to a ray. The ray, when intersection tested against objects of a node, accesses data that is stored in the memory stack. When data is to be consumed from the memory stack by the ray, the ray tracing system uses a memory pointer associated with the ray to locate the requested data. When data is to be stored to the memory stack, the memory allocation circuitry stores data in a free memory block and uses a linked list to link the memory block with other memory blocks storing additional data for the ray.

The invention provides a high-resolution machine vision detection method and system for precise chromatic aberration detection and a medium, and the method comprises the steps: carrying out the calibration of a camera based on a camera calibration tool, and synchronously calibrating a light source parameter and a color parameter; setting shooting parameters based on the calibrated camera, obtaining a workpiece image in real time, preprocessing the workpiece image, mapping the preprocessed image to a standard color space from an original RGB space, and extracting color features of the preprocessed image; comparing the color feature with the color feature of the standard sample, calculating a color difference index, and comparing with the color difference index based on a set color difference threshold to obtain a detection result; by calibrating various parameters of the camera, the visual detection precision is ensured, and by performing color space mapping on the workpiece image and analyzing the difference between the color difference index of the color feature and the color difference threshold value, the color abnormal area is accurately analyzed, and the detection precision of the abnormal color is improved.

The invention discloses a multi-cluster heterogeneous computing power scheduling method oriented to an AI training reasoning task, and belongs to the technical field of computers. According to a scheduling mechanism with issuing of the AI task as a core, the state of a resource pool is monitored in real time, resources are dynamically allocated, it is ensured that the AI task is efficiently executed, the use efficiency of the whole resource pool is improved, and the load state of an AI application example is detected in real time; through an elastic telescoping function, AI application examples are automatically expanded and shrunk, stable operation of AI tasks is ensured, resources of a plurality of clusters are integrated into a unified resource pool, centralized management and cooperative scheduling of the resources are achieved, the load condition of each cluster is monitored in real time, load balancing is automatically carried out among the clusters, and the AI tasks are reasonably distributed to different clusters. And the GPU resources of the specified model are accurately allocated to the AI task according to the actual demand of the AI task, so that the situation that the AI task application runs on non-optimal resources is avoided, and the efficient running of the AI task is ensured.

The invention discloses a memory writing method and device, a storage medium and a program product, and relates to the technical field of memory access, and the method comprises the following steps: determining a memory step length of an initial image tensor corresponding to a target image, determining a target vectorization width according to the memory step length and a memory data width of a target graphics processor, and determining a target data dimension of the target graphics processor, determining a target thread grid corresponding to the initial image tensor according to the target data dimension, performing image tensor slicing by using the target thread grid to obtain a target image tensor, and writing the target image tensor into a memory. According to the method, the memory layout (step length) of the input tensor can be dynamically analyzed, so that the optimal vectorization width is adaptively determined, the memory access efficiency is maximized, slicing is performed according to the data dimension when the target graphics processor outputs the data, the method has adaptability and high efficiency, the GPU video memory bandwidth is fully utilized, and the memory bandwidth utilization rate is improved.

The invention discloses a lesion area self-adaptive segmentation method and system for a seminal vesicle endoscope image, particularly relates to the field of medical image processing, is used for solving the problems of geometric distortion and artifacts in the seminal vesicle endoscope image, and aims to eliminate geometric deviation caused by thick layer sampling through synchronous acquisition and attitude correction. Then, a resampling strategy is adjusted in a self-adaptive mode through key geometric features, the problems of inter-layer artifacts and resolution imbalance are effectively weakened, a lesion segmentation network is optimized through smooth regularization and geometric constraint, continuity and geometric accuracy of lesion boundaries are ensured, finally, the accurate lesion mask is dynamically overlaid to a real-time frame stream, and the real-time frame stream is obtained. A quantitative basis is provided for biopsy path planning and photodynamic dose scheduling; smooth and continuous images are completed and output in a strict time window, the perception ability of an operator to tiny pathological changes is enhanced, meanwhile, the method is suitable for various endoscope devices, motion blur and light spot artifacts are restrained, and focus details are kept clear.

The embodiment of the invention discloses a GPU video memory channel allocation method and device, equipment and a storage medium. An exemplary embodiment of the method comprises the following steps: pre-applying for a plurality of physical video memory pages from a physical video memory space; mapping video memory colors to the plurality of physical video memory pages according to a mapping table of colored partitions and video memory colors of the physical video memory pages to obtain video memory channels corresponding to the colored partitions; in response to a detected target task of performing video memory operation according to the required color and the required space, querying an unallocated colored partition of a video memory channel corresponding to the required color; and distributing a target physical video memory page to the target task from the plurality of physical video memory pages according to the demand space, and returning a virtual address space corresponding to the target physical video memory page to the target task for use.

The invention provides a fractal graph drawing method and device, a storage medium and electronic equipment, and relates to the field of computer graphics. The method comprises the following steps: the electronic equipment iterates a preset number of times by utilizing a current basic fractal graph to obtain a derivative fractal graph; judging whether the number of pixels required for displaying the derivative fractal graph is changed or not compared with the current basic fractal graph; if the derivative fractal graph will change, taking the derivative fractal graph as a new basic fractal graph, and returning to the step of obtaining the derivative fractal graph by utilizing the current basic fractal graph to carry out iteration for preset times; and if the fractal graph does not change, taking the derivative fractal graph as a target fractal graph. Thus, whether the fractal graph reaches the optimal definition or not is judged by judging whether the number of pixels before and after iteration changes, and compared with visual inspection, the definition of the fractal graph can be judged more objectively.

The invention discloses a data processing system, method and device, a medium and a program product, and relates to the technical field of computers. Weight data of a target model corresponding to a model processing task and key value pair data needing to be processed are stored in logic processing equipment; and the execution end of each operation in the target model can be a host, a logic processing device or a computing device, so that the pressure of the computing device for running and storing the model can be reduced, a proper execution end can be selected for each operation in the model, and the model operation efficiency is improved. And the execution end only needs to load the weight sub-data and the key value pair sub-data required by the currently executed operation from the logic processing equipment, and the model operation efficiency is further accelerated through loading a small amount of data. Therefore, the performance of the model can be brought into full play, and the model training and reasoning efficiency is improved.

The invention discloses a depth operation implementation method and device for parallel pixels in the vertical direction, a medium, equipment and a product. The method comprises the following steps: mapping each channel group with a thread bundle containing NT threads; acquiring jumping step length of vertical direction access and parameter configuration of a sliding window operator; performing register resource allocation for each thread to form a sliding window data cache region; determining NH row starting point coordinates of the current scanning round; when the current scanning round is executed, in each column slice participating in calculation, pixel groups at NT row and column positions are scanned from each row starting point coordinate with the jump step length as the span, and the pixel groups are loaded to register groups of all threads in corresponding thread bundles in sequence, so that each thread can process the calculation task of the corresponding local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The invention provides a multi-core GPU cache division method, architecture and data access method, relates to the technical field of graphics processor design, and aims to realize cross-core access performance system-level optimization and improve the performance of processing large-scale image data by introducing a cache allocation mechanism based on topology awareness. The method comprises the steps that a multi-core-grain GPU topological structure comprising a target computing core grain and at least one associated computing core grain is obtained, a to-be-divided far-end data cache of the target computing core grain is used for caching image data from a far-end video memory, and the to-be-divided far-end data cache is connected with the associated computing core grain through an inter-core-grain interconnection network; if the number of the calculation core particles contained in the multi-core-particle GPU does not exceed a first preset threshold value, the inter-core-particle hop count between each associated calculation core particle and a target calculation core particle is determined based on the topological structure, and then the corresponding capacity of the associated calculation core particles in the to-be-divided cache of the target calculation core particle is determined; and dividing the to-be-divided cache according to the capacity corresponding to each associated calculation core particle.

One embodiment provides a graphics processor comprising a memory interface and a processing cluster array including a plurality of processing resources interconnected via a switched interconnect network, at least one of the plurality of processing resources including a matrix accelerator configured to execute an instruction to perform a multi-dimensional sparse matrix multiply and accumulate operation having input in a sparse microscaling format including merged sparsity and scaling metadata.

A method, apparatus, non-transitory computer readable medium, apparatus, and system for image processing include obtaining an input prompt and retrieving an intermediate noise state based on a similarity between the input prompt and a candidate prompt corresponding to the intermediate noise state. An image generation model generates a synthetic image based on the input prompt and the intermediate noise state.

The embodiment of the invention discloses a frame rate improving method, electronic equipment and a storage medium, and relates to the technical field of display processing. The method comprises the steps that when it is determined that the frame rate of a game picture needs to be increased, a frame insertion rendering thread is created; generating a frame insertion image in a frame insertion rendering thread according to the frame rendering data; and inserting the frame insertion image before or after an original image generated by the main rendering thread according to the frame rendering data. Therefore, when the frame rate of the game picture needs to be improved, the electronic equipment can create a frame insertion rendering thread, and the frame insertion rendering thread can share part of rendering tasks of the main rendering thread, so that the main rendering thread can have more time to process complex scenes, perform real-time interaction and the like; according to the technical scheme, jamming, delay and the like caused by overload of the main rendering thread are reduced, so that rendering of the game picture can maintain a stable target frame rate, the rendering effect of the game picture is improved, and then the game experience feeling of a user is enhanced.

The invention relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. Determining a first jump step length required for rearranging the block data based on the block size of the input data in the first dimension; secondly, performing jump reading on the block data according to a first jump step length, rearranging and loading read input elements into a thread private register so as to realize transposition storage of the block data in the thread private register, and mapping a thread direction on a second dimension so as to obtain a data basis of convolution correlation calculation; convolution correlation calculation is executed based on the transposed data in the thread private register and the weight data in the thread private register, repeated data reading in the calculation process is reduced during sliding window calculation, and an operator is converted into calculation performance bottleneck operation from memory access performance bottleneck operation.

The disclosure describes hardware compression of sparse matrix content. One embodiment provides a graphics processor, the graphics processor comprising: a base die, the base die comprising a plurality of chiplet slots; and a plurality of chiplets, the plurality of chiplets being coupled with the plurality of chiplet slots. At least one chiplet of the plurality of chiplets comprises: a graphical core cluster comprising a plurality of processing elements; a shared local memory coupled with the plurality of processing elements; a plurality of matrix engines coupled to the shared local memory; and codec circuitry coupled with the shared local memory and the plurality of matrix engines. Codec circuitry is configured to decode matrix data stored in a first format in a shared local memory into a second format for consumption by a plurality of matrix engines.

The invention provides a data loading method, a data storage method, a processor, electronic equipment and a medium. The data loading method is used for loading a to-be-processed tensor from an original tensor of a memory to a cache region, and comprises the following steps: determining a plurality of requests for loading the to-be-processed tensor in combination with the number of pixels included in the to-be-processed tensor, a data storage format of the original tensor and an initial coordinate of the to-be-processed tensor in a coordinate system determined by the original tensor, the plurality of requests are used for sequentially acquiring data of the original tensor from the original tensor by taking the starting coordinate as a starting point until the number of the acquired data is equal to the number of pixels included in the tensor to be processed, and the data loaded by each request belong to the data range of the original tensor or do not belong to the data range of the original tensor.

The invention provides a data loading method, a data storage method, a processor, electronic equipment and a medium. The data loading method comprises the steps of determining a plurality of first requests for loading a to-be-processed tensor based on an obtained loading mode of the to-be-processed tensor, a shape and a size of the to-be-processed tensor, a data storage format of the to-be-processed tensor and an initial coordinate of the to-be-processed tensor in a coordinate system determined by an original tensor; sequentially sending a first request in the kth loading request group in the X loading request groups, and sequentially obtaining data from the storage space to obtain first data returned by the kth loading request group; in response to the situation that the size of the first data returned by the kth loading request group is not aligned according to the multiple of Y, the first data is filled to obtain second data, and the size of the second data obtained through filling is aligned according to the multiple of Y; and writing the second data into the cache region. According to the data loading method, the complexity of instructions is reduced, and the overall performance of the processor is improved.

The invention relates to a tensor data movement accelerator. One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster comprising a plurality of graphics cores and tensor processing circuitry. The tensor processing circuit includes: a local memory; a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply-accumulate operation; and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory and a local memory coupled to the memory interface. The tensor data moving accelerator includes circuitry configured to convert tensor data from a first tensor format to a second tensor format.

The invention discloses a neural radiation field rendering method based on dynamic hash coding, and the method comprises the steps: employing the feature sequence data as the input, calculating the density value and color value of each sampling point through the forward propagation of a neural network, carrying out the volume rendering integral operation according to the ray tracing principle in the direction of a ray, and obtaining the feature sequence data; judging a final color output result of the current pixel point; according to an error value between the color output result and a real image, updating a network parameter weight through a back propagation algorithm, and if the error value is greater than a convergence threshold, continuing to iterate the training process to adjust a feature coding strategy to obtain an optimized neural radiation field model parameter; and after the rendering performance configuration parameters are obtained, optimizing a storage allocation strategy of feature data through a memory pool management mechanism, and if the current memory occupancy rate exceeds a safety threshold, starting a data compression algorithm to reduce the storage space requirement, and obtaining a real-time rendering output result. According to the invention, high-quality real-time rendering of the dynamic scene is realized.