1112 results about "Memristor" patented technology

The invention discloses a machine vision-based resistor disc defect online detection system and a grading method, relates to the technical field of industrial machine vision detection, and solves the defect problems in the aspects of multi-scale defect dynamic perception, cross-level feature interaction and process adaptive optimization in the prior art. According to the scheme, metal reflection interference is inhibited through Retinex illumination correction and a combined denoising model; adopting a deformable convolution kernel and cavity space pyramid pooling to realize gradient entropy driving dynamic sensing of the multi-scale defect; constructing a bidirectional cross-layer attention network to realize early fusion of high-resolution details and high-level semantics; modeling local-global feature physical association based on a graph attention network and a self-supervised message passing mechanism; integrating reinforcement learning and a memristor random calculation unit to form a closed-loop parameter optimization system; according to the method, the multi-scale defect detection precision, the cross-modal feature fusion efficiency and the system adaptive capacity under complex working conditions are remarkably improved.

The invention relates to the field of artificial intelligence hardware acceleration, and discloses a memristor-based multilevel compression collaborative optimization neural network deployment method and device, and a storage medium. The method comprises the following steps: carrying out progressive structured pruning on a pre-training model based on a dual-drive scoring mechanism of an L1 norm and gradient sensitivity and hardware feedback, and generating a hardware-friendly sparse weight structure; the characteristics of the memristor are simulated through a micro-nonlinear conductance modeling function, and network weight and conductance parameters are synchronously optimized to reduce errors by adopting mixed precision quantification of four bits of a convolutional layer and two bits of a full-connection layer; a conductance drift and read-write noise model is injected, and the anti-interference capability of the model is improved in combination with adaptive noise enhancement and KL divergence loss; and mapping the optimized model to a memristor memory architecture to complete weight coding and reasoning. Through collaborative optimization of pruning, quantification and distillation, the problems of insufficient storage density, non-ideal characteristic interference and algorithm and hardware mismatch in memristor deployment are solved.

The invention discloses a fault diagnosis and remote monitoring system and method for a solar power supply system, and relates to the technical field of fault diagnosis of a solar system, and the system comprises a heterogeneous multi-mode sensing module which collects the multi-dimensional information of an assembly through a plurality of sensors; the memristor storage and calculation integrated unit is used for realizing data filtering and feature extraction; the multi-scale causal diagnosis engine is used for diagnosing faults by fusing deep learning and causal diagrams; a self-adaptive topology communication network ensures data transmission; a digital twinborn monitoring platform and visual operation and maintenance are adopted, and in addition, an intelligent evolution decision and self-reconfiguration sensor network module is further arranged, so that the intelligence and reliability of the system are improved. Through cooperation of multiple modules, accurate fault diagnosis and positioning are realized, the diagnosis time is shortened, stable data transmission is ensured, self-repairing and autonomous learning capabilities are provided, the operation and maintenance cost can be reduced, the power generation efficiency can be improved, and the reliability and economic benefits of a solar power supply system can be enhanced.

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

A hardware emulator and an emulation system including the hardware emulator are provided. The hardware emulator includes an artificial neural network-based reconstruction model configured to reconstruct dynamics of a dynamical system based on input data and a memristor-based circuit configured to emulate state space representation of the dynamical system based on the reconstruction model.

The invention discloses a motion recognition method and system based on a redox photoelectric memristor, a terminal and a storage medium, and the method comprises the steps: selecting classical motions based on a human body motion data set, extracting time sequence data, and coding the time sequence data into an optical pulse sequence; constructing a reservoir array composed of a plurality of photoelectric memristors, and expanding an optical pulse sequence signal into a high-dimensional state vector; constructing a supervised training model, solving a weight matrix, and constructing a memristive cross array; and outputting an action classification result through simulation domain operation based on the output current multi-path light current signals in combination with the memristor cross array. According to the method, the motion features can be directly fed into a rear-end classification network for action recognition without depending on a complex digital feature extraction algorithm, so that the transmission and processing overhead of redundant data is fundamentally eliminated; a high-efficiency, low-delay and high-robustness hardware solution is provided for real-time and anti-noise motion recognition in scenes such as intelligent monitoring and man-machine interaction.

The invention relates to the technical field of image encryption, in particular to an image chaotic encryption method based on a magnetic control memristor and electronic equipment, and the method comprises the steps: obtaining an input image; calculating a hash value or generating a random challenge value according to the input image to determine input excitation; judging whether the magnetic field intensity is in a set legal magnetic field domain; if so, calling a real response path of the magnetic control memristor to generate a real response code stream at least according to the input excitation and the magnetic field intensity; constructing a chaotic parameter and a disturbance source according to the real response code stream, and injecting the chaotic parameter and the disturbance source into the fractional order hyperchaotic system; generating a dynamic key stream through a fractional order hyper-chaotic system according to the chaotic parameters; the dynamic secret key stream is combined with a mapping algorithm to globally scramble pixels of an input image, the dynamic secret key stream and a disturbance source are used to carry out bidirectional diffusion on the scrambled image, and a chaotic encryption image is obtained. According to the invention, the magnetic control memristor PUF and the fractional order hyper-chaotic system are deeply fused, and a hardware and algorithm collaborative image encryption mechanism is realized.

According to the hybrid fitting FPGA technology chaotic signal generator implementation method, a memristive chaotic system with complex nonlinear characteristics such as a hyperbolic function and a natural logarithm can be efficiently generated on a resource-limited FPGA. According to the scheme, target function slope distribution is analyzed, binomial fitting is adopted for slope steep intervals, hardware architecture is optimized to reduce resource occupation, and linear fitting is adopted for slope gentle intervals to simplify implementation logic. According to the memristor chaotic system model constructed based on the hybrid strategy, an iterative operation module is integrated on a chip. Experimental verification shows that the method obviously reduces the consumption of storage resources while keeping high precision, and is particularly suitable for chaotic signal generation scenes with low power consumption and high real-time requirements.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention provides a heterojunction memristor based on a two-dimensional material CrPS4 and a preparation method of the heterojunction memristor, and relates to the field of microelectronic semiconductor material photoelectric memristors. The heterojunction memristor comprises a substrate, a two-dimensional material CrPS4-based heterojunction and an active metal electrode which are stacked in sequence. According to the vertical heterojunction memristor disclosed by the invention, the prepared novel two-dimensional material CrPS4 is adopted as a resistive function layer material, and the vertical heterojunction memristor shows excellent non-volatile resistive property.

The invention discloses a direct current charging pile detection system and method applied to the field, and relates to the technical field of power equipment on-line monitoring, and the method comprises the steps: inputting a three-dimensional data set into a Toeplitz cyclic measurement matrix for compressed sampling, reconstructing the three-dimensional data set into a high-resolution signal through employing an improved orthogonal matching pursuit algorithm, and carrying out the detection of the high-resolution signal; analyzing and calculating a local variable coefficient through a sliding window, marking abnormal positions, and integrating the abnormal positions into an abnormal position set; inputting the abnormal position set into a pre-trained long and short term memory prediction model, evaluating the insulation residual life and the fault risk level, and calculating the maximum allowable output current of the DC charging pile in real time; the load impedance is dynamically adjusted and detected through the memristor array, the output current of the direct current charging pile is collected in real time, and synchronous compression wavelet transform is adopted to analyze a harmonic ridge line and extract a harmonic component; the accuracy of fault early warning is remarkably improved, rapid dynamic adjustment of the output current is achieved, and the technical problem of multi-physics field coupling monitoring of the rapid charging pile is effectively solved.

The invention relates to a heterogeneous neural network acceleration device based on cooperation of a DSP (Digital Signal Processor) and a memristor, which adopts a hybrid computing architecture design of a DSP and memristor cross array, such as dynamic precision switching, a real-time closed-loop feedback mechanism based on a Lyapunov stability theory, a self-adaptive cross-domain quantization module, hardware instruction set optimization and the like. The hybrid architecture has good balance performance and universality, stability is remarkably improved through conductivity monitoring, self-adaptive PWM pulse generation and quantization table updating, a higher signal-to-noise ratio is achieved at lower cost through combination of a self-adaptive cross-domain quantization module and noise reduction, hardware level optimization is achieved through customization of an instruction set, the hybrid architecture is more suitable for an HNN calculation task, and the method is suitable for the HNN calculation task. The energy efficiency ratio and the anti-drifting capability of the HNN acceleration circuit are improved, and the acceleration performance is improved.

The invention discloses a peak code modulation circuit based on a dynamic memristor, which comprises the dynamic memristor and a signal conversion module, and is characterized in that the signal conversion module comprises a signal isolation module, a feature extraction module and a pulse conversion module which are connected in sequence. The dynamic memristor generates a voltage signal with a slow-rising and steep-falling characteristic under constant current input. The signal isolation module comprises a high-impedance input buffer circuit; the feature extraction module comprises an asymmetric time constant signal processing circuit used for performing enhanced extraction on the steep drop feature of the memristor output signal; and the pulse conversion module comprises a dual-threshold positive feedback hysteresis comparison circuit and is used for converting the output signal of the feature extraction module into a rectangular digital pulse. The circuit is specially designed according to the characteristics of the memristor, is simple in structure, is easy to integrate, can achieve the efficient conversion from an analog signal to a standard digital pulse, and is suitable for the fields of neuromorphic calculation and low-power-consumption signal processing.

The invention belongs to the technical field of brain-like calculation and storage calculation integrated chips, and particularly discloses a memristor differential double sub-array structure, a convolution acceleration system and application, the memristor differential double sub-array structure comprises two parallel sub-arrays which are not directly and electrically connected, the two sub-arrays comprise the same number of memristors, and the memristors are arranged in the parallel sub-arrays. The memristors in the two sub-arrays are paired to form a differential unit, and each differential unit stores a weight parameter in the convolution kernel in a differential form and participates in convolution operation; and the memristors in the same sub-array are connected in parallel. And by combining the differential double-subarray structure and the transimpedance amplification reading circuit, the fluctuation and noise of the device can be effectively suppressed, and the precision and stability of convolution calculation are improved. According to the method, efficient convolution operation and feature extraction can be realized on the edge side, the method has the advantages of low power consumption, multi-resistance-state controllability, high integration and the like, the method is suitable for various edge intelligent scenes such as image recognition, mode detection, video monitoring, inspection analysis and the like, and the intelligent processing capacity of the terminal side is improved.

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

The invention provides a memristor based on a quasi 2D / 3D heterojunction perovskite and a preparation method and application of the memristor. The invention belongs to the technical field of memristors. In the memristor, a three-dimensional (3D) (FAPbI3) 0.95 (MAPbBr3) 0.05 perovskite thin film and a CF3-PEAI quasi-two-dimensional perovskite thin film are prepared by adopting a spin coating method and are used as functional layers of the memristor. The device has a stable I-V cycle characteristic, not only can realize a stable conductivity adjustable characteristic under positive and negative voltages, but also can accurately simulate a recognition task of a handwritten data set by utilizing the device and linear updating for enhancing and inhibiting a conductivity weight, and the accuracy rate can reach 94%. The invention aims to provide the perovskite memristor with a novel structure so as to meet the requirements of efficient neural synaptic bionic and brain-like computing system construction.

An electrical memristive device has a layer structure. The layer structure comprises two electrodes and a bilayer material arrangement that connects the two electrodes. The bilayer material arrangement may, for example, be sandwiched by the two electrodes, in direct contact therewith. The bilayer material arrangement includes an HfOy layer, where 1.3±0.1≤y<1.9±0.1, as well as a WOx layer in direct contact with the HfOy layer, where 2.5±0.1≤x<2.9±0.1. The bilayer arrangement involves sub-stoichiometric layers of HfOy and WOx, where the WOx layer may advantageously have a polycrystalline structure in the monoclinic phase, while the HfOy layer is preferably amorphous.

Provided in the embodiments of the present disclosure are a storage unit, a memristor array, a compute-in-memory circuit and an operation method. The storage unit comprises n weight units and a lateral gate transistor. Each of the n weight units comprises a first memristor element and a first switch element, a first electrode of the first memristor element being electrically connected to a first electrode of the first switch element, and a second electrode of the first memristor element being used as a second end of the corresponding weight unit and being used for receiving a first bit line signal. The second electrodes of the first switch elements of the N weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other, and are electrically connected to a first end of the lateral gate transistor. The control electrodes of the first switch elements are respectively used for receiving different first word line signals. A second end of the lateral gate transistor is used for receiving a source line signal, and a control end of the lateral gate transistor is used for receiving a second word line signal.

The invention relates to the technical field of electronic devices, in particular to a single-molecule photoelectric memristor based on photoresponse rotating shaft molecules and a preparation method of the single-molecule photoelectric memristor. The single-molecule electric memristor comprises a light response rotating shaft molecule and a graphene point electrode pair, and the light response rotating shaft molecule is connected between the graphene point electrode pair. When ultraviolet light irradiates the photoresponse rotating shaft molecule, a high conductivity state occurs when the corresponding rotating shaft molecule rotates, and when visible light irradiates the photoresponse rotating shaft molecule, a low conductivity state occurs when the corresponding rotating shaft molecule rotates. Based on this, the monomolecular photoelectric memristor has high and low conductivity bistable states, and can realize rapid and reversible change of the conductivity state, thereby improving response speed, operation efficiency, and stability, flexibility and adaptability of performance. The single-molecule photoelectric memristor provided by the invention is expected to be widely applied to the fields of neuromorphic calculation, artificial intelligence, brain-like calculation and the like. The preparation method provided by the invention is simple and convenient to operate, mild in reaction condition and beneficial to industrial production.

The invention discloses a memristor based on a covalent organic framework and a preparation method and application thereof.The memristor comprises a substrate, a semiconductor electrode, a covalent organic framework film and a metal electrode which are sequentially arranged in a stacked mode, and the covalent organic framework film is composed of 1, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 16, 17, 17, 17, 17, 17, 17, 17, 17, the catalyst is prepared by condensing 1, 3, 5-tri (4-aminophenyl) benzene and terephthalaldehyde or terephthalaldehyde with an alkyl or alkoxy side chain. The covalent organic framework film has a highly ordered structure and an adjustable porous structure, the preparation process is simple, the film thickness is uniform, the flatness and the crystallinity are high, and the dielectric property is adjusted, so that the switching voltage and the cycling stability of the memristor are adjusted, and the memristor has stable and repeatable switching performance; the COFs-based memristor has high on / off ratio, low device variability and high flexibility, can be used for preparing the COFs-based memristor, can provide technical support for neuromorphic devices with high efficiency, adjustability, structure adjustability and rich functions, and can be applied to the field of intelligent sensing and autonomous system control such as an auxiliary driving system.

The invention discloses an environment-emotion gradient association memristive neural network circuit based on a TAP cell regulation mechanism. The environment-emotion gradient association memristive neural network circuit is composed of a hippocampus module and an amygdala kernel module. The hippocampus module comprises an environment recognition neuron module and an emotion generation neuron module; the environment recognition neuron module and the emotion generation neuron module are each composed of a weight regulation and control module adj based on a TAP cell regulation mechanism, an adder, a memristor, a resistor, an operational amplifier, a function module ABM1 and a sampling holder. Wherein the weight regulation and control module adj is composed of a voltage-controlled switch, a summator, a function module ABM2 and a function module ABM3. The almond kernel module is composed of a weight regulation and control module adj, a memristor, a resistor, an operational amplifier and a sampling holder. The provided circuit simulates the hippocampus and amygdala nucleus of the brain in structure, the regulation principle of TAP cells on neural stem cells is used for reference in a weight regulation mechanism, and bidirectional gradient associated memory of the environment and the emotion can be achieved.

The invention belongs to the technical field of organic / polymer information storage, and particularly provides a photoelectric memristor based on a covalent organic framework film and preparation and application of the photoelectric memristor. According to the invention, a photoelectric memristor based on a donor-redox covalent organic framework (COF, COF) is utilized, so that the photoelectric memristor can be applied to the field of photoelectric memristors, and therefore, the photoelectric memristors can be applied to the field of photoelectric memristors. The structure of the device is a classic sandwich structure, the bottom electrode is a glass substrate plated with ITO, and the active layer is a BTT-Cu3 COF film. The prepared ITO / BTT-Cu3 COF / ITO device has the advantages of quick response and high energy efficiency, and the refresh rate and the recognition precision higher than those of a traditional electronic device can be obviously realized. The high frequency refresh capability ensures that rapidly changing information, such as motion trails or environmental changes, can be captured and processed in real time.

This electronic circuit implements calculation operations each providing a binary output, and comprises word lines; pairs of complementary bit lines; source lines; a set of memory cells organized according to a matrix including rows and columns, the memory cells of a same row being selectable by a word line, the memory cells of a same column being connected to a pair of complementary bit lines and to a source line; and a reading device implemented during each calculation operation. Each memory cell comprises two memristors and two switches.The reading device includes:a logic unit for each column, each being configured to perform a logic operation presenting a switching between a low value and a high value depending solely on the value of the input of the logic unit which is connected to a respective source line during said calculation operation,a module for converting a number of high or low values at the output of the logic units into an intermediate value dependent on said number of high / low values, the latter being an electrical value the variation of which over time depends on a time constant which is a function of said number of high / low values, anda comparison module for comparing the intermediate value with a reference value and for outputting a single-bit digital signal dependent on the comparison.

The invention discloses a communication system signal receiving method, circuit, device and equipment based on a memristor, and belongs to the field of integrated circuits and the field of communication signal processing. According to the communication system signal receiving method provided by the invention, element values of a real number field channel matrix and a variance value of a noise signal vector are mapped into a conductivity value of a memristor, a real number field receiving signal vector is mapped into a voltage signal vector, the voltage signal vector is input into an analog domain calculation circuit, the output of the circuit is measured, and detection of all emission signal components is realized. The communication system signal receiving circuit, device and equipment are realized based on the method. Compared with a traditional processor based on digital domain calculation, the analog domain calculation circuit based on the memristor, which is realized by aiming at a serial interference elimination detection algorithm, is shorter in calculation delay and higher in energy efficiency, and compared with an existing linear detection algorithm circuit based on the memristor, the analog domain calculation circuit based on the memristor has the advantages of better detection performance and lower bit error rate.

The present invention discloses a memristor based on a GaN / PEDOT:PSS planar heterojunction and a preparation method thereof, including a substrate; a GaN thin film, the GaN thin film is p-type conductive, and the GaN thin film is attached to the surface of the substrate; a PEDOT:PSS organic layer, the PEDOT:PSS organic layer is p-type conductive, and the PEDOT:PSS organic layer is attached to the surface of the GaN thin film; a first electrode, forming an ohmic contact with the GaN thin film; and a second electrode, forming an ohmic contact with the PEDOT:PSS organic layer. Through the combined action of the space charge layer generated by the GaN / PEDOT:PSS heterojunction and the nitrogen vacancies in the GaN thin film, the present invention can realize the switching of the device resistance between the high resistance state and the low resistance state under the control of an external voltage, and realize the non-volatile writing and erasing of data.

The invention discloses a real-time reserve pool calculation method and system based on pulse amplitude information coding, and belongs to the technical field of reserve pool calculation of space-time sequence tasks. The method comprises the steps that modal information in a real environment is received and preprocessed, encoding is carried out according to time steps, and the codes are pulse sequences with different pulse amplitudes; feeding the pulse sequence into an SL end of a volatile memristor array, writing the pulse sequence into the volatile memristor array, and receiving nonlinear response current of dynamic volatile memristor array space projection at a BL end in real time; receiving the response current by the FPGA, sampling at equal intervals to construct a virtual node, converting the response current into a voltage signal through a TIA, and feeding the voltage signal into a pre-trained nonvolatile memristor array for reasoning; and receiving the response current, outputting a maximum value corresponding neuron index through the WTA winner eating circuit, representing a classification or prediction result, and transmitting the result back to an upper computer or performing action decision at a local end.

The invention relates to the technical field of AI audio chips, and discloses an audio processing model quantification method and system, and the method comprises the steps: applying an incremental voltage pulse to a multi-layer memristor cross array, measuring a conductivity value, and generating a memristor quantification configuration table; programming the neuron units in the multi-layer memristor cross array to obtain quantized neuron units; calculating a synaptic weight matrix; the audio signal to be processed is input into the quantization neuron unit to execute pulse calculation, the audio features are obtained, and the audio recognition result is generated on the end-side processor, so that the problems of nonlinearity and element difference of the memristor are effectively solved, the robustness of the system is improved, and the optimal balance of precision and power consumption can be realized in different scenes.

The invention discloses a design method and an implementation circuit of a discrete local active memristor. The design method comprises the following steps: determining a discrete iterative operation model of the discrete local active memristor; determining a modular framework of the discrete local active memristor comprising a nonlinear function module; and selecting a nonlinear function module to complete the design of the discrete local active memristor. Through the determination of the discretization iteration operation model and the modularization framework of the discrete type local active memristor, the design of the discrete type local active memristor and the realization of the corresponding circuit are realized, and the reliability, the accuracy and the adaptability are higher.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

The invention belongs to the technical field of external diagnosis devices, and particularly relates to a memristor for adenovirus concentration detection and a preparation method of the memristor. The memristor comprises a bottom electrode layer, a metal oxide layer, a functional layer and an upper electrode layer which are sequentially formed from bottom to top in the thickness direction, the bottom electrode layer is an FTO conductive glass layer, the metal oxide layer is tantalum pentoxide, the functional layer is a gelatin-beta cyclodextrin composite film, and the upper electrode layer is a conductive electrode layer. The gelatin-beta cyclodextrin composite film with the memristive effect serves as a functional layer, after the film makes contact with adenoviruses, the film adsorbs virus particles, then the unique resistance change characteristic of the memristor is caused, the memristive behavior of the memristor is further fed back, and the memristive effect of the memristor is improved. The method is used for recording and analyzing the electrochemical or bio-electricity signal characteristics of adenovirus solutions with different concentrations, the adenovirus solutions with different concentrations are effectively distinguished according to the electric signal difference of the adenovirus solution and the control solution, the effect is obvious, and the repeatability is good.