1397 results about "Memristor" patented technology

The invention discloses a memristor-based neuron circuit, comprising a synaptic circuit, a neuron activation function circuit and a synaptic weight control circuit. In the synaptic circuit, a memristor, under the control of four MOS tubes, changes the memristor value to simulate the change of the synaptic weight in the neuron network. The designed neuron synaptic circuit is capable of being directly connected with a digital logic electrical level so as to achieve convenient and real-time adjustment to the synaptic weight and through the use of the feature that the output voltage of an operational amplifier is restricted by the power supply voltage, the neuron circuit activation function can be realized as a saturated linear function. The neuron synaptic weight change circuit can utilize the existing CMOS micro-controller and at the same time, the micro-controller can be loaded by the neuron network algorithm to change the synaptic weight to realize corresponding functions. According to the invention, a plurality of neuron circuits could be connected into a large-scale neuron network for complicated functions such as mode identification, signal processing, associated memory and non-linear mapping, etc.

The invention discloses a feedback artificial neural network training method and a feedback artificial neural network calculating system and belongs to the field of calculation of neural networks. According to the artificial neural network training method, the synapse weight is adjusted according to a feedforward signal and a feedback signal at the two ends of each neural synapse; when the signals at the two ends of each neural synapse are an excitation feedforward signal and an excitation feedback signal respectively, the synapse weight is adjusted to the maximum value; when the signals at the two ends of each neural synapse are a tranquillization feedforward signal and an excitation feedback signal respectively, the synapse weight is adjusted to the minimum value. According to the feedback artificial neural network calculating system, each node circuit comprises a calculating module, a feedforward module and a feedback module and the node circuits are connected through the neural synapses simulated by memristors, and a series of pulse signals are adopted to achieve the feedback artificial neural network training method. An artificial neural network provided by the system and the method is high in rate of convergence, and the artificial neural network calculating system is few in control element, low in energy consumption and capable of being applied to data mining, pattern recognition, image recognition and other respects.

The invention discloses a memristor-based neuron circuit. According to the neuron circuit, partially volatile bipolar resistive transition devices are selected and used as memristors of a synapse array, and a volatile resistive transition device is selected and used as a memristor for expressing membrane potential of neurons, so that the neuron circuit is formed; and synapse basis units are arranged. The neuron circuit can realize an integral discharge function in biological neurons and express local graded potentials; and synapses have partial volatility, can express spike-timing-dependent plasticity, and have great similarity with biological neurons and synapses in the aspects of information storage, transmission and processing. According to the neuron circuit, the basic units can be provided for hardware to simulate a cerebral neural network structure; the technical problems of neuron discharge time delay, difficulty in realizing high-density integration and the like in the prior art are solved; and the neuron circuit can be used for constructing a brain-like information processing system, can quickly process a large amount of information in parallel, and has a greatly high application value in realizing a cerebral neurologic calculation network.

The invention discloses a memristor based image identification system and method. The system comprises an image signal extracting module, a plurality of memristor based neural network modules, and an identification module, wherein an input end of the identification module is connected with an output end of each neural network module, and an input end of each neural network module is connected with an output end of the signal extracting module. The method includes the following steps that (1) a feature vector of a gray level image to be identified is acquired and input into the neural network modules; (2) each neural network module grades and identifies the feature vector according to an image model of each neural network module; (3) a difference value between a value of each neural network module and obtained standard values during training is calculated, and the classification of an image to be identified is judged according to the difference value. The memristor based image identification system has good expansibility, high integration density, and low power consumption; the method has low time complexity and high identification accuracy.

The invention discloses a memristor-based logical gate circuit. An and-gate circuit comprises a first memristor, a second memristor, a third memristor, a single-directional conduction element and a first resistor; the input end of the first memristor is used as a first input end of the and-gate circuit, and the input end of the second memristor is used as a second input end of the and-gate circuit; and the output end of the third memristor is used as an output end of the and-gate circuit. An or-gate circuit comprises a fourth memristor, a fifth memristor and a second resistor; the input end of the fourth memristor is used as a first input end of the or-gate circuit, and the input end of the fifth memristor is used as a second input end of the or-gate circuit; and one end of the second resistor is connected with the output end of the fourth memristor and the output end of the fifth memristor, and the other end of the second resistor is used as an output end of the or-gate circuit. A not-gate circuit comprises a sixth memristor, a seventh memristor, a three-state gate and a third resistor; the input end of the sixth memristor is used as an input end of the not-gate circuit; and the output end of the seventh memristor is used as an output end of the not-gate circuit.

A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

A semiconductor device, including: a first transistor sharing a first diffusion with a second transistor; a third transistor sharing a second diffusion with the second transistor; and at least one programmable resistor; wherein the at least one programmable resistor is connected to the first diffusion and the second diffusion, wherein the at least one programmable resistor includes one of the following: memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

The invention discloses a training device for a memristor-based neural network and a training method thereof. The neural network comprises N neuron layers which are connected one by one. The trainingmethod comprises the following steps of: inputting input data into a first neuron layer of the neural network so as to output an output result of the neural network at the Nth neuron layer, and calculating an output error of the Nth neuron layer; and counter-propagating the output error of the Nth neuron layer in a layer-by-layer manner so as to correct weight parameters between the neuron layers;and in the layer-by-layer counter-propagation process, three-valuing an output error of the mth neuron layer, and reversely inputting a voltage signal corresponding to an output result of the three-valuing operation to the mth neuron layer so as to correct a weight parameter of the mth neuron layer, wherein N is an integer greater than or equal to 3, and m is an integer greater than 1 and smallerthan N. According to the training method, the calculation ability of the memristor-based neural network is improved.

In one example, an integrated circuit includes two integrated circuit dies that are face-to-face mounted together. The first integrated circuit die includes passive variable resistance memory and the second integrated circuit die includes memory control logic (e.g., CMOS logic circuit). The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the first integrated circuit die is electrically connected to the memory control logic on the second integrated circuit die through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the second integrated circuit die operatively coupled to the memory control logic.

The invention discloses an artificial synaptic device based on a photoelectric coupling memristor and a modulation method of the artificial synaptic device. The artificial synaptic device comprises an upper electrode, a lower electrode and a functional material layer, wherein the functional material layer is arranged between the upper electrode and the lower electrode, the upper electrode, the functional material layer and the lower electrode jointly form a sandwich structure, the functional material layer is made of a material having a photoelectric effect, the lower electrode is a transparent conductive electrode, an electrical signal is input through the upper electrode and the lower electrode, and an optical signal is input through the transparent conductive electrode. In the artificial synaptic device provided by the invention, light is introduced as a control signal of the other end except the electrical signal, two control ends of the artificial synapse device are expanded to three ends, the artificial synaptic device can generate resistance change under an external optical excitation signal by the additionally-arranged end, the artificial synaptic device can be configured to be in a plurality of resistance states correspondingly by selection and control of intensity, frequency and optical pulse time of the optical excitation signal, and various synaptic plasticity functions are correspondingly achieved.

An apparatus and method provides the foundation for designing reconfigurable electronic computing systems. The invention relies on an ability to change the resistance state of a memristor device to achieve an optimal voltage at specific circuit nodes, whereby this dynamically and autonomously causes the circuit to reconfigure itself and produce a different output for the same input relative to the circuit's initial state. The circuit's state remains constant until the memristor's resistance is changed, at which point the circuit's function is “reprogrammed”.

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.

A physical unclonable function (PUF) device consisting of a hybrid CMOS-memristor circuit that leverages variations in the required write-time of a memristor. Variations in the time required to write, or SET, a memristor from a high to low resistance state arise from variability in physical parameters such as the memristor thickness. When applying a SET voltage across the memristor for the nominal minimum SET time, variability leads to a situation where the memristor will actually SET to the low resistance state only 50% of the time. When the device does not SET it will remain in the high resistance state. Since the to resistance state of the memristor corresponds to reading either a logic 1 or logic 0 on the output of the circuit, the write-time based memristive PUF produces a digital signature directly corresponding to the fabrication process-induced physical variations of an integrated circuit.

The invention discloses a memristor equivalent simulation circuit which comprises a resistance network, an integrated operational amplifier U1 and a multiplying unit 2. Two ends of the resistance network are respectively connected input ends (A and B), the resistance network is connected with the integrated operational amplifier U1 which is used for achieving voltage following, reversing amplification and integral operation, the integrated operational amplifier U1 is connected with the multiplying unit 2 connected with the resistance network, and the multiplying unit 2 is used for achieving multiplying of signals. The TiO2 memristor equivalent simulation circuit is used for simulating voltage current characteristics of a memristor and replacing a practical meristor to carry out experiments, application and research.

A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.

The invention discloses a memristor hyperchaos system and circuit with abundant dynamic behaviors. The new fifth-order memristor hyperchaos system is provided and has the abundant chaos dynamic behaviors and phase track graphs at different angles, and the different chaos behaviors such as grids and scrolls can be seen. A basic step for generating a complex dynamic chaos system through a memristor in future is made.

An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed.

In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.