1362 results about "Memristor" patented technology

The invention discloses a machine vision-based resistor disc defect online detection system and a grading method, relates to the technical field of industrial machine vision detection, and solves the defect problems in the aspects of multi-scale defect dynamic perception, cross-level feature interaction and process adaptive optimization in the prior art. According to the scheme, metal reflection interference is inhibited through Retinex illumination correction and a combined denoising model; adopting a deformable convolution kernel and cavity space pyramid pooling to realize gradient entropy driving dynamic sensing of the multi-scale defect; constructing a bidirectional cross-layer attention network to realize early fusion of high-resolution details and high-level semantics; modeling local-global feature physical association based on a graph attention network and a self-supervised message passing mechanism; integrating reinforcement learning and a memristor random calculation unit to form a closed-loop parameter optimization system; according to the method, the multi-scale defect detection precision, the cross-modal feature fusion efficiency and the system adaptive capacity under complex working conditions are remarkably improved.

The invention relates to the field of artificial intelligence hardware acceleration, and discloses a memristor-based multilevel compression collaborative optimization neural network deployment method and device, and a storage medium. The method comprises the following steps: carrying out progressive structured pruning on a pre-training model based on a dual-drive scoring mechanism of an L1 norm and gradient sensitivity and hardware feedback, and generating a hardware-friendly sparse weight structure; the characteristics of the memristor are simulated through a micro-nonlinear conductance modeling function, and network weight and conductance parameters are synchronously optimized to reduce errors by adopting mixed precision quantification of four bits of a convolutional layer and two bits of a full-connection layer; a conductance drift and read-write noise model is injected, and the anti-interference capability of the model is improved in combination with adaptive noise enhancement and KL divergence loss; and mapping the optimized model to a memristor memory architecture to complete weight coding and reasoning. Through collaborative optimization of pruning, quantification and distillation, the problems of insufficient storage density, non-ideal characteristic interference and algorithm and hardware mismatch in memristor deployment are solved.

The invention discloses a bionic moving target sensing, storage and calculation integrated photoelectric detection system based on continuous photoconduction, and relates to the field of bionic intelligent vision and the field of brain-like calculation, and the system comprises a synaptic bionic photoelectric detector array and a brain-like memristor array which are interconnected. When the synaptic-like bionic photoelectric detector array detects visual information of a moving target, a fixed bias voltage is applied to a device in each pixel, space illumination information corresponding to each pixel is converted into a continuously attenuated photocurrent signal, illumination information of a multi-frame dynamic target is continuously received in the continuous attenuation process of the photocurrent, and the visual information of the moving target is detected by the synaptic-like bionic photoelectric detector array. After the last frame of illumination information is input, a light current signal of each pixel is read, and a feature map memorizing all historical moment information is determined; the brain-like memristor array is based on the Ohm's law and the Kirchhoff's law, performs deep neural network operation on the feature map, outputs a current corresponding to a task result label, identifies a dynamic target, and can meet the requirements of a deep neural network and a complex dynamic visual task.

The invention discloses a fault diagnosis and remote monitoring system and method for a solar power supply system, and relates to the technical field of fault diagnosis of a solar system, and the system comprises a heterogeneous multi-mode sensing module which collects the multi-dimensional information of an assembly through a plurality of sensors; the memristor storage and calculation integrated unit is used for realizing data filtering and feature extraction; the multi-scale causal diagnosis engine is used for diagnosing faults by fusing deep learning and causal diagrams; a self-adaptive topology communication network ensures data transmission; a digital twinborn monitoring platform and visual operation and maintenance are adopted, and in addition, an intelligent evolution decision and self-reconfiguration sensor network module is further arranged, so that the intelligence and reliability of the system are improved. Through cooperation of multiple modules, accurate fault diagnosis and positioning are realized, the diagnosis time is shortened, stable data transmission is ensured, self-repairing and autonomous learning capabilities are provided, the operation and maintenance cost can be reduced, the power generation efficiency can be improved, and the reliability and economic benefits of a solar power supply system can be enhanced.

The invention relates to the technical field of electronic devices, in particular to a monomolecular electric memristor based on dipole control and a preparation method thereof.The monomolecular electric memristor comprises a molecular heterojunction, and the molecular heterojunction is formed by connecting dipole molecules and graphene point electrodes through amido bonds; the dipole molecule comprises an amide structure based on a carbazole nitrogen-containing heterocyclic ring unit, under the action of an external electric field, a side chain chemical bond of the dipole molecule can rapidly rotate, the size and direction of an intramolecular dipole moment can be changed, the molecule can be rapidly and stably switched among different resistance states, and the read-write speed of the memristor is remarkably improved; the storage state is stably kept under the power-off condition, and the long-term stability and reliability of the memristor function are ensured. The preparation method comprises the processes of introducing dipole molecules and forming amido bonds between the dipole molecules and the graphene point electrode, and the preparation method is simple and convenient to operate, mild in condition and beneficial to large-scale production.

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

The invention discloses a memristor-based signal detection circuit and method, a receiver and equipment, and relates to the field of wireless communication, a voltage source module of the circuit is connected with a voltage input end of a memristor array module, and a current source module is connected with a current input end of the memristor array module; the current output end of the memristor array module is connected with the reverse input end of the operational amplifier module and one end of the feedback resistor module, the other end of the feedback resistor module and the output end of the operational amplifier module are connected with the input end of the multiplier module, and the output end of the multiplier module is connected with one end of the resistor module. The voltage of the voltage source module is set according to the emission vector set; the current of the current source module is set according to the received radio frequency signal, and the conductance value of the memristor is set according to the channel matrix, so that a relatively low bit error rate of signal detection can be realized on the basis of greatly reducing calculation time and power consumption, and meanwhile, the requirement on programmable bit precision of the memristor is also reduced.

The invention discloses an in-memory computing array and an operation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. A 2T1R in-memory computing array based on subthreshold current is designed, each unit in the array is composed of a memristor, a gate tube T1 and a reading tube T2, write-in and erase operations are similar to a 1T1R array architecture, but read-out is carried out through the transistor T2 working in a subthreshold region, the reading current generated by the reading tube is small, and the read-in and erase operations can be carried out through the memristor, the gate tube T1 and the reading tube T2. And the parallelism degree of in-memory calculation is increased, and ultrahigh parallel calculation of 100-1000 orders of magnitude can be realized. And meanwhile, the reading current of the reading tube T2 is in exponential correlation with the gate voltage, so that a larger switching current ratio can be obtained, and a reading window of the in-memory calculation unit is amplified. Compared with a 1T1R array architecture, more complex in-memory calculation operation can be realized, and an operation strategy can be flexibly selected, so that more efficient multiply-accumulate operation is realized.

The invention discloses an optical memristor, and relates to the field of photon integrated circuits and optical computing, and the optical memristor comprises a waveguide layer, a ferroelectric film layer, an electrode structure and a substrate. The ferroelectric film layer is located on the upper surface of the substrate; the waveguide layer and the electrode structure are located on the upper surface of the ferroelectric film layer; the waveguide layer is used for propagating an incident light signal and performing amplitude modulation on the incident light signal; the electrode structure is used for applying an electric field to the ferroelectric film layer; and the ferroelectric film layer is used for carrying out phase modulation on optical signals transmitted in the waveguide layer under the action of the electric field. The ferroelectric material is used as the optical switch of the optical memristor, efficient modulation of the optical phase is achieved through the non-volatility and the high electro-optical effect of the ferroelectric material, and meanwhile the optical memristor has the advantages of being low in energy consumption and rapid in response.

A hardware emulator and an emulation system including the hardware emulator are provided. The hardware emulator includes an artificial neural network-based reconstruction model configured to reconstruct dynamics of a dynamical system based on input data and a memristor-based circuit configured to emulate state space representation of the dynamical system based on the reconstruction model.

The invention discloses a motion recognition method and system based on a redox photoelectric memristor, a terminal and a storage medium, and the method comprises the steps: selecting classical motions based on a human body motion data set, extracting time sequence data, and coding the time sequence data into an optical pulse sequence; constructing a reservoir array composed of a plurality of photoelectric memristors, and expanding an optical pulse sequence signal into a high-dimensional state vector; constructing a supervised training model, solving a weight matrix, and constructing a memristive cross array; and outputting an action classification result through simulation domain operation based on the output current multi-path light current signals in combination with the memristor cross array. According to the method, the motion features can be directly fed into a rear-end classification network for action recognition without depending on a complex digital feature extraction algorithm, so that the transmission and processing overhead of redundant data is fundamentally eliminated; a high-efficiency, low-delay and high-robustness hardware solution is provided for real-time and anti-noise motion recognition in scenes such as intelligent monitoring and man-machine interaction.

The invention discloses a brain-computer interface signal identification circuit based on a memristor neural network. The brain-computer interface signal identification circuit is composed of three neuron circuits. Each neuron circuit is composed of nine parallel branches and comprises a signal input module, a weight adjusting module, a first summing module, a memristor, a second summing module, a sampling module and a comparison module. In a single neuron circuit, after nine paths of input signals Vin1-Vin9 are respectively processed by signal input modules, weight adjusting modules, summation modules (1) and memristors of nine parallel branches, the nine paths of signals are combined together and pass through a single summation module (2), a sampling module and a comparison module, and a single identification signal of the neuron circuit is output. According to the designed circuit, a memristor neural network circuit is built by using resistance plasticity and threshold characteristics of a memristor, the meaning of a brain-computer interface signal can be preliminarily identified through a self-learning mechanism of the memristor, and the identification precision of the brain-computer interface signal can be remarkably enhanced.

The invention relates to a memristor array-based MIMO communication system signal detection method, circuit, device and equipment, which are used in the field of wireless communication signal processing. In order to solve the problem that an existing MIMO signal detection calculation circuit based on a memristor array is very sensitive to conductance errors of memristors, an MIMO channel matrix is expressed as a product of a small-scale fading coefficient matrix and a large-scale fading coefficient matrix, and a matrix calculation expression of ZF signal detection and MMSE signal detection is converted into a new equivalent form. A matrix calculation circuit based on the memristor array is used for calculating the converted equivalent expression, and signal detection is achieved; the invention provides two kinds of matrix calculation circuit design schemes based on the memristor array, two kinds of corresponding MIMO communication system signal detection devices and three kinds of MIMO communication system signal detection equipment based on the memristor array. According to the invention, the sensitivity to the conductivity error of the memristor is lower, and the signal detection performance is better.

The invention relates to the technical field of image encryption, in particular to an image chaotic encryption method based on a magnetic control memristor and electronic equipment, and the method comprises the steps: obtaining an input image; calculating a hash value or generating a random challenge value according to the input image to determine input excitation; judging whether the magnetic field intensity is in a set legal magnetic field domain; if so, calling a real response path of the magnetic control memristor to generate a real response code stream at least according to the input excitation and the magnetic field intensity; constructing a chaotic parameter and a disturbance source according to the real response code stream, and injecting the chaotic parameter and the disturbance source into the fractional order hyperchaotic system; generating a dynamic key stream through a fractional order hyper-chaotic system according to the chaotic parameters; the dynamic secret key stream is combined with a mapping algorithm to globally scramble pixels of an input image, the dynamic secret key stream and a disturbance source are used to carry out bidirectional diffusion on the scrambled image, and a chaotic encryption image is obtained. According to the invention, the magnetic control memristor PUF and the fractional order hyper-chaotic system are deeply fused, and a hardware and algorithm collaborative image encryption mechanism is realized.

According to the hybrid fitting FPGA technology chaotic signal generator implementation method, a memristive chaotic system with complex nonlinear characteristics such as a hyperbolic function and a natural logarithm can be efficiently generated on a resource-limited FPGA. According to the scheme, target function slope distribution is analyzed, binomial fitting is adopted for slope steep intervals, hardware architecture is optimized to reduce resource occupation, and linear fitting is adopted for slope gentle intervals to simplify implementation logic. According to the memristor chaotic system model constructed based on the hybrid strategy, an iterative operation module is integrated on a chip. Experimental verification shows that the method obviously reduces the consumption of storage resources while keeping high precision, and is particularly suitable for chaotic signal generation scenes with low power consumption and high real-time requirements.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention provides a heterojunction memristor based on a two-dimensional material CrPS4 and a preparation method of the heterojunction memristor, and relates to the field of microelectronic semiconductor material photoelectric memristors. The heterojunction memristor comprises a substrate, a two-dimensional material CrPS4-based heterojunction and an active metal electrode which are stacked in sequence. According to the vertical heterojunction memristor disclosed by the invention, the prepared novel two-dimensional material CrPS4 is adopted as a resistive function layer material, and the vertical heterojunction memristor shows excellent non-volatile resistive property.

The invention discloses a direct current charging pile detection system and method applied to the field, and relates to the technical field of power equipment on-line monitoring, and the method comprises the steps: inputting a three-dimensional data set into a Toeplitz cyclic measurement matrix for compressed sampling, reconstructing the three-dimensional data set into a high-resolution signal through employing an improved orthogonal matching pursuit algorithm, and carrying out the detection of the high-resolution signal; analyzing and calculating a local variable coefficient through a sliding window, marking abnormal positions, and integrating the abnormal positions into an abnormal position set; inputting the abnormal position set into a pre-trained long and short term memory prediction model, evaluating the insulation residual life and the fault risk level, and calculating the maximum allowable output current of the DC charging pile in real time; the load impedance is dynamically adjusted and detected through the memristor array, the output current of the direct current charging pile is collected in real time, and synchronous compression wavelet transform is adopted to analyze a harmonic ridge line and extract a harmonic component; the accuracy of fault early warning is remarkably improved, rapid dynamic adjustment of the output current is achieved, and the technical problem of multi-physics field coupling monitoring of the rapid charging pile is effectively solved.

The invention relates to a heterogeneous neural network acceleration device based on cooperation of a DSP (Digital Signal Processor) and a memristor, which adopts a hybrid computing architecture design of a DSP and memristor cross array, such as dynamic precision switching, a real-time closed-loop feedback mechanism based on a Lyapunov stability theory, a self-adaptive cross-domain quantization module, hardware instruction set optimization and the like. The hybrid architecture has good balance performance and universality, stability is remarkably improved through conductivity monitoring, self-adaptive PWM pulse generation and quantization table updating, a higher signal-to-noise ratio is achieved at lower cost through combination of a self-adaptive cross-domain quantization module and noise reduction, hardware level optimization is achieved through customization of an instruction set, the hybrid architecture is more suitable for an HNN calculation task, and the method is suitable for the HNN calculation task. The energy efficiency ratio and the anti-drifting capability of the HNN acceleration circuit are improved, and the acceleration performance is improved.

The invention discloses a neural network training method suitable for memristor type brain-like chip hardware deployment. According to the method, a cross array equivalent circuit is extracted through a partial element equivalent circuit method in a training stage, and a time domain transient simulation solving process of the equivalent circuit of the cross array is integrated into gradient propagation, so that the network can learn and adapt to the output characteristics of the cross array in the training process; furthermore, an unstructured dynamic pruning method based on a weight threshold is introduced, the memristor proportion in a low resistance state is effectively reduced, sneaking paths in the cross array are inhibited, and meanwhile, the operation cost of the cross array is reduced. Compared with a traditional training method, the method provided by the invention can significantly enhance the stability and precision of the neural network during hardware deployment, has wide applicability, and can be used for neural network training and deployment optimization of various advanced memory devices.

The invention discloses an HfZrO4 memristor and a manufacturing method, relates to the technical field of memristors, can realize bidirectional resistance adjustment in a homopolar voltage region without the combination of a plurality of memristor units, and is simple in structure and convenient to manufacture. The HfZrO4 memristor comprises a Pt top electrode, an HfZrO4 resistive layer and a Pt bottom electrode which are sequentially arranged from top to bottom, the Pt bottom electrode and the Pt top electrode are conductive and then form a loop with the HfZrO4 resistive layer, and the resistance of the loop is changed by a voltage signal applied to the HfZrO4 resistive layer; the manufacturing method comprises the following steps: cutting a silicon wafer with a silicon oxide layer on the surface as a substrate, and taking the silicon oxide layer as an insulating layer; after the insulating layer is cleaned, a layer of metal Pt serves as a Pt bottom electrode through magnetron sputtering; cleaning and activating the Pt bottom electrode by adopting a plasma cleaning machine; multiple atomic layer deposition is carried out on the cleaned and activated bottom electrode according to the sequence of Hf-> H2O-> Zr-> H2O so as to generate an HfZrO4 resistive layer; and sputtering a plurality of metal Pt on the HfZrO4 resistive layer through magnetron sputtering to serve as a Pt top electrode so as to form the HfZrO4 memristor.

The invention discloses a peak code modulation circuit based on a dynamic memristor, which comprises the dynamic memristor and a signal conversion module, and is characterized in that the signal conversion module comprises a signal isolation module, a feature extraction module and a pulse conversion module which are connected in sequence. The dynamic memristor generates a voltage signal with a slow-rising and steep-falling characteristic under constant current input. The signal isolation module comprises a high-impedance input buffer circuit; the feature extraction module comprises an asymmetric time constant signal processing circuit used for performing enhanced extraction on the steep drop feature of the memristor output signal; and the pulse conversion module comprises a dual-threshold positive feedback hysteresis comparison circuit and is used for converting the output signal of the feature extraction module into a rectangular digital pulse. The circuit is specially designed according to the characteristics of the memristor, is simple in structure, is easy to integrate, can achieve the efficient conversion from an analog signal to a standard digital pulse, and is suitable for the fields of neuromorphic calculation and low-power-consumption signal processing.

The invention discloses a driving information security management system and method based on a memristor neural network, and relates to the technical field of information security, and the method comprises the steps: S1, monitoring the synchronism of a response system and a driving system in real time, and collecting feedback signal data; s2, analyzing and designing a synchronous controller through a Lyapunov stability theory; s3, dynamically selecting an information encryption mode by using the memristor neural network according to the synchronization error, the feedback signal and the signal encryption level; s4, ensuring that the probability that the encrypted information is decrypted in the driving feedback interval is lower than a set threshold value; and S5, extracting and analyzing the historical encryption signal, and updating an information encryption mode and a network security level. Based on the Lyapunov stability theory, the synchronous controller is constructed, the signal encryption level is dynamically adjusted by using the memristor neural network, and high-level safety is ensured to be kept in the dynamic change process.

The invention belongs to the technical field of brain-like calculation and storage calculation integrated chips, and particularly discloses a memristor differential double sub-array structure, a convolution acceleration system and application, the memristor differential double sub-array structure comprises two parallel sub-arrays which are not directly and electrically connected, the two sub-arrays comprise the same number of memristors, and the memristors are arranged in the parallel sub-arrays. The memristors in the two sub-arrays are paired to form a differential unit, and each differential unit stores a weight parameter in the convolution kernel in a differential form and participates in convolution operation; and the memristors in the same sub-array are connected in parallel. And by combining the differential double-subarray structure and the transimpedance amplification reading circuit, the fluctuation and noise of the device can be effectively suppressed, and the precision and stability of convolution calculation are improved. According to the method, efficient convolution operation and feature extraction can be realized on the edge side, the method has the advantages of low power consumption, multi-resistance-state controllability, high integration and the like, the method is suitable for various edge intelligent scenes such as image recognition, mode detection, video monitoring, inspection analysis and the like, and the intelligent processing capacity of the terminal side is improved.

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

The invention provides a memristor based on a quasi 2D / 3D heterojunction perovskite and a preparation method and application of the memristor. The invention belongs to the technical field of memristors. In the memristor, a three-dimensional (3D) (FAPbI3) 0.95 (MAPbBr3) 0.05 perovskite thin film and a CF3-PEAI quasi-two-dimensional perovskite thin film are prepared by adopting a spin coating method and are used as functional layers of the memristor. The device has a stable I-V cycle characteristic, not only can realize a stable conductivity adjustable characteristic under positive and negative voltages, but also can accurately simulate a recognition task of a handwritten data set by utilizing the device and linear updating for enhancing and inhibiting a conductivity weight, and the accuracy rate can reach 94%. The invention aims to provide the perovskite memristor with a novel structure so as to meet the requirements of efficient neural synaptic bionic and brain-like computing system construction.

The invention belongs to the technical field of memristors, and particularly relates to a preparation method of a high-stability heterojunction material memristor, and the method comprises the following steps: S1, making a sample, and employing a conductive material as a substrate and a bottom electrode; s2, preparing a Cs3Bi2Br9 solution, and preparing the Cs3Bi2Br9 solution by mixing CsBr powder, BiBr3 powder, DMSO (Dimethylsulfoxide) and DMF (Dimethyl Formamide); s3, mixing and stirring the Cs3Bi2Br9 solution in the S2, adding HBr after 1 hour, and then continuously stirring and mixing; s4, performing plasma treatment on the sample in the S1, and spin-coating the sample with a Cs3Bi2Br9 solution; s5, sputtering a ZnO thin film on the sample subjected to spin coating in the step S4 for end sealing; s6, plating a top electrode on the sample subjected to ZnO film end sealing; by using the ZnO thin film to seal the end, the challenge brought by the traditional solution method for constructing the active layer of the perovskite memristor at present can be overcome, the preparation repetition rate of the memristor is effectively improved, the stability of the perovskite and the reliability of the device are effectively improved, and the problem that the stability of the existing preparation method of the perovskite thin film memristor is relatively poor is solved.

An electrical memristive device has a layer structure. The layer structure comprises two electrodes and a bilayer material arrangement that connects the two electrodes. The bilayer material arrangement may, for example, be sandwiched by the two electrodes, in direct contact therewith. The bilayer material arrangement includes an HfOy layer, where 1.3±0.1≤y<1.9±0.1, as well as a WOx layer in direct contact with the HfOy layer, where 2.5±0.1≤x<2.9±0.1. The bilayer arrangement involves sub-stoichiometric layers of HfOy and WOx, where the WOx layer may advantageously have a polycrystalline structure in the monoclinic phase, while the HfOy layer is preferably amorphous.

The invention discloses a multi-dimensional interface memristor, and belongs to the field of semiconductor devices, a metal oxide / graphene two-dimensional film material is used as a switch layer of the memristor, and the preparation method comprises the following steps: carrying out hydrophilization treatment on a graphene dispersion liquid, and then carrying out first ultrasonic dispersion; adding a metal oxide quantum dot dispersion liquid, and carrying out secondary ultrasonic dispersion, so that the metal oxide quantum dots are loaded on the surface of the graphene to obtain a successfully loaded solution; and plating the successfully loaded solution on the surface of a substrate by adopting a wet coating process, and drying to form a film, thereby obtaining the metal oxide / graphene two-dimensional film switch layer. Wherein the metal oxide is SnO2, TiO2, NiO2, CeO2 or IGZO (Indium Gallium Zinc Oxide). According to the invention, the oxide quantum dots are attached to the single-layer graphene film to form the zero-dimensional quantum dot / two-dimensional graphene composite film as the switch layer of the memristor, and the method can introduce a large number of oxide / graphene interfaces, so that the regulation and control effect of the interfaces on the photoelectric characteristics of the device can be amplified.

The invention relates to the technical field of analog-to-digital converters, in particular to an on-chip adjustable non-uniform quantization analog-to-digital converter based on a memristor. Comprising a memristor array unit, an input signal conversion circuit, an output signal control conversion circuit and an on-chip adjustment circuit, the input signal conversion circuit is used for connecting an original input signal and a reference voltage and performing amplitude conversion on the input signal and the reference voltage; the memristor array unit is used for receiving the converted input signal and reference voltage and dividing the reference voltage into a plurality of reference voltage nodes; the output signal control conversion circuit is used for connecting a plurality of reference voltage nodes and outputting a digital signal in a bus form; and the on-chip adjusting circuit is used for carrying out gating adjustment on the memristor array unit, so that non-uniform quantization of data is realized, and quantization noise is effectively reduced.