455 results about "Memristor" patented technology

The invention discloses a motion recognition method and system based on a redox photoelectric memristor, a terminal and a storage medium, and the method comprises the steps: selecting classical motions based on a human body motion data set, extracting time sequence data, and coding the time sequence data into an optical pulse sequence; constructing a reservoir array composed of a plurality of photoelectric memristors, and expanding an optical pulse sequence signal into a high-dimensional state vector; constructing a supervised training model, solving a weight matrix, and constructing a memristive cross array; and outputting an action classification result through simulation domain operation based on the output current multi-path light current signals in combination with the memristor cross array. According to the method, the motion features can be directly fed into a rear-end classification network for action recognition without depending on a complex digital feature extraction algorithm, so that the transmission and processing overhead of redundant data is fundamentally eliminated; a high-efficiency, low-delay and high-robustness hardware solution is provided for real-time and anti-noise motion recognition in scenes such as intelligent monitoring and man-machine interaction.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention belongs to the technical field of brain-like calculation and storage calculation integrated chips, and particularly discloses a memristor differential double sub-array structure, a convolution acceleration system and application, the memristor differential double sub-array structure comprises two parallel sub-arrays which are not directly and electrically connected, the two sub-arrays comprise the same number of memristors, and the memristors are arranged in the parallel sub-arrays. The memristors in the two sub-arrays are paired to form a differential unit, and each differential unit stores a weight parameter in the convolution kernel in a differential form and participates in convolution operation; and the memristors in the same sub-array are connected in parallel. And by combining the differential double-subarray structure and the transimpedance amplification reading circuit, the fluctuation and noise of the device can be effectively suppressed, and the precision and stability of convolution calculation are improved. According to the method, efficient convolution operation and feature extraction can be realized on the edge side, the method has the advantages of low power consumption, multi-resistance-state controllability, high integration and the like, the method is suitable for various edge intelligent scenes such as image recognition, mode detection, video monitoring, inspection analysis and the like, and the intelligent processing capacity of the terminal side is improved.

The invention discloses an environment-emotion gradient association memristive neural network circuit based on a TAP cell regulation mechanism. The environment-emotion gradient association memristive neural network circuit is composed of a hippocampus module and an amygdala kernel module. The hippocampus module comprises an environment recognition neuron module and an emotion generation neuron module; the environment recognition neuron module and the emotion generation neuron module are each composed of a weight regulation and control module adj based on a TAP cell regulation mechanism, an adder, a memristor, a resistor, an operational amplifier, a function module ABM1 and a sampling holder. Wherein the weight regulation and control module adj is composed of a voltage-controlled switch, a summator, a function module ABM2 and a function module ABM3. The almond kernel module is composed of a weight regulation and control module adj, a memristor, a resistor, an operational amplifier and a sampling holder. The provided circuit simulates the hippocampus and amygdala nucleus of the brain in structure, the regulation principle of TAP cells on neural stem cells is used for reference in a weight regulation mechanism, and bidirectional gradient associated memory of the environment and the emotion can be achieved.

The invention belongs to the technical field of external diagnosis devices, and particularly relates to a memristor for adenovirus concentration detection and a preparation method of the memristor. The memristor comprises a bottom electrode layer, a metal oxide layer, a functional layer and an upper electrode layer which are sequentially formed from bottom to top in the thickness direction, the bottom electrode layer is an FTO conductive glass layer, the metal oxide layer is tantalum pentoxide, the functional layer is a gelatin-beta cyclodextrin composite film, and the upper electrode layer is a conductive electrode layer. The gelatin-beta cyclodextrin composite film with the memristive effect serves as a functional layer, after the film makes contact with adenoviruses, the film adsorbs virus particles, then the unique resistance change characteristic of the memristor is caused, the memristive behavior of the memristor is further fed back, and the memristive effect of the memristor is improved. The method is used for recording and analyzing the electrochemical or bio-electricity signal characteristics of adenovirus solutions with different concentrations, the adenovirus solutions with different concentrations are effectively distinguished according to the electric signal difference of the adenovirus solution and the control solution, the effect is obvious, and the repeatability is good.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

The invention relates to a memristor and a preparation method thereof. The preparation method comprises the following steps: providing an insulating substrate with a bottom electrode formed on the surface; depositing an aluminum oxide thin film on the bottom electrode by adopting electron beam evaporation under a room temperature condition to form a resistive function layer, and not performing high-temperature annealing treatment after deposition is completed, so that a primary oxygen vacancy defect is reserved in the thin film; and then depositing a top electrode on the resistive function layer through thermal evaporation or electron beam evaporation to obtain the memristor. The resistive function layer is an aluminum oxide film which is not densified through annealing, and internal defects of the resistive function layer provide a channel for metal ion migration, so that the reversible resistive characteristic is achieved. The memristor device is simple in structure and suitable for normal-temperature process preparation, the stable resistance switching behavior can be achieved, excessive densification of a film layer and thermal damage of an ITO electrode interface caused by high-temperature annealing are avoided, and the memristor has high cycle durability and nonvolatile data retention capacity and has the stable bipolar resistance change characteristic.

In certain examples, a method may include receiving a privacy parameter and selecting an electrical property range for cells in a crossbar array based on the privacy parameter. The cells in the crossbar array may then be programmed based on the selected electrical property range, which may provide a certain level of differential privacy.

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.

The invention relates to the technical field of microelectronic devices, in particular to a single-molecule memristor-rectifier device based on supramolecular assembly and a preparation method thereof. According to the preparation method, the guest molecule B is covalently connected with the tail end of the graphene electrode pair, so that stable and tight interface bonding between the supramolecular functional molecule and the electrode can be ensured; and then soaking the graphene electrode pair connected with the guest molecule B in a solution containing the host molecule A and the guest molecule C to form a supramolecular functional molecule between the graphene electrode pair. The guest molecule C in the supramolecular functional molecule has intrinsic oxidation-reduction activity, and the molecular structure of the guest molecule C can generate a reversible electron gain and loss process, so that controllable and reversible adjustment of charge distribution in the molecule is realized. Under the action of an electric field, through the reversible oxidation-reduction reaction of the guest molecule C, significant changes of intramolecular charge distribution and electron transmission characteristics are triggered, and finally reliable switching of high and low resistance states of the device is achieved.

Memristor storage unit comprising a plurality of memristor storage devices (100; 302), each of which comprises: a memristive memory cell (102, 202); an input port (104) and an output port (108) that are directly attached to the memristive memory cell (102, 202); and an electrically isolated gate terminal (112) from the memristive memory cell (102, 202) for volatile gate-induced modulation of a conductivity of the memristive memory cell (102, 202) by receiving electrical signals; the memristor storage unit further comprises: a temperature effect control unit (402) suitable for generating a portion of the received electrical signals based on a temperature-based resistance drift effect of each of the memristor storage devices (100, 302); and / or a resistance drift correction unit (404) which is suitable for generating a different part of the received electrical signals based on a time-dependent resistance drift effect of each of the memristor storage devices (100, 302).

The invention belongs to the technical field of neural networks and emotion recognition, and particularly relates to an emotion recognition method for realizing an SE-ConvNeXt network based on a memristor, according to the scheme, a lightweight ConvNeXt model is taken as a substrate, a channel attention module (SE-Block) is fused, an emotion recognition network model based on the SE-ConvNeXt network is constructed, and in the model, a channel attention module (SE-Block) is fused, so that the emotion recognition efficiency is improved. SE-Block dynamically strengthens key emotion representation through feature re-calibration, ConvNeXt effectively avoids the problem of gradient disappearance or gradient explosion of a deep network, and significantly improves the emotion feature discrimination ability; meanwhile, the scheme innovatively combines a convolution kernel priority algorithm (CKF) to optimize an SE-ConvNeXt network model circuit framework realized based on a memristor array, through cross-kernel weight mapping and dynamic calculation path integration, the problem that an invalid calculation flow is not eliminated after intra-kernel pruning of a traditional convolutional neural network circuit is solved, the convolution calculation energy consumption is reduced, and the calculation efficiency is improved. While high-precision emotion recognition is maintained, the overall operation processing efficiency of the SE-ConvNeXt network model circuit is improved.

The invention discloses a depression detection device, which is applied to the depression diagnosis field, and comprises an MEG signal acquisition module used for acquiring brain MEG signals; the memristor DWT calculation module is used for extracting a signal time-frequency characteristic of the brain MEG signal through the memristor array written with the DWT wavelet coefficient; the memristor CNN classification module is used for performing depression diagnosis on the time-frequency characteristics of the signals through the memristor array in which CNN model parameters are written, and outputting a diagnosis result; the diagnosis output module is used for visually displaying the diagnosis result; and the conductivity detection and calibration module is used for reading the conductivity values of the memristor arrays in the memristor DWT calculation module and the memristor CNN classification module, and calibrating the conductivity values based on a standard conductivity value. A DWT + CNN detection architecture is constructed, low-power-consumption parallel calculation is realized through the memristor, and conductivity deviation of the memristor caused by time drift and temperature fluctuation is avoided through conductivity detection calibration.

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first bottom electrode with a first feature size and a second bottom electrode with a second feature size, and the first feature size is greater than the second feature size; a first resistive switching layer and a second resistive switching layer; a first top electrode with a third feature size and a second top electrode with a fourth feature size, and the third feature size is greater than the fourth feature size; wherein a vertical projection of the first bottom electrode and a vertical projection of the first top electrode at least partially overlap to form a first overlapping area, and the first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping area constitute an erasable memristor; a vertical projection of the second bottom electrode and a vertical projection of the second top electrode at least partially overlap to form a second overlapping area, and the second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping area constitute a non-erasable memristor.

The invention discloses a full-connection Isin machine and an updating method thereof. The full-connection Isin machine comprises a spinning unit array, a global control module, an input driving module and an output driving module, the spinning unit array comprises a plurality of spinning units, any two spinning units interact with each other, a memristor array formed by memristor units is arranged in each spinning unit, and the output driving module is connected with the input driving module. The memristor array receives spin values from other spin units and stores weights equivalent to interaction; the driving module selectively activates and drives the memristor arrays in the plurality of spin units to perform spin updating operation; the output driving module enables all the spinning units to output spinning values; the global control module carries out global control on the input driving module and the output driving module so as to realize parallel control on all the spinning units, and each spinning unit receives spinning values from all the other spinning units and inputs the updated spinning values into all the other spinning units when each spinning update is carried out.

The present application belongs to the technical field of nanoelectronic devices, and provides an integrated gas sensing-computing synaptic device and a preparation method therefor. The device comprises: a first functional layer, a barrier layer, a second functional layer, a first metal electrode, and a second metal electrode; the first functional layer is heavily doped silicon; the second functional layer uses CuOx material, such that defect energy levels are formed by interstitial oxygen and copper vacancies; the barrier layer increases contact area between the second functional layer and a test gas; a direct current voltage scan is applied between the first metal electrode and the second metal electrode, to simulate resistive switching behavior of a memristor; the second functional layer reacts with the test gas, to implement a gas sensing function; a constant voltage signal is applied between the first metal electrode and the second metal electrode, and in a gas pulse environment, a current response state exhibits a synaptic response. The present application can implement in-situ sensing and processing of gas information, improving information processing efficiency, and the gas information inference method of the integrated gas sensing-computing device is simpler.

The application discloses a high-speed link signal equalization method based on a three-dimensional memristor type equalizer, which comprises the following steps: obtaining a distorted signal and generating an ideal received signal, and then constructing a data set; training a recurrent neural network by using the data set to obtain a trained weight parameter; obtaining a conductance value matrix in the three-dimensional memristor type equalizer by mapping the weight parameter; deploying the conductance value to the three-dimensional memristor type equalizer according to the conductance value matrix; and finally inputting the distorted signal into the three-dimensional memristor type equalizer to obtain an optimized signal after compensation distortion. Compared with the traditional feedforward equalizer and decision feedback equalizer method, the application effectively reduces the time domain waveform distortion, improves the high-speed signal integrity, has wide applicability, can be used for the training and deployment application of the memristor type equalizer of various complex high-speed links, and deploys the above-mentioned conductance value to the three-dimensional memristor cross array, so as to improve the integrated density and reduce the area occupied by the equalizer.

The invention discloses a PUF (Physical Unclonable Function) circuit based on a memristor cellular automaton and a use method thereof, and belongs to the technical field of integrated circuit design and information security, the circuit comprises a first cellular initialization module, a second cellular initialization module, 2N cellular node modules, 2N-bit excitation signal input terminals, 2N-bit response signal output terminals, and power supply terminals VCC, VDD, VEE and GND, the 2N cellular node modules are connected end to end to form an annular array, N is an integer which is a positive integer multiple of 4, and each cellular node module comprises a Rule30 logic module and a cellular module, so that the problems of high hardware overhead, poor expandability and insufficient attack resistance of a traditional PUF (Physical Unclonable Function) are effectively solved; the circuit structure is simplified; the hardware resource consumption is reduced; and the flexible expansion of response bits is supported.

This invention relates to the fields of semiconductor information storage and artificial synaptic devices, specifically to a biological synaptic intrinsically self-assembled topological phase-change memristor and its fabrication method. The fabrication method includes: providing a substrate; depositing a bottom electrode; and depositing SrFeO on the bottom electrode. x The thin film serves as the storage medium layer; the storage medium layer undergoes heat treatment, including in-situ annealing and post-annealing. By controlling the oxygen pressure difference between in-situ and post-annealing, the single-component SrFeO is made more efficient. x An intrinsically self-assembled superlattice structure, characterized by alternating vertical and horizontal orientation regions of oxygen vacancy channels, spontaneously forms within the thin film. This structure restricts the formation sites of conductive filaments, significantly improving the consistency and stability of the device's resistive switching cycle. The process of this invention is simple, requiring no introduction of a second-phase material. The resulting memristor requires no electrical formation, exhibits a high on / off ratio, multi-level storage, and short-term synaptic plasticity, making it applicable to neuromorphic computing chips and artificial intelligence devices.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

The invention discloses a multi-stage pulse magnetic control memristor multi-neuron chaotic circuit, and belongs to the technical field of chaotic circuits. Comprising a magnetic control memristor module, a multi-neuron integral-hyperbolic tangent operation module and a multistage pulse input module which are electrically connected to form a nonlinear chaotic circuit. The magnetic control memristive module provides nonlinear memristive characteristics to magnetically control and adjust neuron signals; the multi-neuron integral-hyperbolic tangent operation module comprises at least one channel and is used for completing signal integral and hyperbolic tangent nonlinear transformation, and three independent channels are preferably selected; the multistage pulse input module inputs multistage pulse signals with adjustable amplitude and frequency. Through PSIM simulation and experimental board physical verification, an output voltage phase diagram observed by an oscilloscope is consistent with a simulation phase diagram, and it is proved that the circuit can flexibly generate 1-4 vortex attractors to adapt to scenes of safety communication, artificial intelligence, teaching, scientific research and the like.

This invention relates to the field of memory technology, specifically to a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus. The ferroelectric metal-controlled memristor includes a top electrode layer, a control layer, and a bottom electrode layer, which are sequentially contacted from top to bottom. It combines the unique ferroelectric properties of gallium oxide with the excellent electrical properties of blue phosphorus, a two-dimensional material. The control layer formed by these two materials interacts through van der Waals forces, and the polarization direction of the gallium oxide layer is switched by applying voltages in different directions to the heterojunction, enabling memristor writing and reading. This avoids the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, thus reducing the operating power consumption of the memristor while improving its read / write speed and stability.

The application belongs to the technical field of integrated circuits, and discloses a circuit structure for one-step solution of linear equations based on a memristor array, wherein the linear equations are Ax=b, and in the circuit, a first memristor array matrix operation core realizes mapping of the matrix A, takes a negative value of a first operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current as a first operation current vector after the operation, a bias mapping module maps b into a bias current vector, a current superposition module superimposes the first operation current vector and the bias current vector to generate a superimposed current vector, and converts the superimposed current vector into a second operation voltage vector through a transimpedance amplifier module, a second memristor array matrix operation core realizes mapping of the matrix A, takes the second operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current, and performs an integral operation on the word line current through an integrator module to obtain an updated first operation voltage vector. T The above hardware circuit can realize solution of the linear equations.

The invention discloses a synaptic memory cell for neuromorphic calculation, a preparation method and a synaptic array, the synaptic memory cell comprises two gating transistors and two resistance change memristors, and the gating transistors and the resistance change memristors are in one-to-one correspondence connection; the gate transistor comprises a grid electrode, a dielectric layer and a channel layer which are sequentially arranged from bottom to top, and a source electrode and a drain electrode which are arranged on the surface of the channel layer, and a first passivation layer is arranged between the source electrode and the drain electrode; the channel layer is made of hydrogenated amorphous silicon; the resistance change memristor comprises a bottom electrode, a resistance change layer and a top electrode which are sequentially arranged on the drain electrode, and a second passivation layer which is arranged on the surface of the drain electrode and the surface of the first passivation layer; the resistive layer is a hexagonal boron nitride film; and the two resistive memristors are connected with each other through a metal layer arranged on the surface of the top electrode. According to the invention, low-temperature process compatibility is realized, so that three-dimensional stacking integration is facilitated, and the conductivity fluctuation coefficient is remarkably reduced.

The application belongs to the technical field of microelectronic devices, and particularly relates to a nonvolatile FeOOH / TiO2 heterojunction memristor and a preparation and multi-value storage control method thereof. The nonvolatile FeOOH / TiO2 heterojunction memristor comprises a bottom electrode, a TiO2 resistive switching layer and a FeOOH resistive switching layer which are epitaxially grown on the bottom electrode in sequence, and an upper electrode deposited on the surface of the FeOOH resistive switching layer. The preparation method comprises the following steps: placing a bottom electrode substrate with a conductive surface downward in a water heating reaction kettle inner container, adding a reaction solution prepared by tetrabutyl titanate, keeping part of the bottom electrode substrate higher than the reaction solution surface, sealing, and placing in a muffle furnace for water heating reaction; obtaining a TiO2 / bottom electrode sample; placing an epitaxial growth surface downward in the water heating reaction kettle inner container, adding a reaction solution of FeCl3.6H2O, sealing, and placing in a muffle furnace for water heating reaction to obtain a required FeOOH / TiO2 / bottom electrode heterojunction sample; and depositing an upper electrode with a certain thickness and morphology on the surface. The application provides a low-cost and high-density nonvolatile FeOOH / TiO2 heterojunction memristor.

This invention provides a terminal-side load balancing system, method, and apparatus based on energy storage devices. The system includes: a signal conversion module for converting digital traffic signals representing network traffic received from a base station by a communication module into analog traffic signals; a memristor detection circuit connected between the signal conversion module and ground for detecting current changes corresponding to the analog traffic signals to generate feedback signals reflecting network traffic volume; and a main control chip for calculating real-time network bandwidth based on the feedback signals and comparing the real-time network bandwidth with a preset threshold. When the main control chip detects that the real-time network bandwidth is lower than the preset threshold, it generates a load balancing feedback command and reports it to the operator's network side via the communication module to trigger network-side load balancing operations. This achieves high-precision network traffic detection at the terminal side and can proactively trigger network-side load balancing based on the detection results.

The invention discloses a channel estimation circuit and a channel estimation method based on memristors, and relates to the field of wireless communication and integrated circuits, and the circuit comprises three memristor arrays which are respectively used for mapping a first real number matrix, a second real number matrix and a diagonal matrix, the first real number matrix is composed of absolute values of non-positive elements of a channel estimation pilot frequency sequence cross-correlation mapping matrix, and the second real number matrix is composed of non-diagonal elements in non-negative elements of the channel estimation pilot frequency sequence cross-correlation mapping matrix; the diagonal matrix is composed of diagonal elements in non-negative elements of a channel estimation pilot frequency sequence cross-correlation mapping matrix; the switch module controls the memristor to be connected to or disconnected from the circuit; the inverter array is connected between the first memristor array and the second memristor array and is used for realizing matrix subtraction and positive and negative value compensation; the operational amplifier array is connected with the row lines and the column lines of the memristor array to form a feedback loop, channel estimation values are output, the integration level is high, the calculation speed is high, and energy consumption is low.

The invention relates to the technical field of micro-nano electronic devices, in particular to a nanofluid memristor prepared by puncturing a PDMS film and a mechanical-electric coupling regulation and control system and method of the nanofluid memristor. The memristor is composed of a silicon substrate with a window and a PDMS thin film covering the silicon substrate, a three-degree-of-freedom probe station is used for driving a tungsten probe to conduct nanoscale puncture on the PDMS thin film under an optical microscope, and a pore channel with the self-constriction / reversible closing characteristic is formed; after the needle is removed, the hole channel is in a near-closed or sub-nanometer equivalent hole diameter state, by applying controllable pressure to the closed liquid chamber and superposing bias voltage, sudden change / gradual change dual-mode regulation and control of the hole diameter and non-volatile hysteresis conductance switching are achieved, and the switch ratio of the device can reach 108. According to the method, FIB is not needed in hole forming, the process is simple and convenient, the cost is low, high-contrast and programmable nanofluid memristive behaviors are achieved through the structural design of the window orientation and the clamping direction, pressure rate programming and a pressure removal maintaining / negative pressure reset strategy, and the method is suitable for the fields of single molecule detection, ion circuit storage and the like.

The application discloses a water-soluble polymer-based proton-type memristor and a preparation method thereof. The memristor has a sandwich structure and is sequentially composed of a top electrode, an inorganic resistive switching functional layer, an organic resistive switching functional layer and a bottom electrode. The top electrode is a metal active electrode, the bottom electrode is indium tin oxide (ITO), the inorganic resistive switching functional layer is a metal oxide film, and the organic resistive switching functional layer is a doping system composed of a water-soluble polymer and a doping material. The preparation process of the proton-type memristor is reliable and stable. The obtained memristor has the characteristics of high biocompatibility and green environmental protection. The device performance consistency and environmental dependence are improved, and the simulation of bionic synaptic plasticity is greatly improved. The device can be controlled by using a low voltage, has low power consumption, and has a good bidirectional current modulation effect, so that the device provides a possibility for further enriching synaptic functions and designing flexible wearable devices.

Neural network systems and methods are provided. In one embodiment, a method of making a neural network device includes: forming a mesh layer on a substrate, the mesh layer including a matrix of randomly dispersed conductive nano-strands insulated from one another; forming an isolation trench extending into the mesh layer; forming a memristor device extending into the mesh layer, the memristor device including: an electrical conductor, and a layer of memristive material in electrical contact with individual nano-strands of a first set of conductive nano-strands in the mesh layer; forming an electrode extending into the mesh layer and spaced from the memristor device by the isolation trench, wherein the electrode is in electrical contact with individual conductive nano-strands of a second set of conductive nano-strands in the mesh layer; and forming a modulating device bridging the memristor device and the electrode.