782 results about "Memristor" patented technology

The invention discloses a machine vision-based resistor disc defect online detection system and a grading method, relates to the technical field of industrial machine vision detection, and solves the defect problems in the aspects of multi-scale defect dynamic perception, cross-level feature interaction and process adaptive optimization in the prior art. According to the scheme, metal reflection interference is inhibited through Retinex illumination correction and a combined denoising model; adopting a deformable convolution kernel and cavity space pyramid pooling to realize gradient entropy driving dynamic sensing of the multi-scale defect; constructing a bidirectional cross-layer attention network to realize early fusion of high-resolution details and high-level semantics; modeling local-global feature physical association based on a graph attention network and a self-supervised message passing mechanism; integrating reinforcement learning and a memristor random calculation unit to form a closed-loop parameter optimization system; according to the method, the multi-scale defect detection precision, the cross-modal feature fusion efficiency and the system adaptive capacity under complex working conditions are remarkably improved.

The invention discloses a fault diagnosis and remote monitoring system and method for a solar power supply system, and relates to the technical field of fault diagnosis of a solar system, and the system comprises a heterogeneous multi-mode sensing module which collects the multi-dimensional information of an assembly through a plurality of sensors; the memristor storage and calculation integrated unit is used for realizing data filtering and feature extraction; the multi-scale causal diagnosis engine is used for diagnosing faults by fusing deep learning and causal diagrams; a self-adaptive topology communication network ensures data transmission; a digital twinborn monitoring platform and visual operation and maintenance are adopted, and in addition, an intelligent evolution decision and self-reconfiguration sensor network module is further arranged, so that the intelligence and reliability of the system are improved. Through cooperation of multiple modules, accurate fault diagnosis and positioning are realized, the diagnosis time is shortened, stable data transmission is ensured, self-repairing and autonomous learning capabilities are provided, the operation and maintenance cost can be reduced, the power generation efficiency can be improved, and the reliability and economic benefits of a solar power supply system can be enhanced.

A hardware emulator and an emulation system including the hardware emulator are provided. The hardware emulator includes an artificial neural network-based reconstruction model configured to reconstruct dynamics of a dynamical system based on input data and a memristor-based circuit configured to emulate state space representation of the dynamical system based on the reconstruction model.

The invention discloses a motion recognition method and system based on a redox photoelectric memristor, a terminal and a storage medium, and the method comprises the steps: selecting classical motions based on a human body motion data set, extracting time sequence data, and coding the time sequence data into an optical pulse sequence; constructing a reservoir array composed of a plurality of photoelectric memristors, and expanding an optical pulse sequence signal into a high-dimensional state vector; constructing a supervised training model, solving a weight matrix, and constructing a memristive cross array; and outputting an action classification result through simulation domain operation based on the output current multi-path light current signals in combination with the memristor cross array. According to the method, the motion features can be directly fed into a rear-end classification network for action recognition without depending on a complex digital feature extraction algorithm, so that the transmission and processing overhead of redundant data is fundamentally eliminated; a high-efficiency, low-delay and high-robustness hardware solution is provided for real-time and anti-noise motion recognition in scenes such as intelligent monitoring and man-machine interaction.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses a direct current charging pile detection system and method applied to the field, and relates to the technical field of power equipment on-line monitoring, and the method comprises the steps: inputting a three-dimensional data set into a Toeplitz cyclic measurement matrix for compressed sampling, reconstructing the three-dimensional data set into a high-resolution signal through employing an improved orthogonal matching pursuit algorithm, and carrying out the detection of the high-resolution signal; analyzing and calculating a local variable coefficient through a sliding window, marking abnormal positions, and integrating the abnormal positions into an abnormal position set; inputting the abnormal position set into a pre-trained long and short term memory prediction model, evaluating the insulation residual life and the fault risk level, and calculating the maximum allowable output current of the DC charging pile in real time; the load impedance is dynamically adjusted and detected through the memristor array, the output current of the direct current charging pile is collected in real time, and synchronous compression wavelet transform is adopted to analyze a harmonic ridge line and extract a harmonic component; the accuracy of fault early warning is remarkably improved, rapid dynamic adjustment of the output current is achieved, and the technical problem of multi-physics field coupling monitoring of the rapid charging pile is effectively solved.

The invention belongs to the technical field of brain-like calculation and storage calculation integrated chips, and particularly discloses a memristor differential double sub-array structure, a convolution acceleration system and application, the memristor differential double sub-array structure comprises two parallel sub-arrays which are not directly and electrically connected, the two sub-arrays comprise the same number of memristors, and the memristors are arranged in the parallel sub-arrays. The memristors in the two sub-arrays are paired to form a differential unit, and each differential unit stores a weight parameter in the convolution kernel in a differential form and participates in convolution operation; and the memristors in the same sub-array are connected in parallel. And by combining the differential double-subarray structure and the transimpedance amplification reading circuit, the fluctuation and noise of the device can be effectively suppressed, and the precision and stability of convolution calculation are improved. According to the method, efficient convolution operation and feature extraction can be realized on the edge side, the method has the advantages of low power consumption, multi-resistance-state controllability, high integration and the like, the method is suitable for various edge intelligent scenes such as image recognition, mode detection, video monitoring, inspection analysis and the like, and the intelligent processing capacity of the terminal side is improved.

The invention discloses a memristor based on a covalent organic framework and a preparation method and application thereof.The memristor comprises a substrate, a semiconductor electrode, a covalent organic framework film and a metal electrode which are sequentially arranged in a stacked mode, and the covalent organic framework film is composed of 1, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 16, 17, 17, 17, 17, 17, 17, 17, 17, the catalyst is prepared by condensing 1, 3, 5-tri (4-aminophenyl) benzene and terephthalaldehyde or terephthalaldehyde with an alkyl or alkoxy side chain. The covalent organic framework film has a highly ordered structure and an adjustable porous structure, the preparation process is simple, the film thickness is uniform, the flatness and the crystallinity are high, and the dielectric property is adjusted, so that the switching voltage and the cycling stability of the memristor are adjusted, and the memristor has stable and repeatable switching performance; the COFs-based memristor has high on / off ratio, low device variability and high flexibility, can be used for preparing the COFs-based memristor, can provide technical support for neuromorphic devices with high efficiency, adjustability, structure adjustability and rich functions, and can be applied to the field of intelligent sensing and autonomous system control such as an auxiliary driving system.

The invention discloses an environment-emotion gradient association memristive neural network circuit based on a TAP cell regulation mechanism. The environment-emotion gradient association memristive neural network circuit is composed of a hippocampus module and an amygdala kernel module. The hippocampus module comprises an environment recognition neuron module and an emotion generation neuron module; the environment recognition neuron module and the emotion generation neuron module are each composed of a weight regulation and control module adj based on a TAP cell regulation mechanism, an adder, a memristor, a resistor, an operational amplifier, a function module ABM1 and a sampling holder. Wherein the weight regulation and control module adj is composed of a voltage-controlled switch, a summator, a function module ABM2 and a function module ABM3. The almond kernel module is composed of a weight regulation and control module adj, a memristor, a resistor, an operational amplifier and a sampling holder. The provided circuit simulates the hippocampus and amygdala nucleus of the brain in structure, the regulation principle of TAP cells on neural stem cells is used for reference in a weight regulation mechanism, and bidirectional gradient associated memory of the environment and the emotion can be achieved.

The invention discloses a real-time reserve pool calculation method and system based on pulse amplitude information coding, and belongs to the technical field of reserve pool calculation of space-time sequence tasks. The method comprises the steps that modal information in a real environment is received and preprocessed, encoding is carried out according to time steps, and the codes are pulse sequences with different pulse amplitudes; feeding the pulse sequence into an SL end of a volatile memristor array, writing the pulse sequence into the volatile memristor array, and receiving nonlinear response current of dynamic volatile memristor array space projection at a BL end in real time; receiving the response current by the FPGA, sampling at equal intervals to construct a virtual node, converting the response current into a voltage signal through a TIA, and feeding the voltage signal into a pre-trained nonvolatile memristor array for reasoning; and receiving the response current, outputting a maximum value corresponding neuron index through the WTA winner eating circuit, representing a classification or prediction result, and transmitting the result back to an upper computer or performing action decision at a local end.

The invention relates to the technical field of AI audio chips, and discloses an audio processing model quantification method and system, and the method comprises the steps: applying an incremental voltage pulse to a multi-layer memristor cross array, measuring a conductivity value, and generating a memristor quantification configuration table; programming the neuron units in the multi-layer memristor cross array to obtain quantized neuron units; calculating a synaptic weight matrix; the audio signal to be processed is input into the quantization neuron unit to execute pulse calculation, the audio features are obtained, and the audio recognition result is generated on the end-side processor, so that the problems of nonlinearity and element difference of the memristor are effectively solved, the robustness of the system is improved, and the optimal balance of precision and power consumption can be realized in different scenes.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

The invention belongs to the technical field of external diagnosis devices, and particularly relates to a memristor for adenovirus concentration detection and a preparation method of the memristor. The memristor comprises a bottom electrode layer, a metal oxide layer, a functional layer and an upper electrode layer which are sequentially formed from bottom to top in the thickness direction, the bottom electrode layer is an FTO conductive glass layer, the metal oxide layer is tantalum pentoxide, the functional layer is a gelatin-beta cyclodextrin composite film, and the upper electrode layer is a conductive electrode layer. The gelatin-beta cyclodextrin composite film with the memristive effect serves as a functional layer, after the film makes contact with adenoviruses, the film adsorbs virus particles, then the unique resistance change characteristic of the memristor is caused, the memristive behavior of the memristor is further fed back, and the memristive effect of the memristor is improved. The method is used for recording and analyzing the electrochemical or bio-electricity signal characteristics of adenovirus solutions with different concentrations, the adenovirus solutions with different concentrations are effectively distinguished according to the electric signal difference of the adenovirus solution and the control solution, the effect is obvious, and the repeatability is good.

The invention relates to a matrix decomposition device and method based on a memristor cross array, which are suitable for efficient hardware implementation of singular value decomposition (SVD), the memristor cross array receives a conductance value mapped by a Grubrum matrix constructed by a to-be-decomposed matrix and a bit line input voltage converted by a bit line column vector, and outputs a corresponding current; converting the corresponding current into a voltage vector; performing normalization processing on the voltage vector to obtain a normalized vector; judging whether convergence occurs or not; performing normalization processing on the steady-state voltage vector to obtain a final output vector; and according to the final output vector, main characteristic values are extracted based on a first normalization circuit, and main singular values and corresponding singular matrixes are calculated. Compared with the prior art, the high parallel computing characteristic of the memristor cross array is utilized, efficient operation and hardware acceleration of matrix decomposition are achieved, the method has the advantages of being low in power consumption, high in speed and good in expansibility, and the method is suitable for application scenes such as artificial intelligence, signal processing and large-scale matrix operation.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

The invention relates to a memristor and a preparation method thereof. The preparation method comprises the following steps: providing an insulating substrate with a bottom electrode formed on the surface; depositing an aluminum oxide thin film on the bottom electrode by adopting electron beam evaporation under a room temperature condition to form a resistive function layer, and not performing high-temperature annealing treatment after deposition is completed, so that a primary oxygen vacancy defect is reserved in the thin film; and then depositing a top electrode on the resistive function layer through thermal evaporation or electron beam evaporation to obtain the memristor. The resistive function layer is an aluminum oxide film which is not densified through annealing, and internal defects of the resistive function layer provide a channel for metal ion migration, so that the reversible resistive characteristic is achieved. The memristor device is simple in structure and suitable for normal-temperature process preparation, the stable resistance switching behavior can be achieved, excessive densification of a film layer and thermal damage of an ITO electrode interface caused by high-temperature annealing are avoided, and the memristor has high cycle durability and nonvolatile data retention capacity and has the stable bipolar resistance change characteristic.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

In certain examples, a method may include receiving a privacy parameter and selecting an electrical property range for cells in a crossbar array based on the privacy parameter. The cells in the crossbar array may then be programmed based on the selected electrical property range, which may provide a certain level of differential privacy.

The invention discloses a full-light-operated memristor based on an oxide / quantum dot composite structure and a method, and belongs to the technical field of optoelectronic devices. The invention discloses a structure of a full-light-operated memristor. The structure sequentially comprises a substrate, a lower electrode layer, an oxide / quantum dot composite structure layer and an upper electrode layer from bottom to top, the oxide / quantum dot composite structure layer is composed of an oxide layer and a quantum dot layer. According to the full-light-operated memristor disclosed by the invention, the oxide is combined with the high-light-sensitivity quantum dots to form II-type, Z-type and S-type heterojunctions, and photo-induced electrons in the heterojunctions can realize directional transfer from the quantum dots to the oxide under illumination, so that the effective working window of the device is improved. Compared with an existing full-light-control memristor, the composite structure shows a larger working window, the full-light-control performance of the device is remarkably improved, and practical application of the full-light-control memristor in the fields of neuromorphic calculation and artificial vision is facilitated.

The invention relates to the technical field of quantum reinforcement learning, in particular to a reinforcement learning method and system for quantum gate regulation, and the method sequentially comprises the steps: carrying out the normalization of an offline sample, carrying out the principal component analysis, and then preparing a prior quantum state; performing wavelet scattering and persistent coherence on the quantum pulses to extract topological features, and mapping the topological features into a non-Abell geometric gate rotation angle to generate an action probability; constructing a sparse high-dimensional vector, selecting a target super vector through Grover amplification, writing the target super vector into the silicon carbide memristor array, and retrieving an action vector according to a conduction function determined by the topological feature vector; the motion vector drives the Heisenberg cellular automaton to predict the environment, the local error triggers the fine tuning of the rotation angle and the conduction value, and the global distance triggers the topology recompilation and the quantum natural gradient. According to the method, decision making within 250 microseconds, low-energy-consumption retrieval and steady-state self-healing are achieved.

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.

The invention relates to the technical field of microelectronic devices, in particular to a single-molecule memristor-rectifier device based on supramolecular assembly and a preparation method thereof. According to the preparation method, the guest molecule B is covalently connected with the tail end of the graphene electrode pair, so that stable and tight interface bonding between the supramolecular functional molecule and the electrode can be ensured; and then soaking the graphene electrode pair connected with the guest molecule B in a solution containing the host molecule A and the guest molecule C to form a supramolecular functional molecule between the graphene electrode pair. The guest molecule C in the supramolecular functional molecule has intrinsic oxidation-reduction activity, and the molecular structure of the guest molecule C can generate a reversible electron gain and loss process, so that controllable and reversible adjustment of charge distribution in the molecule is realized. Under the action of an electric field, through the reversible oxidation-reduction reaction of the guest molecule C, significant changes of intramolecular charge distribution and electron transmission characteristics are triggered, and finally reliable switching of high and low resistance states of the device is achieved.

The invention discloses a synaptic plastic mechanism bionic circuit based on a threshold symmetric memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a pre-synaptic neuron circuit, the threshold symmetric memristor and a post-synaptic neuron circuit; the bionic circuit is divided into an excitatory synaptic moldability mechanism circuit and an inhibitory synaptic moldability mechanism circuit according to a synaptic moldability mechanism; the design method of the circuit comprises the following steps: firstly, designing neuron waveforms before and after synapse, then traversing changes of memristive synapse conductance values at different time intervals to obtain a corresponding curve of the conductance changes and the time intervals, verifying the fitting degree of a biological synapse plastic mechanism curve and the curve, and if the fitting degree is low, determining that the biological synapse plastic mechanism curve is not matched with the curve. And if not, redesigning the pulse waveforms before and after synapse. The synaptic plasticity mechanism simulated by the bionic circuit provided by the invention and a biological synaptic STDP mechanism model have a small fitting error, the provided design method is higher in universality, circuit parameters can be adjusted according to different memristors, and different forms of biological synaptic plasticity mechanisms can be simulated.

The invention discloses a hybrid clustering optimization method and system for memristor array weight mapping, belongs to the technical field of storage and calculation integrated chips, and solves the problem that the reasoning precision is reduced due to the fact that edge weights are forcibly classified into unmatched clustering centers due to the fact that an existing clustering method is poor in adaptability to weight distribution characteristics. According to the method, the posterior probability is obtained based on the weight of the target neural network and the discrete level number of the conductance state of the initialized target memristor array; performing hierarchical clustering based on a result obtained in the step 1 to obtain a corresponding clustering center; performing resistance drift pre-compensation based on all the clustering centers to obtain a corrected clustering center; and carrying out weight-conductance mapping deployment based on the corrected clustering center. The memristor array weight mapping method is used for memristor array weight mapping.

The embodiment of the invention provides a semiconductor device and a forming method thereof. The semiconductor device comprises a first semiconductor structure, a first bonding layer and a second semiconductor structure which are sequentially stacked along a first direction, wherein the first semiconductor structure comprises a transistor structure; the second semiconductor structure comprises a memristor structure; the first bonding layer comprises a first bonding structure and a second bonding structure which are arranged along a second direction; the memristor structure is connected with the transistor structure through the first bonding structure and the second bonding structure; the second direction is perpendicular to the first direction.

The invention discloses an organic semiconductor heterojunction photoelectric self-adaptive memristor and a preparation method thereof, and belongs to the field of neuromorphic devices, and the memristor sequentially comprises a substrate, a bottom electrode, a lower active layer, an upper active layer and a top electrode from bottom to top; the upper active layer is prepared from an organic material zinc phthalocyanine, and the lower active layer is prepared from an organic material N, N-tricosylperylene-3, 4, 9, 10-tetracarboxylic diimide. The memristor prepared by the invention realizes simulation of desensitization behavior and retina light adaptation function, and adaptivity modes are switched according to a stimulation type time-sharing trigger mechanism to support multi-mode perception and adaptive information processing in a dynamic environment, so that the development of a neuromorphic device for simulating the adaptivity function of a biological sensory system is promoted.

The invention provides a multi-resistance-state ferroelectric memristor and a preparation method thereof.The multi-resistance-state ferroelectric memristor comprises a bottom electrode, a ferroelectric layer and a top electrode which are sequentially arranged in a stacked mode from bottom to top, the ferroelectric layer comprises at least two layers of aluminum scandium nitride thin films, and in the different layers of aluminum scandium nitride thin films, the number of the aluminum scandium nitride thin films is larger than the number of the aluminum scandium nitride thin films. The ratio of scandium atoms to aluminum atoms is gradually increased along with the number of layers from bottom to top. In each layer of aluminum scandium nitride film, the number of scandium atoms is gradually increased from bottom to top to form gradient distribution, so that the resistance of each aluminum scandium nitride film can be influenced, a plurality of stable resistance states are generated, a multi-resistance-state effect is realized, the storage state of the memristor is greatly enriched, and possibility is provided for high-density data storage.

An analog neuromorphic circuit is disclosed having a first and a second memristor crossbar configuration implemented into an autoencoder. The first memristor crossbar configuration includes resistive memories that provide resistance values to each corresponding input voltage applied to the first memristor crossbar configuration to generate first output voltages that are compressed from the input voltages. The second memristor crossbar includes resistive memories that provide resistance values to each corresponding first output voltage applied to the second memristor crossbar configuration to generate second output voltages that are decompressed from the first output voltages. A controller compares the second output voltages to the input voltages to determine if the second output voltages are within a threshold of the input voltages. The controller generates an alert when the second output voltages exceed the threshold from the input voltages thereby indicating that input data associated with the input voltages has not been previously identified.

Memristor storage unit comprising a plurality of memristor storage devices (100; 302), each of which comprises: a memristive memory cell (102, 202); an input port (104) and an output port (108) that are directly attached to the memristive memory cell (102, 202); and an electrically isolated gate terminal (112) from the memristive memory cell (102, 202) for volatile gate-induced modulation of a conductivity of the memristive memory cell (102, 202) by receiving electrical signals; the memristor storage unit further comprises: a temperature effect control unit (402) suitable for generating a portion of the received electrical signals based on a temperature-based resistance drift effect of each of the memristor storage devices (100, 302); and / or a resistance drift correction unit (404) which is suitable for generating a different part of the received electrical signals based on a time-dependent resistance drift effect of each of the memristor storage devices (100, 302).

The invention discloses a photoelectric detection convolution calculation system based on a programmable resistor array, and the system consists of a photoelectric detection array, the programmable resistor array, a gating module, a sampling amplification module, a signal filtering module, an analog-to-digital conversion module, and a main control unit, and all parts work cooperatively with signals through reasonable electrical connection. And detection, weighting, summation and digital output of optical signals are realized. According to the system, the complexity of a dual-device differential structure in the memristor array is avoided structurally, a peripheral driving and calibration circuit is simplified, meanwhile, the high stability and rapid reconfigurable characteristics of the programmable resistor array are utilized, the target of directly completing convolution operation at the photoelectric detection front end is achieved, and the system is suitable for large-scale popularization and application. And the response speed, the calculation precision and the engineering realizability of the system are effectively improved.