137 results about "Synaptic weight" patented technology

The invention relates to the technical field of artificial intelligence, can be applied to service scenes of pension service, financial science and technology, medical health and the like, and discloses a multi-level heterogeneous integrated chip task processing method, device, equipment and medium, and the method comprises the steps: constructing a multi-level heterogeneous integrated chip composed of a perception processing layer, an intelligent decision-making layer and a driving control layer, the layers are connected through a vertical interconnection structure; receiving multi-modal task data and extracting features to generate feature vectors; inputting the feature vector into a neuromorphic processing unit to determine a task decision result; converting the decision result into a driving signal to control an execution device; adjusting synaptic weights based on the feedback signal; and monitoring chip operation state parameters and dynamically adjusting processing frequency and structure parameters. By integrating multi-modal sensing, neuromorphic decision and a dynamic feedback mechanism, data sensing, decision and execution processing are completed in a chip, and the real-time performance and the calculation efficiency are improved by combining operation state monitoring and adjusting frequency and structure.

The invention is applied to the field of mechanical fault diagnosis signal processing, and particularly provides a pulse neural network mechanical fault diagnosis method based on STFT dimension transformation, and the method comprises the steps: collecting a one-dimensional mechanical vibration signal, carrying out the wavelet decomposition, carrying out the wavelet reconstruction of a low-frequency component and a denoised high-frequency component, and carrying out the wavelet reconstruction of the low-frequency component and the denoised high-frequency component; obtaining a denoised one-dimensional vibration signal; performing short-time Fourier transform, and converting the time-frequency two-dimensional matrix into a time-frequency two-dimensional matrix; inputting the time-frequency two-dimensional matrix into an improved HH threshold neuron model, carrying out Poisson sparse coding on the time-frequency two-dimensional matrix, and only carrying out pulse response on signal significant features; constructing a suprathreshold coding convolutional network with residual connection, inputting a sparse coding matrix, training by adopting an unsupervised learning rule based on STDP, and adaptively adjusting a network synaptic weight; and inputting to a trained above-threshold coding convolutional network, and obtaining pulse emission activity of neurons of an output layer through network forward propagation to determine a fault diagnosis result.

A bidirectional autoencoder learns or approximates an identity mapping as it trains a single network with a version of the new bidirectional backpropagation algorithm. Ordinary unidirectional autoencoders find many uses in image processing and in large language models. But they use separate networks for encoding and decoding. Bidirectional autoencoders use the same synaptic weights for encoding and decoding. The forward pass encodes while the backward pass decodes. Bidirectional autoencoders improved network performance and significantly reduced memory usage and used fewer parameters. Simulations compared unidirectional with bidirectional autoencoders for image compression and denoising. The models trained on the MNIST handwritten-digit and CIFAR-10 image datasets. The performance measures were the peak signal-to-noise ratio and the index of structural similarity. Bidirectional autoencoders outperformed unidirectional autoencoders and still reduced the number of trainable synaptic parameters by about 50%.

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

The invention discloses an image classification method and device, equipment, a medium and a product, and relates to the field of image classification, and the method comprises the steps: obtaining to-be-classified image data; according to the to-be-classified image data, performing classification by using a classification model to obtain a classification category; the classification model is a trained pulse neural network; the spiking neural network comprises a plurality of neural layers; each neural layer comprises a plurality of neurons; each neuron comprises an emission threshold value and an input resistance; the training process of the classification model specifically comprises the following steps: taking sample image data as the input of a spiking neural network, taking a sample classification category as the output of the spiking neural network, and determining a total loss function of the spiking neural network according to cross entropy loss and adaptive sparse loss; and optimizing the synaptic weight, the emission threshold and the input resistance of the spiking neural network by using a back propagation algorithm to obtain a classification model. The method can improve the classification precision.

The invention belongs to the field of hardware neural network design, and particularly discloses a CMOS-based attractor recurrent neural network system and an implementation method thereof.A neuron calculation module receives an external input high-level signal and generates an initial synaptic high-level signal; integration and activation calculation are carried out based on the current output by the synaptic calculation module, and whether a synaptic high-level signal is generated or not is determined according to an activation state; the synaptic storage module writes the non-zero weight into a synaptic weight SRAM (Static Random Access Memory) array; the synaptic calculation module performs product operation on the synaptic high-level signal and the synaptic weight in the synaptic weight SRAM array, and outputs current; when the STDP updating module is in a neuron training mode, the STDP updating module updates the synaptic weight SRAM array according to the synaptic high-level signal; and the group state module outputs a neuron sequence number corresponding to the maximum activation frequency. A cyclic connection structure of the attractor neural network is formed, and the real-time cognitive behavior requirement of the brain is met.

The invention provides a brain-like chip heterogeneous calculation and dynamic model updating method, which comprises the following steps: constructing a neuron pulse coding and video feature parallel calculation model, carrying out heterogeneous integration on a brain-like chip supporting an SNN pulse neural network and a multi-core processor, and constructing a spatial-temporal feature dual-channel processing unit; developing a task load balancing algorithm based on synaptic weight dynamic allocation, including constructing a resource state matrix, designing a task allocator based on reinforcement learning, and performing decision optimization in a dynamic environment; a direct memory access channel is established between a brain-like chip and a video codec, a dedicated instruction set is expanded, and motion vector data of a video encoder is read through instruction level collaboration; carrying out binary differential coding on the key layer by adopting hierarchical parameter importance sorting, and compressing the update quantity of the key layer by combining a compression algorithm; and migrating a full-amount model to a lightweight model through dynamic knowledge distillation, and dynamically generating an adaptive model in combination with an attention migration loss function.

The invention discloses a big data analysis system and method for a financial guarantee circle, and relates to the technical field of data analysis, and the method comprises the steps: collecting industrial and commercial, judicial and financial data in real time through an API gateway, and constructing a quantization guarantee network model and a quantum annealing parameter configuration file after preprocessing; a quantum annealing machine is used for executing hidden relation detection, and Bayesian confidence coefficient calibration is combined to generate a high-association guarantee ring list and a quantum calculation log; simulating a risk conduction path based on a synaptic plasticity model of the spiking neural network, and outputting a synaptic weight change table and a dynamic conduction diagram; the risk levels are mapped into a hierarchical blocking strategy matrix through a dynamic blocking decision engine, topology reinforcement is carried out by combining historical data and adopting a minimum spanning tree algorithm, and a stable subnet list and a protection path diagram are generated; and finally, performing weighted fusion on the quantum log, the conduction model and the subnet data, constructing a three-dimensional risk map, and optimizing a real-time decision by using a long and short-term memory network and an attention mechanism network.

The invention relates to the technical field of AI audio chips, and discloses an audio processing model quantification method and system, and the method comprises the steps: applying an incremental voltage pulse to a multi-layer memristor cross array, measuring a conductivity value, and generating a memristor quantification configuration table; programming the neuron units in the multi-layer memristor cross array to obtain quantized neuron units; calculating a synaptic weight matrix; the audio signal to be processed is input into the quantization neuron unit to execute pulse calculation, the audio features are obtained, and the audio recognition result is generated on the end-side processor, so that the problems of nonlinearity and element difference of the memristor are effectively solved, the robustness of the system is improved, and the optimal balance of precision and power consumption can be realized in different scenes.

The invention relates to a battery life and safety collaborative prediction method and system based on an improved pulse neural network algorithm, and belongs to the technical field of electric tool battery management. The method is based on a four-level SNN architecture, an input layer receives voltage, current, temperature, stress and change rate parameters of a battery, and neural pulse conversion of the parameters is realized through rate coding and time coding; the synaptic layer simulates a physical hysteresis effect between parameters by using a double-index model, and the hidden layer passes through Adaptive Iamp; the F neurons integrate historical memory and nonlinear coupling, and the output layer generates health status, residual life and risk index. The synaptic weight is optimized through a supervised STDP learning rule, the contribution degree of each parameter is quantified, a membrane potential linear accumulation mechanism of the life dimension and an abnormal pulse triggering mechanism of the safety dimension are established, and a joint early warning decision is realized. The system is deployed in a battery management system, the battery state can be monitored in real time, and accurate decision support is provided for battery full life cycle management.

The present invention discloses a servo motor energy-saving control system and method, which relates to the technical field of servo motor energy saving. It includes: based on the magnetic field intensity matrix and the temperature distribution matrix, obtaining the magnetothermal coupling coefficient, identifying the temperature anomaly area, and generating a hot spot marker; based on the magnetothermal coupling coefficient and the hot spot marker, encoding the magnetothermal coupling coefficient into a pulse sequence through a pulsed neural network, and using the synaptic weight update mechanism of the hidden layer neurons to generate an energy recovery threshold and an efficiency threshold; based on the energy recovery threshold and the efficiency threshold, performing dynamic energy recovery on the servo motor, collecting the vibration signal after energy recovery, calculating the maximum Lyapunov exponent, and updating the pulsed neural network. The present invention realizes the precise correlation mapping between magnetic field distortion and local temperature rise through the calculation of the magnetothermal coupling coefficient and the hot spot marker, breaks through the limitations of traditional independent analysis, and provides a physical basis for energy recovery.

The invention discloses a multi-frequency weak fault enhancement method based on fractional order resonance response atlas reconstruction, and the method comprises the steps: carrying out the noise reduction, trend term removal, phase compensation and modal decomposition of a mechanical vibration signal, determining a lag phase through a frequency sweep method for phase compensation, adjusting the phase of a same-frequency signal, reconstructing an effective component through the combination of a modal decomposition borrowing geometric method and a Pearson matrix, and carrying out the phase compensation. Constructing a nonlinear resonance model with historical memory; inputting the parameters into the same-direction coupling neuron model, dynamically updating and simulating transmission intensity change through synaptic weight, and solving response and step length; constructing a zero-energy coupling index based on a signal zero-crossing behavior, energy distribution and time-frequency analysis, wherein the time-frequency analysis comprises short-time Fourier transform and wavelet packet energy spectrum calculation to extract energy features; and iteratively optimizing parameters by using a quantum optimization algorithm, adjusting a rotation angle and preserving population diversity to prevent premature convergence, and outputting optimal parameters by taking a zero-energy coupling index as a target.

The present invention provides systems and methods for utilizing an application-specific integrated circuit (ASIC) for an artificial neural network connected to the memory, the ASIC comprising: a plurality of neurons organized in an array, wherein each neuron comprises a register, a processing element and at least one input, and a plurality of synaptic circuits, each synaptic circuit including a memory for storing a synaptic weight, wherein each neuron is connected to at least one other neuron via one of the plurality of synaptic circuits, wherein the array is configured to analyze said business sale transaction information trained on historical datasets relating to asset utilization, wherein the AI / ML categorization engine makes a prediction regarding the most efficient use(s) of an asset.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit out of the neuron circuits includes an input circuit, a charge holding circuit, a comparison circuit, a firing circuit, a charge control circuit, and a control signal output circuit. When a determination signal changes from a second value to a first value, the firing circuit outputs a spike signal. The control signal output circuit outputs a control signal indicating a comparison voltage that is based on an excess component of a membrane potential exceeding a threshold potential. In response to acquiring the spike signal from the first neuron circuit, a first synapse circuit out of the synapse circuits that acquires the spike signal from the first neuron circuit outputs a synaptic current of a current amount corresponding to the control signal and a synaptic weight.

A neural network device according to an embodiment includes a plurality of neuron circuits and a plurality of synapse circuits. In a case where an internal state value of a second neuron circuit is larger than a set determination reference value, a first synapse circuit among the synapse circuits executes potentiation processing to increase the degree of influence of a synaptic weight on a synapse signal in response to acquiring the input spike from the first neuron circuit. In response to outputting an output spike being a spike signal from the second neuron circuit, the first synapse circuit executes attenuation processing to decrease the degree of influence of the synaptic weight on the synapse signal.

The application provides a pulse neural network structure, comprising a first neuron, a synaptic unit and a second neuron connected in sequence, and a probability selection unit connected with the first neuron, the probability selection unit is used for generating a random number, the first neuron is used for determining a required action of the synaptic unit as a long-term potentiation action or a long-term depression action according to an actual time difference of a first pulse emitted by the first neuron and a second pulse emitted by the second neuron, when the random number is a preset random number, an adjusting pulse is sent to the synaptic unit according to the required action of the synaptic unit, the synaptic unit is used for storing a synaptic weight, and the synaptic weight is adjusted according to the adjusting pulse. In the embodiment of the application, the probability selection unit is designed based on a resistive random access memory, a large amount of resources is saved, and the stability is relatively high without depending on the device characteristics of the resistive random access memory, so that higher device consistency can be realized by using limited resources.

This invention relates to the field of neuromorphic computing technology and provides a method and system for dynamic adjustment of synaptic weights in real-time neurofeedback for neuromorphic chips. The method includes: capturing the pulse signals and timestamps emitted by presynaptic and postsynaptic neurons; calculating the time difference between the presynaptic and postsynaptic pulses; when the absolute value of the time difference is less than a preset time window threshold, querying a pulse timing dependency plasticity rule base based on the sign of the time difference to determine the corresponding synaptic weight adjustment type; generating corresponding voltage pulse parameters based on the adjustment type and the current conductance state of the target memristor synapse; and applying a write voltage pulse to the target memristor synapse according to the voltage pulse parameters to adjust its conductance value in situ in real time, thereby dynamically updating the synaptic weights. This invention solves the problems of poor dynamic environment adaptability, low energy efficiency, and high learning latency caused by traditional offline weight update mechanisms.

The application provides a brain-like synapse learning method and a brain-like technology neural morphological hardware system, and the method comprises the following steps: determining a pulse pair generated by a presynaptic neuron and a postsynaptic neuron in a brain-like synapse learning circuit, wherein the pulse pair comprises an input pulse generated by the presynaptic neuron and an output pulse generated by the postsynaptic neuron; determining an STDP mechanism corresponding to the pulse pair and a synapse weight corresponding to the STDP mechanism based on the pulse pair; and performing STDP learning corresponding to the brain-like synapse learning circuit based on the pulse pair and the synapse weight; wherein the STDP mechanism is a pulse time-dependent plasticity mechanism, and the front and rear pulses of the pulse pair correspond to a long-term potentiation process or a long-term depression process in the STDP mechanism according to the time sequence. The application realizes online learning of brain-like intelligence, and plays the environment self-adaptive characteristics of brain-like computing.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

The invention relates to the technical field of brain-computer interfaces, and discloses a brain-computer interface system based on quantum nerve coupling and miniature nuclear fusion energy supply and an enhancement method. The quantum neural chip is composed of a boron phosphide quantum dot array, the distance between quantum dots is smaller than or equal to 5 nm, and the quantum neural chip is coupled with neurons through the quantum tunneling effect; the neural mimicry processing module adopts a pulse neural network (SNN) to analyze a multi-modal neural signal in real time and integrates a dynamic synaptic weight adjustment unit; the miniature nuclear energy-gathering energy supply module is designed based on a star simulator, the deuterium and tritium fuel loading capacity is smaller than or equal to 1 mg, the constraint magnetic field intensity is larger than or equal to 5 T, and the output power density is larger than or equal to 0.5 W / cm < 2 >.

The invention provides a neural network training method and device, equipment and a medium, and the method comprises the following steps: 1, obtaining training data of an image, voice or text type, and carrying out the normalization and feature extraction processing; according to the invention, the three-terminal two-dimensional photoelectric synapse device is prepared, a single / double input mode is supported, cooperative regulation and control of an optical pulse sequence and a grid electric signal sequence are realized, the problem that the multi-mode processing capability of a traditional double-terminal device is limited is solved, and the complex feature extraction efficiency is improved; the nonvolatile storage of synaptic weight is realized through the ferroelectric regulation and control layer, and the remanent polarization of the ferroelectric regulation and control layer is Prgt; 5 [mu] C / cm < 2 > and erasing durability gt; 106 cycles are carried out, continuous power supply is not needed, and training power consumption and cost are reduced; through the high carrier mobility (gt, 200cm < 2 > / Vs) and nanosecond-level photoresponse characteristics (carrier lifetime lt, 10ns) of the two-dimensional photosensitive layer (such as MoS2 / WSe2), the response speed of the device is increased to nanosecond level, and the training requirement of a high-speed neural network is met.

This invention discloses a photonic neural synapse device with a dual-micro-ring structure and a convolutional computation network model. The device includes a front resonant ring, a rear resonant ring, and two coupled phase-change material (PCM) films. The two PCM films are matched and correspond to the front and rear resonant rings, respectively. Synaptic weighting is achieved by controlling the coupled PCM films. The front and rear resonant rings are used to split the input optical signal in the bus waveguide into a 50:50 ratio, and output the difference signal current through a balanced photodetector. The photonic neural synapse of this invention has the advantages of high bandwidth and high speed. Once the synaptic weights are determined, it is a passive device with theoretically zero power consumption. Furthermore, this invention designs a dual-micro-ring structure, which ensures that the modulation of light does not affect the resonant wavelength, improving modulation accuracy, reducing optical transmission loss, and broadening the range of synaptic weights. This invention can be widely applied in the field of micro-nano optoelectronics.

There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter. There is also provided a corresponding method of operating and a corresponding method of forming the neurosynaptic processing core.

The present invention provides systems and methods for utilizing an application-specific integrated circuit (ASIC) for an artificial neural network connected to the memory, the ASIC comprising: a plurality of neurons organized in an array, wherein each neuron comprises a register, a processing element and at least one input, and a plurality of synaptic circuits, each synaptic circuit including a memory for storing a synaptic weight, wherein each neuron is connected to at least one other neuron via one of the plurality of synaptic circuits, wherein the array is configured to analyze said business sale transaction information trained on historical datasets relating to asset utilization, wherein the AI / ML categorization engine makes a prediction regarding the most efficient use(s) of an asset.

Embodiments relate to a semiconductor device including a body made of a first conducting semiconductor material, a source and a drain made of a second conducting semiconductor material and formed on the body, a first gate formed on the body with a gate insulating layer interposed between the first gate and the body, a second gate formed opposite the first gate with respect to the body, and an insulating layer stack having a charge storage layer formed between the body and the second gate, and a method for controlling a synapse weight of a target semiconductor device within a neural network including semiconductor devices.

An example method of the presently disclosed technology may include: (1) transforming a neural network from an artificial neural network (ANN) to a spiking neural network (SNN); (2) when the neural network is transformed into the SNN, modifying synaptic weights of the neural network by applying a simulated memory replay process to the neural network; and (3) after applying the simulated memory replay process to the neural network, transforming the neural network from the synaptic weight-modified SNN to a synaptic weight-modified ANN.

Optical synapse (1; 30; 50; 80), which has: a memristive unit (2; 31; 52; 60; 70) for non-volatile storage of a synaptic weight that depends on a resistance of the unit; and an optical modulator (3; 20) for a fleeting modulation of an optical transmission in a waveguide (4; 81); and wherein the memristive unit and the optical modulator are connected in a control circuit (5; 54) which is capable of supplying a programming signal for programming the synaptic weight to the memristive unit in a write mode and of supplying an electrical signal dependent on the synaptic weight to the optical modulator in a read mode, thereby volatilely controlling the optical transmission in dependence on the programmed synaptic weight.

Systems and methods for generating Artificial Neural Networks (ANNs) based on the principles of biological sleep are disclosed. Namely, the systems and methods can be configured to apply a sleep-like phase to ANNs which enables training to be generalized, performance to be improved, and catastrophic forgetting for sequential multi-task training to be prevented. Various implementations of these systems and methods can be configured to: (i) train an ANN using backpropagation algorithm, (ii) convert the architecture of the ANN to an equivalent Spiking Neural Network (SNN) and simulate a sleep phase in the SNN while using plasticity rules to modify synaptic weights, and (iii) convert the modified synaptic weights associated with the simulated sleep phase of the SNN back into the ANN. This transformation from ANN to SNN to ANN effectively emulates learning mechanisms actuated during biological sleep and, as such, overcomes limitations commonly associated with machine learning.

The application relates to a light-emitting electrochemical artificial synapse with a photoelectric signal parallel output function, which comprises, from bottom to top, a substrate, a bottom electrode, a light-emitting active layer and a top electrode; the light-emitting active layer is composed of a light-emitting material, an ion transmission matrix and a lithium salt; when a continuous voltage pulse is input, the light-emitting material in the active layer and the ion transmission matrix have an electrochemical oxidation-reduction reaction, which causes the gradual increase of the device conductance, and the post-synaptic current is also gradually increased; meanwhile, with the increase of the electron and hole injection, the transient electroluminescence intensity is also gradually increased. The application can simultaneously take the output light signal and the electric signal intensity as the synapse weight, can be used for constructing an optical and electrical hybrid artificial neural network, and provides a brand-new feasible scheme for realizing a neural morphological computing system taking light and electricity as media.

The invention relates to the field of artificial intelligence and the field of integrated circuits, in particular to a chip for in-memory calculation of a spiking neural network, which comprises a synaptic weight storage array for storing synaptic weights; the threshold storage array is used for storing a neuron threshold voltage; the membrane potential storage array is used for storing a neuron membrane potential, a bit line of the membrane potential storage array is connected with a bit line of the synaptic weight storage array, and logic calculation results of the synaptic weight and the neuron membrane potential are directly generated on the connected bit lines; the membrane potential accumulation unit obtains a membrane potential accumulation result through processing of an addition logic circuit; the comparison unit is used for opening read sub-lines of the membrane potential storage array and the threshold voltage storage array and multiplexing an addition logic circuit to realize subtraction calculation of a membrane potential accumulation result and a threshold voltage; and the transmitting unit is used for judging whether the neurons output pulses or not and resetting the membrane potential. The method can achieve the push-training integration of in-memory calculation, remarkably improves the SNN operation energy efficiency, and reduces the power consumption.