55 results about "Synaptic weight" patented technology

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit out of the neuron circuits includes an input circuit, a charge holding circuit, a comparison circuit, a firing circuit, a charge control circuit, and a control signal output circuit. When a determination signal changes from a second value to a first value, the firing circuit outputs a spike signal. The control signal output circuit outputs a control signal indicating a comparison voltage that is based on an excess component of a membrane potential exceeding a threshold potential. In response to acquiring the spike signal from the first neuron circuit, a first synapse circuit out of the synapse circuits that acquires the spike signal from the first neuron circuit outputs a synaptic current of a current amount corresponding to the control signal and a synaptic weight.

This invention relates to the field of neuromorphic computing technology and provides a method and system for dynamic adjustment of synaptic weights in real-time neurofeedback for neuromorphic chips. The method includes: capturing the pulse signals and timestamps emitted by presynaptic and postsynaptic neurons; calculating the time difference between the presynaptic and postsynaptic pulses; when the absolute value of the time difference is less than a preset time window threshold, querying a pulse timing dependency plasticity rule base based on the sign of the time difference to determine the corresponding synaptic weight adjustment type; generating corresponding voltage pulse parameters based on the adjustment type and the current conductance state of the target memristor synapse; and applying a write voltage pulse to the target memristor synapse according to the voltage pulse parameters to adjust its conductance value in situ in real time, thereby dynamically updating the synaptic weights. This invention solves the problems of poor dynamic environment adaptability, low energy efficiency, and high learning latency caused by traditional offline weight update mechanisms.

The application provides a brain-like synapse learning method and a brain-like technology neural morphological hardware system, and the method comprises the following steps: determining a pulse pair generated by a presynaptic neuron and a postsynaptic neuron in a brain-like synapse learning circuit, wherein the pulse pair comprises an input pulse generated by the presynaptic neuron and an output pulse generated by the postsynaptic neuron; determining an STDP mechanism corresponding to the pulse pair and a synapse weight corresponding to the STDP mechanism based on the pulse pair; and performing STDP learning corresponding to the brain-like synapse learning circuit based on the pulse pair and the synapse weight; wherein the STDP mechanism is a pulse time-dependent plasticity mechanism, and the front and rear pulses of the pulse pair correspond to a long-term potentiation process or a long-term depression process in the STDP mechanism according to the time sequence. The application realizes online learning of brain-like intelligence, and plays the environment self-adaptive characteristics of brain-like computing.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

This invention discloses a photonic neural synapse device with a dual-micro-ring structure and a convolutional computation network model. The device includes a front resonant ring, a rear resonant ring, and two coupled phase-change material (PCM) films. The two PCM films are matched and correspond to the front and rear resonant rings, respectively. Synaptic weighting is achieved by controlling the coupled PCM films. The front and rear resonant rings are used to split the input optical signal in the bus waveguide into a 50:50 ratio, and output the difference signal current through a balanced photodetector. The photonic neural synapse of this invention has the advantages of high bandwidth and high speed. Once the synaptic weights are determined, it is a passive device with theoretically zero power consumption. Furthermore, this invention designs a dual-micro-ring structure, which ensures that the modulation of light does not affect the resonant wavelength, improving modulation accuracy, reducing optical transmission loss, and broadening the range of synaptic weights. This invention can be widely applied in the field of micro-nano optoelectronics.

There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter. There is also provided a corresponding method of operating and a corresponding method of forming the neurosynaptic processing core.

The present invention provides systems and methods for utilizing an application-specific integrated circuit (ASIC) for an artificial neural network connected to the memory, the ASIC comprising: a plurality of neurons organized in an array, wherein each neuron comprises a register, a processing element and at least one input, and a plurality of synaptic circuits, each synaptic circuit including a memory for storing a synaptic weight, wherein each neuron is connected to at least one other neuron via one of the plurality of synaptic circuits, wherein the array is configured to analyze said business sale transaction information trained on historical datasets relating to asset utilization, wherein the AI / ML categorization engine makes a prediction regarding the most efficient use(s) of an asset.

Systems and methods for generating Artificial Neural Networks (ANNs) based on the principles of biological sleep are disclosed. Namely, the systems and methods can be configured to apply a sleep-like phase to ANNs which enables training to be generalized, performance to be improved, and catastrophic forgetting for sequential multi-task training to be prevented. Various implementations of these systems and methods can be configured to: (i) train an ANN using backpropagation algorithm, (ii) convert the architecture of the ANN to an equivalent Spiking Neural Network (SNN) and simulate a sleep phase in the SNN while using plasticity rules to modify synaptic weights, and (iii) convert the modified synaptic weights associated with the simulated sleep phase of the SNN back into the ANN. This transformation from ANN to SNN to ANN effectively emulates learning mechanisms actuated during biological sleep and, as such, overcomes limitations commonly associated with machine learning.

A neuro-synaptic processing circuitry for performing event-based neuro-synaptic operations based on synaptic weights and neuron states, the circuitry comprising: a data memory configured to store the synaptic weights; one or more neuron processing elements, NPEs, configurable to execute NPE instructions for performing the event-based neuro-synaptic operations; a controller configured to determine the event-based neuro-synaptic operations in function of one or more neuro-synaptic events; wherein the controller is further configured to generate the NPE instructions from the event-based neuro-synaptic operations; and weight-evaluating means configured to determine if one or more of the synaptic weights have a value of zero; and wherein, if the weight-evaluating means determines one or more of the synaptic weights having a value of zero, the NPEs are configured to omit executing one or more of the NPE instructions involving the one or more of the synaptic weights having a value of zero.

The application discloses an image orientation recognition method and device, equipment and a storage medium. The method comprises the following steps: using a projection neural network to preprocess a target image to obtain standard image data, the preprocessing comprising dimension reduction, noise reduction, normalization, cutting and gain control; encoding the standard image data according to APL neurons and a WTA mechanism through a preset KC layer to obtain encoded image data, the projection neural network and the preset KC layer comprising first synaptic weights subject to random distribution; inputting the encoded image data into a preset MBON layer for orientation analysis to obtain an orientation recognition result, the preset KC layer and the preset MBON layer comprising second synaptic weights updated based on a preset update algorithm. The application avoids the problems of catastrophic forgetting or low learning speed of the existing image orientation recognition model due to large distribution difference of samples with the same label, and avoids the problems of low learning and recognition efficiency of rare details in the image caused by the use of convolution kernels.

This application belongs to the interdisciplinary fields of semiconductor optoelectronic devices, multiferroic materials, and neuromorphic computing. Specifically, it discloses an in-situ differential optoelectronic synaptic device and its in-memory computing method. The method involves grounding the first and second electrodes, applying a voltage to the bottom electrode to change the polarization direction of the ferroelectric domains in the bismuth ferrite thin film, and using the polarization direction of the ferroelectric domains as the weight symbol in the neural weights to set the non-volatile synaptic weights. The voltage on the bottom electrode is then removed or reduced, and a light spot is used to illuminate the bismuth ferrite thin film. By adjusting the position of the light spot, the differential current between the first and second electrodes is read and used as the weight value in the neural weights, thus realizing the read operation. This application achieves integrated storage and computing.

The invention discloses a quantum neuromorphic attention alignment algorithm based on AR and VR, and belongs to the technical field of quantum, and the algorithm comprises the steps: obtaining pulse data; the amplitude and the phase are coded, mapping to the Hilbert space is realized through a parameterized quantum gate, and a trainable attention weight is obtained; a pulse neural network is used for processing quantum state characteristics, an IZHXY neuron model is used for realizing a dynamic threshold mechanism, and synaptic weight updating follows an STDXY rule; according to the method, adversarial training is carried out through a quantum encoding QELXY device Q (x) and a classic generator G (z), modal alignment is realized through a WASSXY distance, the problems of modal splitting, intention misjudgment and low energy efficiency faced by an existing VR / AR algorithm can be solved, intelligent alignment and prediction of multi-sensory information in a virtual environment are realized, and user experience and system performance are improved.

The CMOS neuron-synaptic unit circuit system suitable for the spiking neural network is realized, so that network parameters of the spiking neural network are effectively initialized, and the weight is dynamically adjusted to promote information propagation and learning. The CMOS neuron-synaptic unit circuit system comprises a front LIF neuron circuit module which receives an input pulse signal and generates an output pulse through integration; the synapse circuit receives the output pulse and adjusts the transmission intensity of the signal by adjusting the real-time weight; the STDP circuit adjusts the synaptic weight according to the time difference between the pulse output by the front LIF neuron circuit module and the pulse output by the rear LIF neuron circuit module; the ATML circuit receives the output pulse of the front LIF neuron circuit module and the output pulse of the rear LIF neuron circuit module, and adjusts the weight of the STDP to update the length of a time window by changing the size of a time window length signal Vleak; and the LIF neuron circuit receives the signal from the synaptic circuit module, and simulates the neuron signal integration and pulse generation process again.

The application is applied to the field of mechanical fault diagnosis signal processing, and particularly discloses a mechanical fault diagnosis method based on STFT dimension transformation, which comprises the following steps: collecting a one-dimensional mechanical vibration signal, and performing wavelet decomposition; performing wavelet reconstruction on low-frequency components and high-frequency components after denoising processing, so as to obtain a one-dimensional vibration signal after denoising; performing short-time Fourier transform, so as to convert the signal into a time-frequency two-dimensional matrix; inputting the time-frequency two-dimensional matrix into an improved HH threshold neuron model, performing Poisson sparse coding on the time-frequency two-dimensional matrix, and only performing pulse response on signal significant features; constructing a threshold coding convolution network with residual connection, inputting a sparse coding matrix, training by using an unsupervised learning rule based on STDP, and adaptively adjusting network synaptic weights; inputting into the trained threshold coding convolution network, and determining a fault diagnosis result by means of pulse firing activities of output layer neurons obtained through network forward propagation.

The application discloses a small-scale Hopfield neural network circuit based on a memristor, which comprises an activation function module circuit, a memristor model circuit and a Hopfield neural network circuit; the Hopfield neural network circuit comprises three neuron networks X1, X2 and X3; and a connection weight in the Hopfeild neural network is replaced by the memristor module circuit to obtain a new neural network. By replacing the synaptic weight of the Hopfield neural network system, it is found that the originally stable system exhibits rich dynamic behaviors, including chaos, hyperchaos, quasi-periodicity, double-vortex attractor and the like. The circuit is simple in design, and can adjust the weight parameters Rr and the parameter w32 to realize various dynamic behaviors. Therefore, the circuit can be used in the field of secret communication and is helpful for the research on the nervous system.

The invention relates to the field of emergency management, in particular to a bionic neural network recombination method based on swarm intelligence. The method comprises the steps that a node topological relation based on all agents is established, and an equipment connection strength map is obtained; the node topological relation comprises neuron nodes and synaptic weights; and when the neuron nodes in the equipment connection strength atlas are detected to be invalid, triggering synaptic weight redistribution to realize bionic neural network recombination. In this way, a quantifiable equipment connection strength map is established, and a dynamic data basis is provided for topology reconstruction; when the intelligent agent node has a fault, the load is rebalanced and the service is not interrupted through subsequent topology self-healing, so that the reliability of the communication network is ensured.

The present application belongs to the technical field of bioelectric signal processing and control, and specifically relates to a non-stationary signal codec-free adaptive control method based on a neuromorphic device. The present application directly feeds the collected non-stationary bioelectric signal as a physical excitation into the neuromorphic hardware; by using the transient amplitude-frequency characteristics of the input signal, the dynamic evolution of the synaptic weight is induced through the bottom-layer pulse time-dependent plasticity, and the action pulse is triggered to drive the external physical actuator; the action of the external physical actuator causes natural sensory feedback, promotes the spontaneous remodeling of the power spectral density and phase-amplitude coupling index of the bioelectric signal, and then reversely guides the spontaneous attenuation and convergence of the hardware weight to the optimal steady state. The present application overturns the traditional closed-loop control paradigm of "analog-digital conversion-software algorithm decoding-feature matching", and can realize the adaptive closed-loop driving of complex signals without artificial algorithm code, thereby providing a new physical-level methodology for bionic control and bio-mechatronic adaptive interaction.

The invention discloses a forgetting mechanism conditioned reflex circuit based on a memristor neural network. The circuit is composed of three signal conditioning modules, two feedback regulation and control modules and two reflex generation modules. The signal adjusting module realizes discrimination, amplitude regulation and control and delay shaping of an input signal through a comparator and an operational amplifier; the feedback regulation and control module outputs an enhanced voltage, a weak suppression voltage or a strong suppression voltage according to the combination of the reward signal and the behavior signal, so as to realize differentiation regulation and control on the synaptic weight; and the reflection generation module dynamically changes or detects the resistance value of the memristor by using the write-read characteristic of the memristor, and outputs conditioned reflex behavior signals through the logic gate circuit. The provided forgetting mechanism conditioned reflex circuit can realize the functions of learning, forgetting, generalization, differentiation and the like on the hardware level, the conditioned reflex mechanism in the biological neural network is relatively completely simulated, and the forgetting mechanism conditioned reflex circuit has relatively high biological authenticity and hardware implementation value.

The invention relates to the technical field of MOS (metal oxide semiconductor) transistors, and discloses a neural morphology computing chip based on a single transistor synapse array, which sequentially comprises a carbon nano transistor, a vertical interconnection layer and a floating gate transistor from top to bottom, a dielectric layer is filled between the carbon nano transistor and the vertical interconnection layer, and a dielectric layer is filled between the vertical interconnection layer and the floating gate transistor. The interior of the carbon nano transistor sequentially comprises a gate electrode layer, a gate dielectric layer and a carbon nano tube layer from top to bottom. According to the neuromorphic computing chip based on the single-transistor synaptic array, the carbon nano-transistors and the floating gate transistors are integrated in a three-dimensional stacked structure, so that integration of sensing, storage and computing functions is realized, and photoelectric response characteristics of the carbon nano-tubes are used as input trigger signals; and the nonvolatile modulation of the synaptic weight is realized through a floating gate layer charge storage mechanism, so that the integration density and the energy efficiency ratio of the synaptic unit are remarkably improved, and a feasible technical path is provided for realizing large-scale neural network hardware.

The application discloses a kind of synaptic weight flexible generation large-scale brain simulation method and system, comprising: according to the input brain simulation network information, create neuron cluster;Determine the generation mode of synaptic weight, generation mode is generated in advance and / or on-demand generation;Create the connection between neuron cluster, if generation mode is generated in advance, save the delay of synaptic connection and synaptic weight, if generation mode is on-demand generation, save the delay of synaptic connection;Run brain simulation network simulation, in simulation process, if generation mode is generated in advance, directly read the synaptic weight saved, if generation mode is on-demand generation, randomly generate synaptic weight.The application simultaneously supports synaptic weight generation in advance and on-demand generation, retains the integrity of brain simulation network synaptic plasticity function.

This disclosure provides an apparatus and method for implementing a spiking neural network based on a hardware acceleration unit, relating to the field of digital integrated circuits. The apparatus includes: an encoder configured to encode input data into a pulse sequence and generate an input pulse matrix for the current time step based on the pulse sequence; a hardware acceleration unit matrix module configured to calculate the input pulse matrix and synaptic weight matrix for the current time step to generate a synaptic input current matrix for the current time step; a membrane potential update and leakage module configured to perform membrane potential leakage calculation and membrane potential update calculation for the current time step based on the membrane potential state of the previous time step and the synaptic input current matrix for the current time step to obtain the membrane potential for the current time step; and a pulse output sequence distribution module configured to perform a threshold comparison between the membrane potential for the current time step and a threshold matrix to generate an output pulse matrix for the current time step.

Neural inference processors are provided. Each processor includes a plurality of cores. Each core includes a neural computation unit, an activation memory, and a local controller. The neural computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The activation memory is adapted to store the input activations and the output activations. The local controller is adapted to load the input activations from the activation memory to the neural computation unit and to store the plurality of output activations from the neural computation unit to the activation memory. The processor includes a neural network model memory adapted to store network parameters, including the plurality of synaptic weights. The processor includes a global scheduler operatively coupled to the plurality of cores, adapted to provide the synaptic weights from the neural network model memory to each core.

The application relates to the field of artificial intelligence chips, in particular to an AI chip processing control method and system based on multiple communication protocols, which are applied to an AI chip containing a leakage integral neuron calculation array and comprise the following steps: receiving multiple protocol frames and mapping priority scalars, and converting into an asynchronous pulse sequence; monitoring the heat conduction direction of a silicon substrate to generate a thermal phonon concentration gradient vector, and extracting a projection component of the thermal phonon concentration gradient vector in the direction of neuron connection; reconstructing synaptic conductance by combining the priority scalar and the projection component, generating asymmetric forward and reverse synaptic weights; triggering a non-Hermite skin effect when the weight difference exceeds a critical point, driving pulse polarization to a unidirectional topology edge channel transmission calculation; extracting a dynamic energy band gap by scanning a Hamiltonian eigenvalue spectrum, and executing physical truncation closed-loop control when the gap falls below a safety threshold. The application realizes the determinacy penetration of high-priority protocols in a thermal field environment by using a physical topology mechanism, and solves the problems of signal decoherence and routing blockage.

According to the method, initialization of the pulse neural network is meta-learned by introducing an excitation-suppression balance mechanism constrained by the Deler law, and internal representation widely applicable to many small sample tasks is constructed. In order to ensure that the Thevener's law is strictly obeyed in the synaptic weight updating process, an improved projection gradient descent method is combined with synaptic plasticity, so that the nervous excitability and inhibition characteristics are kept unchanged. According to the invention, an excitation-suppression balance mechanism constrained by the Devener's law is introduced into pulse element learning, and a small sample pulse element learning method based on excitation-suppression balance under the constraint of the Devener's law is provided. In order to enhance the stability and generalization of pulse element learning, a multi-step weighted loss strategy is further developed to guide the element learning of the pulse neural network. The small sample pulse element learning method based on excitation-suppression balance under the constraint of the Devener's law is superior to an early element learning method based on an artificial neural network in some specific tasks, and is completely superior to MAML of a pulse version.

An ASIC for an artificial neural network includes an array of neurons each including a register, processing element, and input; and synaptic circuits each including a memory for storing a synaptic weight. Each neuron is connected to another neuron via a synaptic circuit. The processing elements receive data sets from different providers, the data sets including data features representative of locations used in connection with flying aircraft. The processing elements examine the data features using the synaptic weights and the synaptic circuits to identify duplicative data features, select one or more of the duplicative data features for elimination based on prior selections; and send remaining data features to data consumers for use in flying or managing flight of one or more aircraft.

Minimize the loss of information transmitted. [Solution] The neural network device comprises a plurality of synaptic circuits and a plurality of neuron circuits. The first neuron circuit among the plurality of neuron circuits has an input circuit, a charge holding circuit, a comparison circuit, a firing circuit, a charge control circuit, and a control signal output circuit. The firing circuit outputs a spike signal when the judgment signal changes from a second value to a first value. The control signal output circuit outputs a control signal that represents a comparison voltage based on the excess component that exceeds the threshold potential at the membrane potential. The first synaptic circuit among the plurality of synaptic circuits that acquires the spike signal from the first neuron circuit outputs a control signal and a synaptic current of a current amount corresponding to the synaptic weight when it acquires the spike signal from the first neuron circuit.

The application provides a storage device operation method and a storage device, relates to the technical field of neural networks, and is used for avoiding the case that the conductance of a storage unit in the storage device changes slowly. The storage device comprises a storage unit array composed of a plurality of storage strings, the storage string comprises a plurality of storage units, and the conductance of at least one storage unit in the plurality of storage units is a synaptic weight between a first neuron and a second neuron. The method comprises the following steps: applying a first pulse voltage to a target storage unit to perform a first operation on the target storage unit, wherein the target storage unit comprises the at least one storage unit; and applying a second pulse voltage to the target storage unit to perform a second operation on the target storage unit, wherein the absolute value of the second pulse voltage is greater than the absolute value of the first pulse voltage.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. Each of the synapse circuits acquires one or more spike signals output from one of the neuron circuits, and, in response to acquiring the spike signals, outputs a synaptic current with a current amount corresponding to an assigned synaptic weight and the spike signals. A first neuron circuit out of the neuron circuits outputs N spike signals as the one or more spike signals. The first neuron circuit includes a spike output circuit to output at least an n-th spike signal out of the N spike signals when the membrane potential is higher than an n-th threshold potential out of the N threshold potentials different from each other.

Provided is a method of operating a neuron in a neuromorphic system. The method includes evaluating a membrane potential value at a corresponding time when receiving an input spike, time-modulating a synaptic weight of the membrane potential value and converting the time-modulated synaptic weight into a membrane potential value at a reference time, and generating an output spike when the membrane potential value at the reference time exceeds a certain threshold value. The membrane potential value at the reference time is represented by a floating point number including a predetermined bit of exponent and mantissa, and the floating point number includes time information. The method further includes accessing a memory and scanning a neural state variable when a timer is updated to “0” to update the neural state variable to an updated value at a reference time.