60 results about "Digital circuit design" patented technology

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

The invention discloses a digital circuit design method and device, equipment and a medium, and relates to the technical field of digital circuits, and the method comprises the steps: determining a target type of a to-be-designed digital circuit, and collecting a first training set corresponding to the target type; each training sample in the first training set comprises an input feature item used for designing a target type of historical digital circuit and the actual result quality of the historical digital circuit, and the input feature item comprises a high-level language source code and an HLS constraint parameter; constructing an initial prediction model based on the multi-layer perceptron mixed structure, training the initial prediction model by using the first training set, and searching and optimizing the model architecture based on the network structure to obtain a target prediction model; and predicting the actual result quality corresponding to each parameter combination in a target design space of a to-be-designed digital circuit by using the model, and designing the digital circuit by using the parameter combination of which the quality meets the Pareto frontier. And predicting an accurate actual quality result by utilizing a prediction model without intermediate representation so as to carry out digital circuit design.

The invention discloses a data processing method and device, equipment, a storage medium and a product, the method is applied to integrated circuit electronic design automation software, and the method comprises the following steps: obtaining a digital circuit design file; analyzing the digital circuit design file to generate a corresponding netlist data structure; responding to an object query request sent by a user, accessing the netlist data structure, and searching a data item matched with a target query object specified by the user in the netlist data structure; based on the data item matched with the target query object specified by the user and found in the netlist data structure, the object query result is generated, the netlist data structure is adopted as a data processing basis for object query, hierarchical recursive traversal does not need to be carried out, branch relations among multi-way tree nodes do not need to be processed, and the data query efficiency is improved. And the query efficiency is obviously improved.

The invention relates to a hardware description language generation method and system based on a large language model, and the method comprises the following steps: S1, generating an initial digital circuit design code by adopting the large language model; s2, performing grammar verification on the initial digital circuit design code to obtain grammar verification information; s3, correcting the initial digital circuit design code according to the grammar verification information to obtain a corrected digital circuit design code; s4, performing simulation verification on the corrected digital circuit design code to obtain simulation verification information; s5, judging whether the large language model needs to be optimized or not according to the simulation verification information, if yes, optimizing the large language model, and returning to execute the step S1 after the large language model is optimized; if not, outputting a corrected digital circuit design code, and storing the corrected digital circuit design code to a sample database; according to the method, a'generation-verification-optimization 'closed-loop architecture is constructed, and the code error rate is reduced.

Systems and methods are provided for propagation determinations of unknown values in logic simulations of digital circuit designs. A method may include accessing (402) a digital circuit design (210) and parsing (404) the digital circuit design (210) to detect state elements. The method may also include performing (406) a logic simulation on the digital circuit design (210) that includes tracking propagation of x-values in the digital circuit, wherein the x-values represent an unknown value for an output of a digital circuit design element. During the logic simulation, method steps can include tracking (408) the state elements of the digital circuit design (210) to determine when any output of the state elements is the x-value during the logic simulation and triggering (410) an x-propagation response when an x-propagation criterion is satisfied based on detected x-value outputs for the state elements of the digital circuit design (210).

According to various embodiments of the present invention, a regression analysis-based circuit characteristic optimization device for digital circuit design may: receive, from the outside, information about a digital circuit to be designed, and arbitrarily set a characteristic value for at least one transistor included in the digital circuit; generate a circuit characteristic regression model by mathematically modeling the characteristic of a path included in the digital circuit on the basis of the characteristic value of the transistor included in the digital circuit; obtain an initial coefficient of the circuit characteristic regression model by applying the arbitrarily set characteristic value thereto; and obtain the improved characteristic value for the at least one transistor included in the digital circuit on the basis of the circuit characteristic regression model into which the initial coefficient has been incorporated.

The invention relates to the field of digital circuit design, and provides a method for optimizing noise influence of a synchronous switch in an IBIS model. When a traditional IBIS model measures pull-up / pull-down characteristics, it is assumed that a power supply and ground potential are constant, voltage fluctuation actually caused by a synchronous switch is ignored, and the simulation precision of a high-speed interface is reduced. By collecting current response data of a pull-up circuit and a pull-down circuit of the buffer under different power supply / ground fluctuations, pull-up and pull-down power supply modulation coefficients are calculated respectively, and the influence of power supply voltage disturbance on output current is represented. In the simulation stage, the output current in the IBIS model is dynamically modulated according to the power supply and ground potential change caused by the real-time SSN, so that the simulation is closer to the real chip behavior. The method does not need to modify a model structure, is compatible with an existing process, remarkably improves the accuracy of high-speed signal integrity analysis, is suitable for design verification of DDR, PCIe and other high-density parallel interfaces, and effectively supports the system-level power supply and signal co-simulation requirements.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

A digital circuit design method, apparatus, electronic device, and storage medium. The digital circuit design method includes: determining at least one target logic module in at least one sub-design that requires engineering modification; performing engineering modification processing on each target logic module; wherein the engineering modification processing includes: determining the difference between the target logic module before and after physical implementation; based on the difference, reconstructing the target logic module to obtain a reconstructed logic module, wherein the reconstructed logic module matches the state elements in the target logic module; and performing engineering modification on the reconstructed logic module to obtain a modified logic module. The digital circuit design method enables engineering modification at a module granularity, eliminating design restrictions on engineering modification, greatly improving the efficiency of engineering modification and accelerating project R&D progress.

The invention provides a data verification circuit and method, a chip, an electronic device and electronic equipment, and relates to the technical field of circuit design, and through connection of multiple layers of AND gates and OR gates, AND operation and OR operation are continuously performed, so that a final result can intuitively reflect the quantity condition of effective data in to-be-verified data, and the data verification efficiency is improved. Therefore, whether the to-be-verified data is the target data can be determined. And each layer in the circuit is subjected to AND operation and OR operation based on the AND gate and the OR gate at the same time, so that the generated time delay is relatively small, and application in large-scale and high-speed digital circuit design is facilitated.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The invention discloses a verification method for a digital circuit design of a large-area-array infrared image sensor, and the method comprises the steps: carrying out the analysis of a to-be-verified digital circuit design feature, and obtaining an analysis result; classifying each module in the digital circuit design to obtain a plurality of to-be-modeled modules; modeling input, output and functions of the to-be-modeled module according to an analysis result to form a plurality of universal verification modules; a plurality of universal verification modules are connected with a digital circuit to be verified according to connection requirements, a complete circuit is established, and a verification platform is formed; executing simulation based on the verification platform to obtain a simulation result; and optimizing the digital circuit design according to a simulation result. And the effect of quickly and accurately positioning the design problem is achieved.

The invention relates to the technical field of integrated circuit design, and discloses a module data generation method based on an abstract syntax tree, electronic equipment and a storage medium, and the method comprises the steps: obtaining a digital circuit design file, analyzing the digital circuit design file, and generating a corresponding abstract syntax tree; identifying a module action range contained in the abstract syntax tree, and creating a variable relation data structure corresponding to the module action range; and determining the signal association relationship between the leaf nodes, and creating the association relationship object in the variable relationship data structure based on the signal association relationship between the leaf nodes, thereby effectively avoiding the problem that the signal interaction relationship between the leaf nodes is difficult to accurately identify only depending on an abstract syntax tree. Therefore, the efficiency and the accuracy of calculating and analyzing the signal incidence relation in the module action range by electronic design automation software are improved.

The application relates to the technical field of integrated circuit design, and discloses a module data generation method based on an abstract syntax tree, an electronic device and a storage medium, the method comprising the following steps: acquiring a digital circuit design file, analyzing the digital circuit design file, and generating a corresponding abstract syntax tree; identifying a module scope contained in the abstract syntax tree, and creating a variable relationship data structure corresponding to the module scope; determining a signal correlation relationship between leaf nodes, and creating a correlation relationship object in the variable relationship data structure based on the signal correlation relationship between the leaf nodes, so that the problem that it is difficult to accurately identify the signal interaction relationship between the leaf nodes by only relying on the abstract syntax tree is effectively avoided, and the efficiency and accuracy of calculation and analysis of the signal correlation relationship in the module scope by electronic design automation software are improved.

1. The name of this design product: FPGA teaching and training equipment. 2. The purpose of this design product: to master hardware description language, complete small and medium-scale digital circuit design, etc. 3. The design key point of this appearance design product lies in the shape. 4. The picture or photo that best illustrates the key points of the design: main view.

The implementations described herein relate to non-scannable flip-flops used within scannable digital circuits. For example, one illustrative method includes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; and based on this determination, modifying the scannable digital circuit design to integrate a multiplexing function controlled by a scan enable signal into the first stage, and converting the first scannable flip-flop to a non-scannable flip-flop. The method further includes: determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within a scannable digital circuit design; and based on this determination, retaining the second scannable flip-flop in the circuit design. Corresponding methods, circuits, media, and other implementations are also disclosed.

The invention discloses a residual life prediction system and method for an aero-engine, and belongs to the technical field of life prediction and the technical field of digital circuit design, and the system comprises a multi-modal data collection module, a data preprocessing module, a working mode arbitration module, a low-power-consumption health state evaluation module and a self-adaptive neural network processing module. The multi-modal data acquisition module is connected with the data preprocessing module, the data preprocessing module is connected with the working mode arbitration module, the working mode arbitration module is connected with the low-power-consumption health state evaluation module and the adaptive neural network processing module, and the low-power-consumption health state evaluation module is connected with the adaptive neural network processing module. According to the method, the calculation precision is adaptively adjusted according to the health condition of the aero-engine, so that the limited airborne calculation capability, memory and power consumption are dealt with.

The invention relates to an excitation file generation method and device, electronic equipment and a storage medium, which are applied to the technical field of digital circuit design, and the method comprises the following steps: defining a system clock according to a clock period set by a user in a human-computer interaction interface; according to the interface information in each model file called by the human-computer interaction interface and the interface connection relationship between the model files, defining an interface and assigning a value to the assigned input interface; declaring the name of each model file and the names of the input interface and the output interface in a to-be-generated excitation file; a value set for an input interface in the model file by a user on the human-computer interaction interface is obtained and assigned to the corresponding input interface in the excitation file to be generated, the clock signal is set to be 1, and the reset signal is set to be 0; according to the simulation duration set by the user on the human-computer interaction interface, the simulation duration is set, and after the simulation duration is over, the reset signal is set to be 1. The excitation file generation efficiency and accuracy can be improved.

The invention relates to the technical field of digital circuits, in particular to a method, device and equipment for reducing peak current, a medium and a digital circuit, and the method comprises the steps: obtaining the peak moment of the maximum instantaneous peak current of a target circuit; performing static time sequence analysis on the target circuit, acquiring arrival time and required time of each path in the target circuit, and taking a difference value obtained by subtracting the arrival time from the required time as a time sequence margin; determining the path of which the time sequence margin is greater than 0 as a non-critical path; acquiring a non-critical path where a target logic gate flipped at the peak moment is located as an insertion path; the time delay units are inserted into the insertion paths, so that the target logic gates of the insertion paths are staggered in the overturning time, the total time delay D of the time delay units inserted into the insertion paths meets the condition that D is smaller than or equal to Si-delta, Si is the time sequence margin of the insertion paths, and delta is the preset safety time sequence margin. The technical scheme can reduce the peak current of the digital circuit, and is mainly used for digital circuit design.

The invention belongs to the technical field of digital circuit design, and particularly relates to a TCAM (ternary content addressable memory)-based quick matching search method, which comprises the following steps of: combining a block RAM (random access memory) and a distributed RAM to construct a TCAM; according to the length of the search word, dividing the search word into a plurality of search sub-words according to bits; according to the length of a search sub-word, inputting the search sub-word into a sub-block RAM or a sub-distributed RAM, processing results of a plurality of sub-RAMs, inputting the processed results into an encoder, and outputting a matching address by the encoder; and searching a corresponding operation in the RAM of the matched address and executing the operation. Compared with the prior art, the method has the advantages that the Block RAM (BRAM) and the LUTRAM in the FPGA are comprehensively utilized to optimize the method for dividing the search words, the BRAM and the LUTRAM are flexibly combined, the optimized composite TCAM (OC-TCAM) which is closer to or even fits the number of bits of the search words is achieved, and consumption of storage resources is greatly reduced.

The invention belongs to the technical field of digital circuit design, and particularly relates to a polynomial time discriminant solver, which comprises the following steps of: S1, researching, applying and developing a Boolean function and a Boolean satisfiability discriminant solver in digital circuit design; comprising the following steps: judging whether a satisfiability condition exists or not by utilizing a Boolean satisfiability judgment solver and quickly finding out a working condition; and S2, selecting a proven NPC problem SAT, giving a solution of the SAT, and proving that the solution is completed in polynomial time, thereby proving that P is equal to NP. According to the method, by utilizing examples of three groups of circuit algebras, the high efficiency and usefulness of the given SAT solver are explained, and a complete mathematical proof is given, so that the method has the advantages of high efficiency, high efficiency and high efficiency. Therefore, the cracking of the Pvs NP problem, which is one of seven unsolved problems, is declared. The solver is specially designed for a circuit, and the major problems in the aspects of computer science and application are solved.

The invention discloses a digital circuit design for realizing large-scale SVD (Singular Value Decomposition). The design consists of three parts, namely a matrix column storage module, a parallel selection module and a Jacobian rotation calculation module. According to the scheme, the Hisenberg matrix calculation is performed on the original input matrix, so that the occupation of input storage resources is reduced. Then, through a multi-path selection (mux) mode, SVD rotation solving is carried out on eight matrix column vectors at the same time in each processing period, and the parallel calculation degree of SVD calculation is improved; and finally, point product calculation of a large-scale matrix column vector is realized through a PE processing module, and solving of a rotation angle and right singular value calculation in SVD decomposition are completed. According to the method, multiple SVD sub-algorithms are achieved through the same digital circuit design framework, the repeated utilization rate of hardware resources is increased, the SVD calculation parallelism degree is improved in a multi-path selection mode, and excessive access of a circuit to a storage unit is reduced.

The invention relates to the technical field of integrated circuit design automation (EDA), in particular to a logic circuit comprehensive optimization method based on a graph neural network, which can be applied to a logic comprehensive stage in digital circuit design. Comprising the following steps: representing a logic circuit as a directed symbol graph G = (V, E, X, S), and generating a graph data container C1; constructing a heterogeneous graph neural network model containing alternately stacked side symbol perception GraphSAGE layers and graph isomorphic network GIN layers, and packaging the model into a model container C2; multi-layer convolution is executed, multi-scale features are fused through Dense connection, and a node embedding container C3 is generated; two tasks of node-level probability prediction and graph-level classification prediction are executed in parallel, a prediction result container C4 is output, and graph-level classification outputs selection probabilities of two optimization strategies AIG and MIG; and automatically selecting an optimization strategy according to the classification probability, executing a corresponding circuit optimization algorithm, and outputting an optimized circuit C'and an optimization report.

The invention provides an incremental static time sequence analysis method based on artificial intelligence, which is suitable for circuit time delay analysis in an ECO (Error Correction Oscillation) in a confirmation stage in digital circuit design, and comprises the following steps of: extracting circuit device characteristic data related to time sequence data according to circuit time sequence data which is not subjected to ECO in an original design confirmation stage; constructing a time delay prediction model based on a neural network, and training the time delay prediction model by using the characteristic data of the circuit device to obtain model parameters; extracting feature data of an incremental design circuit device after ECO, and inputting the feature data into the trained time delay prediction model to obtain circuit time delay data of an incremental design structure and corresponding delay data and gain data; transmitting the delay data and the gain data back to a layout device and a wiring device; according to the method, the static time sequence prediction precision can be ensured, and meanwhile, the problem that an incremental design result is difficult to meet time sequence convergence is solved.

The present invention belongs to the technical field of digital circuit design optimization, and more specifically, relates to a timing-balanced large-scale integrated circuit design logic optimization method, device and computer-readable storage medium. The method includes obtaining a netlist to be optimized, taking out a combinational logic chain with more than Z cascaded combinational logic devices of the same type in the netlist; analyzing the operational characteristics of the logic gates or logic blocks in the combinational logic chain, and designing the minimum logic unit; using the minimum logic unit to optimize the combinational logic circuit structure corresponding to the combinational logic chain to compare whether the functions of the combinational logic circuit structure generated by the minimum logic unit and the combinational logic chain before optimization are completely consistent. The present invention solves the problem that the logic gate optimization has the disadvantages of increasing complexity and extending the design cycle in the timing optimization of large-scale integrated circuit design.

The application discloses a composite medium grating photosensitive detector capable of realizing global shutter in a multi-window mode and belongs to the field of digital circuit design. Grouping is performed on a pixel array of the composite medium grating photosensitive detector, N+1 sets of parallel independent column readout circuits are configured for N groups of pixel arrays, and connection switches are ingeniously arranged so that, in a multi-window opening mode, two sets of parallel column readout circuits simultaneously read out the same window, the maximum exposure time difference is greatly reduced, and further, exposure differences between different rows are eliminated through a differential circuit or a programmable gain module, so that the composite medium grating photosensitive detector can simultaneously capture picture information in the multi-window mode, instability generated during shooting is weakened, and the imaging effect of global shutter is achieved.

The present invention proposes an artificial intelligence-based incremental static timing analysis method suitable for analyzing circuit delays during the ECO phase of confirmation in digital circuit design. The method extracts circuit device characteristic data related to the timing data based on circuit timing data from the original design confirmation phase without ECO. A delay prediction model is constructed based on a neural network and trained using the circuit device characteristic data to obtain model parameters. The circuit device characteristic data of the incremental design after ECO is extracted and input into the trained delay prediction model to obtain circuit delay data of the incremental design structure, as well as corresponding delay data and gain data. The delay data and gain data are then fed back to the placer and router. This method ensures static timing prediction accuracy while solving the problem of incremental design results failing to meet timing closure requirements.

The invention is suitable for the field of chip and digital circuit design, and provides a hardware circuit, a method, equipment and a medium for floating point matrix multiplication, and the hardware circuit comprises a floating point multiplication unit which is used for carrying out multiplication on an obtained multiplier in a first standard floating point format and an obtained multiplicand in a second standard floating point format, outputting a product expressed in a first user-defined floating point format; the floating point accumulation unit is used for adding the product and an accumulation input value and outputting an accumulation sum expressed by adopting a second user-defined floating point format; and the format conversion unit is used for converting the accumulated sum of the second custom floating point format into a third standard floating point format and outputting the third standard floating point format. According to the scheme, balance can be achieved between keeping of calculation precision and limiting of hardware overhead.