33 results about "Digital circuit design" patented technology

The invention discloses a digital circuit design method and device, equipment and a medium, and relates to the technical field of digital circuits, and the method comprises the steps: determining a target type of a to-be-designed digital circuit, and collecting a first training set corresponding to the target type; each training sample in the first training set comprises an input feature item used for designing a target type of historical digital circuit and the actual result quality of the historical digital circuit, and the input feature item comprises a high-level language source code and an HLS constraint parameter; constructing an initial prediction model based on the multi-layer perceptron mixed structure, training the initial prediction model by using the first training set, and searching and optimizing the model architecture based on the network structure to obtain a target prediction model; and predicting the actual result quality corresponding to each parameter combination in a target design space of a to-be-designed digital circuit by using the model, and designing the digital circuit by using the parameter combination of which the quality meets the Pareto frontier. And predicting an accurate actual quality result by utilizing a prediction model without intermediate representation so as to carry out digital circuit design.

According to various embodiments of the present invention, a regression analysis-based circuit characteristic optimization device for digital circuit design may: receive, from the outside, information about a digital circuit to be designed, and arbitrarily set a characteristic value for at least one transistor included in the digital circuit; generate a circuit characteristic regression model by mathematically modeling the characteristic of a path included in the digital circuit on the basis of the characteristic value of the transistor included in the digital circuit; obtain an initial coefficient of the circuit characteristic regression model by applying the arbitrarily set characteristic value thereto; and obtain the improved characteristic value for the at least one transistor included in the digital circuit on the basis of the circuit characteristic regression model into which the initial coefficient has been incorporated.

The invention relates to the field of digital circuit design, and provides a method for optimizing noise influence of a synchronous switch in an IBIS model. When a traditional IBIS model measures pull-up / pull-down characteristics, it is assumed that a power supply and ground potential are constant, voltage fluctuation actually caused by a synchronous switch is ignored, and the simulation precision of a high-speed interface is reduced. By collecting current response data of a pull-up circuit and a pull-down circuit of the buffer under different power supply / ground fluctuations, pull-up and pull-down power supply modulation coefficients are calculated respectively, and the influence of power supply voltage disturbance on output current is represented. In the simulation stage, the output current in the IBIS model is dynamically modulated according to the power supply and ground potential change caused by the real-time SSN, so that the simulation is closer to the real chip behavior. The method does not need to modify a model structure, is compatible with an existing process, remarkably improves the accuracy of high-speed signal integrity analysis, is suitable for design verification of DDR, PCIe and other high-density parallel interfaces, and effectively supports the system-level power supply and signal co-simulation requirements.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The invention discloses a verification method for a digital circuit design of a large-area-array infrared image sensor, and the method comprises the steps: carrying out the analysis of a to-be-verified digital circuit design feature, and obtaining an analysis result; classifying each module in the digital circuit design to obtain a plurality of to-be-modeled modules; modeling input, output and functions of the to-be-modeled module according to an analysis result to form a plurality of universal verification modules; a plurality of universal verification modules are connected with a digital circuit to be verified according to connection requirements, a complete circuit is established, and a verification platform is formed; executing simulation based on the verification platform to obtain a simulation result; and optimizing the digital circuit design according to a simulation result. And the effect of quickly and accurately positioning the design problem is achieved.

The invention relates to the technical field of integrated circuit design, and discloses a module data generation method based on an abstract syntax tree, electronic equipment and a storage medium, and the method comprises the steps: obtaining a digital circuit design file, analyzing the digital circuit design file, and generating a corresponding abstract syntax tree; identifying a module action range contained in the abstract syntax tree, and creating a variable relation data structure corresponding to the module action range; and determining the signal association relationship between the leaf nodes, and creating the association relationship object in the variable relationship data structure based on the signal association relationship between the leaf nodes, thereby effectively avoiding the problem that the signal interaction relationship between the leaf nodes is difficult to accurately identify only depending on an abstract syntax tree. Therefore, the efficiency and the accuracy of calculating and analyzing the signal incidence relation in the module action range by electronic design automation software are improved.

The application relates to the technical field of integrated circuit design, and discloses a module data generation method based on an abstract syntax tree, an electronic device and a storage medium, the method comprising the following steps: acquiring a digital circuit design file, analyzing the digital circuit design file, and generating a corresponding abstract syntax tree; identifying a module scope contained in the abstract syntax tree, and creating a variable relationship data structure corresponding to the module scope; determining a signal correlation relationship between leaf nodes, and creating a correlation relationship object in the variable relationship data structure based on the signal correlation relationship between the leaf nodes, so that the problem that it is difficult to accurately identify the signal interaction relationship between the leaf nodes by only relying on the abstract syntax tree is effectively avoided, and the efficiency and accuracy of calculation and analysis of the signal correlation relationship in the module scope by electronic design automation software are improved.

The implementations described herein relate to non-scannable flip-flops used within scannable digital circuits. For example, one illustrative method includes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; and based on this determination, modifying the scannable digital circuit design to integrate a multiplexing function controlled by a scan enable signal into the first stage, and converting the first scannable flip-flop to a non-scannable flip-flop. The method further includes: determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within a scannable digital circuit design; and based on this determination, retaining the second scannable flip-flop in the circuit design. Corresponding methods, circuits, media, and other implementations are also disclosed.

The invention discloses a residual life prediction system and method for an aero-engine, and belongs to the technical field of life prediction and the technical field of digital circuit design, and the system comprises a multi-modal data collection module, a data preprocessing module, a working mode arbitration module, a low-power-consumption health state evaluation module and a self-adaptive neural network processing module. The multi-modal data acquisition module is connected with the data preprocessing module, the data preprocessing module is connected with the working mode arbitration module, the working mode arbitration module is connected with the low-power-consumption health state evaluation module and the adaptive neural network processing module, and the low-power-consumption health state evaluation module is connected with the adaptive neural network processing module. According to the method, the calculation precision is adaptively adjusted according to the health condition of the aero-engine, so that the limited airborne calculation capability, memory and power consumption are dealt with.

The invention relates to an excitation file generation method and device, electronic equipment and a storage medium, which are applied to the technical field of digital circuit design, and the method comprises the following steps: defining a system clock according to a clock period set by a user in a human-computer interaction interface; according to the interface information in each model file called by the human-computer interaction interface and the interface connection relationship between the model files, defining an interface and assigning a value to the assigned input interface; declaring the name of each model file and the names of the input interface and the output interface in a to-be-generated excitation file; a value set for an input interface in the model file by a user on the human-computer interaction interface is obtained and assigned to the corresponding input interface in the excitation file to be generated, the clock signal is set to be 1, and the reset signal is set to be 0; according to the simulation duration set by the user on the human-computer interaction interface, the simulation duration is set, and after the simulation duration is over, the reset signal is set to be 1. The excitation file generation efficiency and accuracy can be improved.

The invention relates to the technical field of digital circuits, in particular to a method, device and equipment for reducing peak current, a medium and a digital circuit, and the method comprises the steps: obtaining the peak moment of the maximum instantaneous peak current of a target circuit; performing static time sequence analysis on the target circuit, acquiring arrival time and required time of each path in the target circuit, and taking a difference value obtained by subtracting the arrival time from the required time as a time sequence margin; determining the path of which the time sequence margin is greater than 0 as a non-critical path; acquiring a non-critical path where a target logic gate flipped at the peak moment is located as an insertion path; the time delay units are inserted into the insertion paths, so that the target logic gates of the insertion paths are staggered in the overturning time, the total time delay D of the time delay units inserted into the insertion paths meets the condition that D is smaller than or equal to Si-delta, Si is the time sequence margin of the insertion paths, and delta is the preset safety time sequence margin. The technical scheme can reduce the peak current of the digital circuit, and is mainly used for digital circuit design.

The invention belongs to the technical field of digital circuit design, and particularly relates to a TCAM (ternary content addressable memory)-based quick matching search method, which comprises the following steps of: combining a block RAM (random access memory) and a distributed RAM to construct a TCAM; according to the length of the search word, dividing the search word into a plurality of search sub-words according to bits; according to the length of a search sub-word, inputting the search sub-word into a sub-block RAM or a sub-distributed RAM, processing results of a plurality of sub-RAMs, inputting the processed results into an encoder, and outputting a matching address by the encoder; and searching a corresponding operation in the RAM of the matched address and executing the operation. Compared with the prior art, the method has the advantages that the Block RAM (BRAM) and the LUTRAM in the FPGA are comprehensively utilized to optimize the method for dividing the search words, the BRAM and the LUTRAM are flexibly combined, the optimized composite TCAM (OC-TCAM) which is closer to or even fits the number of bits of the search words is achieved, and consumption of storage resources is greatly reduced.

The invention relates to the technical field of integrated circuit design automation (EDA), in particular to a logic circuit comprehensive optimization method based on a graph neural network, which can be applied to a logic comprehensive stage in digital circuit design. Comprising the following steps: representing a logic circuit as a directed symbol graph G = (V, E, X, S), and generating a graph data container C1; constructing a heterogeneous graph neural network model containing alternately stacked side symbol perception GraphSAGE layers and graph isomorphic network GIN layers, and packaging the model into a model container C2; multi-layer convolution is executed, multi-scale features are fused through Dense connection, and a node embedding container C3 is generated; two tasks of node-level probability prediction and graph-level classification prediction are executed in parallel, a prediction result container C4 is output, and graph-level classification outputs selection probabilities of two optimization strategies AIG and MIG; and automatically selecting an optimization strategy according to the classification probability, executing a corresponding circuit optimization algorithm, and outputting an optimized circuit C'and an optimization report.

The application discloses a composite medium grating photosensitive detector capable of realizing global shutter in a multi-window mode and belongs to the field of digital circuit design. Grouping is performed on a pixel array of the composite medium grating photosensitive detector, N+1 sets of parallel independent column readout circuits are configured for N groups of pixel arrays, and connection switches are ingeniously arranged so that, in a multi-window opening mode, two sets of parallel column readout circuits simultaneously read out the same window, the maximum exposure time difference is greatly reduced, and further, exposure differences between different rows are eliminated through a differential circuit or a programmable gain module, so that the composite medium grating photosensitive detector can simultaneously capture picture information in the multi-window mode, instability generated during shooting is weakened, and the imaging effect of global shutter is achieved.

The invention is suitable for the field of chip and digital circuit design, and provides a hardware circuit, a method, equipment and a medium for floating point matrix multiplication, and the hardware circuit comprises a floating point multiplication unit which is used for carrying out multiplication on an obtained multiplier in a first standard floating point format and an obtained multiplicand in a second standard floating point format, outputting a product expressed in a first user-defined floating point format; the floating point accumulation unit is used for adding the product and an accumulation input value and outputting an accumulation sum expressed by adopting a second user-defined floating point format; and the format conversion unit is used for converting the accumulated sum of the second custom floating point format into a third standard floating point format and outputting the third standard floating point format. According to the scheme, balance can be achieved between keeping of calculation precision and limiting of hardware overhead.

A control circuit unit includes: a target circuit unit, a plurality of detection circuit units, a plurality of local counters, a global counter, and a management circuit unit. The detection circuit units are disposed in a plurality of local areas of a target area within the control circuit unit, and the target area encompasses the target circuit unit. The detection circuit unit is used to send a first signal in response to a determination of receiving an external electromagnetic attack. The plurality of local counters update the number of recorded localized attack in response to receiving the first signal. The global counter accumulates the number of localized attacks to update the number of recorded globalized attacks. The management circuit unit issues a warning notification based on the number of globalized attacks and the number of localized attacks of each local counter.

The invention discloses a circuit fragile node identification method based on static feature fusion. The method comprises the steps of constructing a circuit basic information base; forming a standardized feature set; constructing a weighted fusion feature matrix; constructing a fragile node identification model; and determining a vulnerable node list and the like. According to the method, feature extraction and model training are carried out only depending on circuit static information, the recognition period can be greatly shortened, and a large-scale complex circuit is adapted; the method covers four static characteristics of trigger topology, bus association, a feedback loop and process attributes, fully captures inherent attributes and association characteristics of circuit nodes, ensures data integrity through submodule flattening and bus signal expansion, adopts an entropy evaluation method objective weighting and multi-model integration strategy, and improves the reliability of the circuit nodes. The accuracy and generalization ability of vulnerable node identification can be effectively improved; meanwhile, process library analysis, netlist processing and feature calculation frameworks are unified, digital circuit designs of different architectures can be adapted, and accurate fragile node reference can be provided for the initial stage of circuit reliability design.

A reconfiguration security fabric comprising a reconfigurable logic block (ReCLB) comprising a plurality of lookup tables (LUTs); one or more programmable input / output (PIO) routers comprising a plurality of multiplexers (MUXs) that determine routing of data to or from the ReCLB; a switch box that is configured to route a plurality of outputs from the plurality of LUTs to the one or more PIO routers; and a configuration bitstream that is communicatively coupled to the ReCLB, the one or more PIO routers, and the switch box, wherein functionality of the ReCLB, the one or more PIO routers, and the switch box is altered by shifting the configuration bitstream.

The present disclosure relates generally to circuits designed and manufactured utilizing first and second design rules. An integrated circuit (IC) includes a plurality of finfet cells designed utilizing digital circuit design rules to provide smaller finfet cells having reduced cell height, and an analog circuit cell structure including a first finfet cell of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells having reduced cell height provide first shorter metal tracks in one direction, and the at least one cut metal layer provides second shorter metal tracks in another direction to improve maximum electromigration current in the integrated circuit.

The invention provides a digital circuit design system, a digital circuit full-automatic design method and a related product, and the digital circuit design system converts a metal layer rule into a process parameter template represented by a coefficient of a process minimum line width unit through a process abstract interface module, so that the process migration cost is reduced. The full-automatic design method of the digital circuit can automatically start from the function description of the target digital circuit, the physical implementation result of the target digital circuit is obtained, the full-process automatic design of the chip is realized, and the design difficulty of the digital circuit is reduced.

The present technology is related to transistor synthesis optimization during the physical design stage of EDA. Aspects of the present technology introduces new ways to restructure transistor-level netlists, such as by reducing transistor count, for digital circuit designs based on the enumeration of “don't cares” of internal nets. One aspect of the present technology includes connecting internal nets with the same truth table up to don't cares without changing the functionality of the entire circuit. With an additional connection in the netlist, optimization opportunities can be identified that may remove transistors and / or improve placement, routing, and / or timing metrics. Furthermore, optimization opportunities may be further increased by (pre)computing satisfiability don't cares at the inputs of the netlist and observability don't cares at the outputs of the netlist from the environment.

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

The invention belongs to the technical field of high-speed digital circuit design, and particularly relates to a high-transmission-efficiency high-speed serial-parallel conversion circuit based on a multi-phase clock and a conversion method.The conversion circuit comprises a double-channel parallel sampling sub-circuit, a high-speed serial-parallel conversion sub-circuit, a high-speed serial-parallel conversion sub-circuit and a high-speed serial-parallel conversion sub-circuit, n / 2 groups of sampling units are used for sampling double-path data under different phase clocks, and each group obtains 2-bit continuous data; and synchronously outputting N-bit parallel data at the uniform clock edge. The serial-to-parallel converter is suitable for serial-to-parallel conversion requirements of any even number of bit widths such as 8 bits, 10 bits, 12 bits and 16 bits, and has the advantages of being high in universality, easy to implement, high in transmission efficiency, low in power consumption and the like.

The application discloses a coarse-grained reconfigurable array and a hardware modeling generation method thereof, and belongs to the field of digital circuit design and processing technology. The coarse-grained reconfigurable array comprises a processing unit array of a reconfigurable array formed by M rows and N columns of processing units, a configuration memory for temporarily storing processing unit operation configuration information, a configuration bus and an input / output interface for connecting the configuration memory and the processing units. The modeling generation method comprises generating sub-module design parameters from top to bottom and generating hardware RTL level code from bottom to top by using an input top-level hardware design parameter. The coarse-grained reconfigurable array and the hardware modeling generation method can complete agile modeling and RTL level code generation of the coarse-grained reconfigurable array, realize target redirection of a driving compilation tool by designing a hardware description intermediate representation, and greatly improve the efficiency of hardware design and software stack development of a hardware accelerator.

The application provides a divider processing method and system for specific divisors, and relates to the technical field of computer arithmetic and digital circuit design, wherein the dividend is expressed in binary form and divided into m n-bit grouped values; when the specific divisor is -1 or a factor of -1, or the divisor is +1 or a factor of +1, or the divisor is a factor of 2 raised to a power, or the divisor is a product between factors, a hardware circuit capable of realizing the division operation is constructed based on a multi-operand adder, an addition tree circuit, a shifter, a small parameter multiplier or a lookup table, so as to realize the complete divider calculation of the efficient, low-cost and synchronous output of the accurate division result for the specific divisor.

A computer-executable method for optimizing a scan chain signal line length in the design of a digital circuit using Q-learning, wherein the method comprises: Obtain (302) stem node details from the stem nodes, Optimizing (304) a connectivity of the stem nodes, Identifying (306) a best starting node and a best ending node for each of the stem nodes, Optimizing (308) child nodes in each of the parent nodes, having: Initializing (308a) a Q-table for each of the root nodes, Selecting (308b) an action based on a fixed start and end node or on the basis of an optimal start and end node, Performing (308c) the action by adding a selected node, Measuring (308d) a reward by measuring a total signal line length of a stem node tour, and Update (308e) the Q-table for each of the child nodes of a child node tour, Determine (310) that a signal line length of a full tour is less or greater than that of a nearest neighbor, Apply (312) or skip (314) a solution.

The application provides a digital circuit design system, a digital circuit full-automatic design method and related products. The digital circuit design system converts a metal layer rule into a process parameter template represented by a coefficient of a process minimum line width unit through a process abstraction interface module, thereby reducing process migration cost. The digital circuit full-automatic design method can automatically obtain a physical implementation result of a target digital circuit from a function description of the target digital circuit, realize full-flow automatic design of a chip, and reduce design difficulty of the digital circuit.

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

The application discloses a PCB structure with embedded resistance and a memory module, and relates to the technical field of high-speed digital circuit design and manufacturing. The PCB structure comprises a PCB laminated structure, the PCB laminated structure comprises a plurality of conductive layers, a dielectric layer is arranged between two adjacent conductive layers, at least one conductive layer located at the inner side is a resistance layer, a resistance is arranged on the resistance layer, at least one conductive layer located at the outermost side is a surface layer, a chip and a gold finger are arranged on the surface layer, and a first end and a second end of the resistance are electrically connected with the chip and the gold finger respectively. The application adopts the form of embedded resistance, and the area occupied by a traditional surface-mounted termination resistance element is saved on the surface of the PCB, thus valuable space is released for high-density mainboard design, and other key elements or optimized signal line wiring can be arranged.