8 results about "Digital circuit design" patented technology

According to various embodiments of the present invention, a regression analysis-based circuit characteristic optimization device for digital circuit design may: receive, from the outside, information about a digital circuit to be designed, and arbitrarily set a characteristic value for at least one transistor included in the digital circuit; generate a circuit characteristic regression model by mathematically modeling the characteristic of a path included in the digital circuit on the basis of the characteristic value of the transistor included in the digital circuit; obtain an initial coefficient of the circuit characteristic regression model by applying the arbitrarily set characteristic value thereto; and obtain the improved characteristic value for the at least one transistor included in the digital circuit on the basis of the circuit characteristic regression model into which the initial coefficient has been incorporated.

The implementations described herein relate to non-scannable flip-flops used within scannable digital circuits. For example, one illustrative method includes: determining that a first propagation delay of a first stage of combinational logic is greater than a delay threshold, the first stage preceding a first scannable flip-flop within a scannable digital circuit design; and based on this determination, modifying the scannable digital circuit design to integrate a multiplexing function controlled by a scan enable signal into the first stage, and converting the first scannable flip-flop to a non-scannable flip-flop. The method further includes: determining that a second propagation delay of a second stage of combinational logic is less than a delay threshold, the second stage preceding a second scannable flip-flop within a scannable digital circuit design; and based on this determination, retaining the second scannable flip-flop in the circuit design. Corresponding methods, circuits, media, and other implementations are also disclosed.

The present technology is related to transistor synthesis optimization during the physical design stage of EDA. Aspects of the present technology introduces new ways to restructure transistor-level netlists, such as by reducing transistor count, for digital circuit designs based on the enumeration of “don't cares” of internal nets. One aspect of the present technology includes connecting internal nets with the same truth table up to don't cares without changing the functionality of the entire circuit. With an additional connection in the netlist, optimization opportunities can be identified that may remove transistors and / or improve placement, routing, and / or timing metrics. Furthermore, optimization opportunities may be further increased by (pre)computing satisfiability don't cares at the inputs of the netlist and observability don't cares at the outputs of the netlist from the environment.

The application provides a divider processing method and system for specific divisors, and relates to the technical field of computer arithmetic and digital circuit design, wherein the dividend is expressed in binary form and divided into m n-bit grouped values; when the specific divisor is -1 or a factor of -1, or the divisor is +1 or a factor of +1, or the divisor is a factor of 2 raised to a power, or the divisor is a product between factors, a hardware circuit capable of realizing the division operation is constructed based on a multi-operand adder, an addition tree circuit, a shifter, a small parameter multiplier or a lookup table, so as to realize the complete divider calculation of the efficient, low-cost and synchronous output of the accurate division result for the specific divisor.

A computer-executable method for optimizing a scan chain signal line length in the design of a digital circuit using Q-learning, wherein the method comprises: Obtain (302) stem node details from the stem nodes, Optimizing (304) a connectivity of the stem nodes, Identifying (306) a best starting node and a best ending node for each of the stem nodes, Optimizing (308) child nodes in each of the parent nodes, having: Initializing (308a) a Q-table for each of the root nodes, Selecting (308b) an action based on a fixed start and end node or on the basis of an optimal start and end node, Performing (308c) the action by adding a selected node, Measuring (308d) a reward by measuring a total signal line length of a stem node tour, and Update (308e) the Q-table for each of the child nodes of a child node tour, Determine (310) that a signal line length of a full tour is less or greater than that of a nearest neighbor, Apply (312) or skip (314) a solution.

The application provides a digital circuit design system, a digital circuit full-automatic design method and related products. The digital circuit design system converts a metal layer rule into a process parameter template represented by a coefficient of a process minimum line width unit through a process abstraction interface module, thereby reducing process migration cost. The digital circuit full-automatic design method can automatically obtain a physical implementation result of a target digital circuit from a function description of the target digital circuit, realize full-flow automatic design of a chip, and reduce design difficulty of the digital circuit.

The application discloses a PCB structure with embedded resistance and a memory module, and relates to the technical field of high-speed digital circuit design and manufacturing. The PCB structure comprises a PCB laminated structure, the PCB laminated structure comprises a plurality of conductive layers, a dielectric layer is arranged between two adjacent conductive layers, at least one conductive layer located at the inner side is a resistance layer, a resistance is arranged on the resistance layer, at least one conductive layer located at the outermost side is a surface layer, a chip and a gold finger are arranged on the surface layer, and a first end and a second end of the resistance are electrically connected with the chip and the gold finger respectively. The application adopts the form of embedded resistance, and the area occupied by a traditional surface-mounted termination resistance element is saved on the surface of the PCB, thus valuable space is released for high-density mainboard design, and other key elements or optimized signal line wiring can be arranged.

The application is suitable for the field of chip and digital circuit design, and provides a hardware circuit, method, equipment and medium for floating point matrix multiplication, wherein the hardware circuit comprises: a floating point multiplication unit, which is used for multiplying a first standard floating point format multiplier and a second standard floating point format multiplicand, and outputs a product in a first self-defined floating point format; a floating point accumulation unit, which is used for adding the product and an accumulation input value, and outputs an accumulation sum in a second self-defined floating point format; and a format conversion unit, which is used for converting the accumulation sum in the second self-defined floating point format into a third standard floating point format and then outputting. The scheme can balance between maintaining calculation accuracy and limiting hardware overhead.