16 results about "Register transfer" patented technology

According to the storage and calculation integrated structure, the end-side AI reasoning method, the medium and the terminal provided by the invention, the system performance and energy efficiency are improved, the storage delay and bandwidth are optimized, the serial-parallel conversion overhead is saved, the cache management overhead is avoided, and the system performance and energy efficiency are improved through the direct interconnection of the storage group and the AI calculation module, the register transfer and the parallel data handling mechanism. The power consumption and the area of prefetching logic are saved, the complexity of a storage system and data handling is reduced, and the storage handling is lightweight; in the process of executing the distributed AI reasoning operation, data carrying and shaping can be synchronously carried out, the data synchronization parallelism degree is improved, the data supply rate is matched with the calculation rate, idle waiting of an AI calculation unit is reduced, and the throughput and the energy efficiency ratio of the system are improved.

An electronic device is provided for securing and desynchronizing register transfers as a mitigation strategy to side channel attacks that employ power analysis profiling, whereby leakage information produced as a result of register switching at the bit-level, by way of random delay cell insertions, is decorrelated from actual power consumption. The technical effect of the solution constructively produces overlapping of current power profiles / signatures, maximally spanning across bit value profiles of a register, which when analyzed from a Hamming Weight or Distance model introduces a wider time-spread of resulting current power profiles thereby impeding deep learning of the transistor switching / flipping state behavior, and consequently disrupting efficacy of profile / signature matching / mapping of transistor state changes characteristic of a traditional power analysis side channel attack. Other embodiments are disclosed

The embodiment of the invention discloses an information interaction method and device. According to the embodiment of the invention, after a congestion hotspot analysis instruction is received, congestion hotspot analysis is carried out on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hotspot, and a to-be-modified code statement is determined in a register transfer-level code according to the combinational logic congestion hotspot; and modifying each to-be-modified code statement into a target code statement, and regenerating a target gate-level netlist according to the modified register transfer-level code. Wherein the to-be-modified code statement only supports to be converted into a combinational logic structure in the logic synthesis process, and the target code statement supports to be converted into a multiplexer structure in the logic synthesis process. Therefore, the embodiment of the invention can support a user to analyze and solve the wiring congestion problem in the logic synthesis process, so that the chip design efficiency is improved, and the negative effects of the wiring congestion problem solving process on the power consumption, the performance and the area of the formed chip are reduced.

Techniques are disclosed that relate to fusing operations for execution of certain instructions. A processor may include a first execution circuit, of a first type, coupled to a first register file, a second execution circuit, of a second type, coupled to a second register file and a load / store circuit coupled to the first and second register files. The load / store circuit includes an issue port configured to receive an instruction operation for execution, a memory execution circuit configured to execute memory access operations, and a register transfer execution circuit. The register transfer execution circuit is configured to execute instruction operations specifying data transfer from the first register file to the second register file and an operation to be performed using the data, and the load / store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.

The present disclosure relates to a clock signal monitoring unit comprising first, second and third flip-flops, first and second XOR gates and a delay element being functionally interconnected in a specific way. The proposed clock signal monitoring unit can detect both a rising edge glitch and a falling edge glitch. In this way there is provided an area saving device, which does not require any trimming efforts, which can save a lot of space and time. Furthermore, the clock signal monitoring unit can have low electric power consumption because it uses as few as four clocked flip-flops implemented via Register Transfer Logic having an already tuned delay element. This makes it useful for designs that use both edges of the clock for correct operation.

Techniques are provided for routing qubit data. For example, one or more embodiments described herein can include a computer-implemented method for training a quantum controller fast path interface that can control the routing of the qubit data. The computer-implemented method can include training, by a system operably coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and a conditional engine by adjusting a delay value such that an equalized clock domain is characterized by a direct register-to-register transfer mode.

A computer-implemented method for inserting clock-gating in a register-transfer level (RTL) design is provided. The computer-implemented method includes flattening the RTL design, identifying modules and state elements in the RTL design, computing a clock-gating expression for each of the state elements of the RTL design, selecting terms of the clock-gating expression for each one of the state elements that is traceable to signals in a same one of the modules as the one of the state elements, determining which clock-gating terms are equivalent to those of other state elements in the RTL design, clustering state elements with equivalent clock-gating terms into clusters and inserting clock-gating logic, which equates to the equivalent clock-gating terms, into the RTL design for each cluster.

The invention belongs to the technical field of chip design, and mainly provides a chip verification method and device, electronic equipment and a computer program product, and the method comprises the steps: carrying out the function verification of a joint test action group in an electronic design automation simulation stage, and obtaining a verification result of a chip in the electronic design automation simulation stage, the function verification time of the joint test action group of the chip is advanced from a field programmable gate array verification stage (i.e., a prototype test and verification stage) to an electronic design automation simulation stage (i.e., a register transfer stage verification stage), and the function verification of the joint test action group of the chip can be realized in the electronic design automation simulation stage. According to the method, problems possibly existing in chip design are found in advance, some problems possibly existing in the chip design are prevented from being left in a field programmable gate array verification stage, and when the problems exist in the chip design, register transmission level codes with the problems can be directly positioned, so that the problems are more explicit, and the problem solving efficiency is improved.

The invention discloses a time sequence driving clock tree synthesis method and product based on key node pairs, and the time sequence driving clock tree synthesis method comprises the steps: constructing an initial clock tree, extracting a plurality of register transmission paths meeting the allowance requirement based on the initial clock tree, constructing a key node pair file according to the plurality of register transmission paths, generating a starting node mapping table and an ending node mapping table for the file according to the key nodes; dividing the plurality of node clusters in the initial clock tree into non-key node clusters and key node clusters based on the initial node mapping table and the termination node mapping table; and respectively processing the non-key node cluster and the key node cluster in the initial clock tree to obtain a final optimized clock tree. The time sequence driven clock tree synthesis method aims to construct a time sequence driven balance clock tree while ensuring time sequence convergence.

The application provides a storage-computation integrated device, an end-side AI inference method, a medium and a terminal. Through direct interconnection of a storage group and an AI computation module, register transfer and parallel data carrying mechanism, system performance and energy efficiency are improved, storage delay and bandwidth are optimized, serial-parallel conversion overhead is saved, cache management overhead is avoided, power consumption and area of prefetch logic are saved, complexity of the storage system itself and data carrying is reduced, and storage carrying is lightweighted. In the process of executing a distributed AI inference operation, data carrying and shaping can be synchronously performed, data synchronization parallelism is improved, data supply rate is matched with computation rate, idle waiting of an AI computation unit is reduced, and system throughput and energy efficiency ratio are improved.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The invention relates to the technical field of embedded system development and verification, and discloses a joint simulation system and method for a heterogeneous multi-core processor. The simulation module is configured to execute processor multi-core architecture simulation, multi-core parallel simulation, memory system layered modeling, peripheral and interface simulation and debugging and performance analysis; the programmable logic subsystem simulation module is configured to provide a multi-precision modeling framework and a dynamic reconstruction mechanism, the multi-precision modeling framework comprises a behavior-level model, a register transfer-level model and a hardware-in-the-loop simulation model, and the dynamic reconstruction mechanism supports model hot plugging and parameter adjustment during operation; and the interaction module is configured to execute data interaction, synchronization and joint debugging of the processor subsystem simulation module and the programmable logic subsystem simulation module. The method is suitable for software and hardware collaborative development and verification of the heterogeneous computing platform.

The present invention discloses a mixed digital-analog simulation method and system for a decoding module based on the V‑ams language. The simulation method includes the following steps: powering on an analog circuit and performing signal initialization on a decoding circuit of a chip under test; driving an advanced peripheral bus to configure registers; using a data file for stimulation and extracting data; performing data conversion on each channel signal to convert it into two differential signals with a phase difference of 180°; inputting the differential signal into a register transfer stage of an analog circuit for processing; the register transfer stage of the analog circuit processes the data and then outputs it to a register transfer stage of a digital circuit for decoding; collecting and transmitting data to a system control module; performing data comparison and displaying the results. The present invention realizes the joint simulation of digital and analog circuits, ensuring the consistency of the working timing of the analog and digital circuits.

Techniques are disclosed that relate to fusing operations for execution of certain instructions. A processor may include a first execution circuit, of a first type, coupled to a first register file, a second execution circuit, of a second type, coupled to a second register file and a load / store circuit coupled to the first and second register files. The load / store circuit includes an issue port configured to receive an instruction operation for execution, a memory execution circuit configured to execute memory access operations, and a register transfer execution circuit. The register transfer execution circuit is configured to execute instruction operations specifying data transfer from the first register file to the second register file and an operation to be performed using the data, and the load / store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.

A timing-driven clock tree synthesis method and product based on key node pairs, the timing-driven clock tree synthesis method comprising: constructing an initial clock tree; extracting multiple register transfer paths satisfying a margin requirement based on the initial clock tree; constructing a key node pair file according to the multiple register transfer paths; and generating a start node mapping table and a termination node mapping table according to the key node pair file; dividing multiple node clusters in the initial clock tree into non-key node clusters and key node clusters based on the start node mapping table and the termination node mapping table; and processing the non-key node clusters and the key node clusters in the initial clock tree respectively to obtain a final optimized clock tree. The timing-driven clock tree synthesis method aims to ensure timing convergence while constructing a timing-driven balanced clock tree.

The invention discloses a test vector verification method and device and a storage medium. The verification method comprises the steps of obtaining a simulation environment for verifying a to-be-tested chip; in the simulation environment, adding a multiplexer to a top layer port of the chip model to be tested; during the invalid level period of the enable signal of the multiplexer, providing a drive signal of a register transfer stage for the to-be-tested chip model through the multiplexer to obtain a test vector; providing a test vector for the to-be-tested chip model through the multiplexer in an effective level period of the enable signal of the multiplexer so as to obtain a simulation waveform; and comparing the simulation waveform with the expected waveform, judging whether the test vector is correct or not according to a comparison result, and judging that the test vector is correct under the condition that the simulation waveform is consistent with the expected waveform. By multiplexing the simulation environment, the consumption of time cost and labor cost for establishing the simulation environment is reduced, and the test efficiency of the wafer is improved.