5 results about "Register transfer" patented technology

The present disclosure relates to a clock signal monitoring unit comprising first, second and third flip-flops, first and second XOR gates and a delay element being functionally interconnected in a specific way. The proposed clock signal monitoring unit can detect both a rising edge glitch and a falling edge glitch. In this way there is provided an area saving device, which does not require any trimming efforts, which can save a lot of space and time. Furthermore, the clock signal monitoring unit can have low electric power consumption because it uses as few as four clocked flip-flops implemented via Register Transfer Logic having an already tuned delay element. This makes it useful for designs that use both edges of the clock for correct operation.

Techniques are provided for routing qubit data. For example, one or more embodiments described herein can include a computer-implemented method for training a quantum controller fast path interface that can control the routing of the qubit data. The computer-implemented method can include training, by a system operably coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and a conditional engine by adjusting a delay value such that an equalized clock domain is characterized by a direct register-to-register transfer mode.

The application provides a storage-computation integrated device, an end-side AI inference method, a medium and a terminal. Through direct interconnection of a storage group and an AI computation module, register transfer and parallel data carrying mechanism, system performance and energy efficiency are improved, storage delay and bandwidth are optimized, serial-parallel conversion overhead is saved, cache management overhead is avoided, power consumption and area of prefetch logic are saved, complexity of the storage system itself and data carrying is reduced, and storage carrying is lightweighted. In the process of executing a distributed AI inference operation, data carrying and shaping can be synchronously performed, data synchronization parallelism is improved, data supply rate is matched with computation rate, idle waiting of an AI computation unit is reduced, and system throughput and energy efficiency ratio are improved.

The invention relates to the technical field of embedded system development and verification, and discloses a joint simulation system and method for a heterogeneous multi-core processor. The simulation module is configured to execute processor multi-core architecture simulation, multi-core parallel simulation, memory system layered modeling, peripheral and interface simulation and debugging and performance analysis; the programmable logic subsystem simulation module is configured to provide a multi-precision modeling framework and a dynamic reconstruction mechanism, the multi-precision modeling framework comprises a behavior-level model, a register transfer-level model and a hardware-in-the-loop simulation model, and the dynamic reconstruction mechanism supports model hot plugging and parameter adjustment during operation; and the interaction module is configured to execute data interaction, synchronization and joint debugging of the processor subsystem simulation module and the programmable logic subsystem simulation module. The method is suitable for software and hardware collaborative development and verification of the heterogeneous computing platform.

A timing-driven clock tree synthesis method and product based on key node pairs, the timing-driven clock tree synthesis method comprising: constructing an initial clock tree; extracting multiple register transfer paths satisfying a margin requirement based on the initial clock tree; constructing a key node pair file according to the multiple register transfer paths; and generating a start node mapping table and a termination node mapping table according to the key node pair file; dividing multiple node clusters in the initial clock tree into non-key node clusters and key node clusters based on the start node mapping table and the termination node mapping table; and processing the non-key node clusters and the key node clusters in the initial clock tree respectively to obtain a final optimized clock tree. The timing-driven clock tree synthesis method aims to ensure timing convergence while constructing a timing-driven balanced clock tree.