93 results about "Test vector" patented technology

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention relates to the technical field of chip test vector intelligent generation scheme design, in particular to a failure analysis-oriented chip test vector intelligent generation method and system. The method comprises the following steps: acquiring a chip design netlist, a fault model and a known failure mode; analyzing potential design or manufacturing defects based on the information; and according to an analysis result, a targeted test vector capable of effectively exciting and isolating potential defects is automatically generated. The system comprises a corresponding input module, an analysis module and a generation module. According to the method, the design information, the fault model and the historical failure mode are intelligently fused, automatic and precise generation of the test vector is achieved, and the defects that a traditional method is insufficient in test coverage rate, low in failure positioning efficiency and limited in automation degree are overcome. According to the method, the test completeness and the failure analysis efficiency can be remarkably improved, the dependence on artificial experience is reduced, and an efficient technical means is provided for guaranteeing the reliability of the chip.

A method of method of classifying data is disclosed. The method comprises manipulating quantum states of qubits of a quantum computing device based on a first copy of a test vector, a second copy of the test vector, a first training vector and a second training vector, so as to load a modified first copy of the test vector, a modified second copy of the test vector, a modified first training vector and a modified second training vector onto the quantum computing device, wherein the magnitude of the angle between the modified first copy of the test vector and the modified first training vector is equal to the magnitude of the angle between the first copy of the test vector and the first training vector, and where the magnitude of the angle between the modified second copy of the test vector and the modified second training vector is equal to the magnitude of the angle between the second copy of the test vector and the second training vector. The method also comprises performing quantum interference between the modified first copy of the test vector and the modified second copy of the test vector, and the modified first training vector and the modified second training vector, to provide modified quantum states of the qubits, performing a measurement on one or more of the qubits, and classifying the test vector based on the measurement.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The invention relates to the technical field of data storage, and discloses a method and system for optimizing test data collected by a memory chip based on machine learning, and the method comprises the steps: collecting original test data from a test platform of a to-be-tested memory chip; constructing a convolutional neural network model, learning a mapping relationship between test data features and memory defects through the convolutional neural network model, training the convolutional neural network model through the collected original test data, optimizing parameters of the convolutional neural network model according to a training result through a back propagation algorithm, and obtaining memory defects through the optimized parameters. The performance of the convolutional neural network model tends to be stable; converting a parameter vector output by the convolutional neural network model into a test vector executable by ATE; and taking the generated test vector as a new training sample, feeding back the new training sample to an original test data updating data set, and iteratively training and optimizing the convolutional neural network model. According to the invention, intelligentization of the test process is realized, and hidden defects sensitive to voltage and time sequence can be effectively captured.

This application relates to the field of simulation verification technology, and specifically to a simulation verification management and control method, apparatus, computing device, and storage medium. The method specifically involves: generating a regression test case list for simulation verification based on functionally decomposed test points; the regression test case list includes classification information based on test vectors to categorize regression test cases; performing simulation regression based on the regression test case list to obtain regression records; analyzing the regression records to obtain analysis results; the analysis results include at least one of the following: regression status, failed test case annotation, test case coverage, convergence status, and simulation resource consumption status; and managing simulation verification based on the analysis results. This application embodiment, by performing simulation verification based on test points and analyzing regression records, allows for quantitative management of verification progress, timely supplementation of test cases, and objective and accurate evaluation of module convergence status, which is beneficial for project convergence and enables comprehensive management of simulation verification projects.

This disclosure provides a chip testing system, method, and apparatus. The system includes: an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring a mode based on rate mode configuration information to determine the target number of channels; and generating a test vector for each channel based on the test instruction sequence identifier; and a test signal output module for performing signal conversion processing on the test vectors to generate a target test signal to complete the chip testing.

A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

The application provides a method for generating a test vector for testing a memory, wherein the method comprises generating a table, the table comprising a functional area in column form and a cycle period in row form, the functional area comprising an assignment area, an operation change area and a cycle jump area, the assignment area completing assignment of different registers of the memory, the operation change area defining whether different registers represented by a current row need to perform operation change when executing a next cycle, and the cycle jump area defining a position of different registers represented by the current row when executing the next cycle and a cycle number; and generating the test vector by using the table. The application adopts a table filling type for generating the test vector, and the whole process only needs to fill corresponding information in the table, so that the operation is simple and convenient, and the table type test vector has strong intuitiveness and good readability.

This application relates to a power estimation system. A method for power estimation for integrated circuit design includes loading a test vector into a first sequence of flip-flops in scan mode, evaluating the test vector in scan mode and saving the results of the evaluation in a second sequence of flip-flops, reading the results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vector is received from an automatic test pattern generator.

The invention discloses a micro-grid energy storage multi-stage economic dispatching method, system and device based on differential evolution and a storage medium, solves the problem of how to improve micro-grid energy storage dispatching efficiency, and belongs to the field of power system operation and control. Comprising the following steps: generating a forced charging baseline instruction of which the system net power accords with a photovoltaic surplus period threshold; setting a power upper limit to initialize population individuals of a differential evolution (DE) algorithm, and generating a test vector; superposing the forced charging baseline instruction and the test vector to synthesize a preliminary attempt power, correcting a capacity boundary exceeding a capacity constraint, and outputting a first correction power; superposing the first corrected power and the system net power to synthesize a system net load, and outputting second corrected power when the corrected system net load is greater than a power boundary of a threshold value; constructing a high-fidelity objective function to execute DE optimization, and outputting an optimal individual to perform microgrid energy storage scheduling control; according to the method, the nonlinear battery life loss and the refined peak-valley arbitrage economy are taken into consideration under the condition that the physical operation safety of the bottom layer is guaranteed.

This invention discloses a flexible scheduling method, system, and application for UPMS (Upright Manufacturing System) workshops based on an improved differential evolution algorithm. The method includes: establishing an independent parallel machine scheduling model with sequentially dependent mold-changing time as the objective of minimizing the maximum completion time; using real-valued vector encoding and decoding it into a scheduling scheme through the maximum position value rule; performing mutation and crossover operations of the differential evolution algorithm on the generated test vectors, with optimizations including load balancing optimization based on destruction and reconstruction and mold-changing optimization based on sequential smoothing; finally, updating the population and outputting the optimal scheduling scheme. This invention significantly reduces sequentially dependent mold-changing time, achieves dual optimization of load balancing and mold-changing cost, and improves solution accuracy and efficiency, making it particularly suitable for discrete manufacturing workshops such as textile printing and dyeing, and injection molding.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.

The application relates to a test vector-free integrated circuit product testing method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: for a target test item which belongs to a target integrated circuit product and depends on a test vector, acquiring a functional test case of the target test item, and storing all the functional test cases in a storage module; determining a current test item to be tested of the target integrated circuit product; judging whether the current test item to be tested is the target test item which depends on the test vector, if yes, calling the target functional test case from the storage module, testing the target integrated circuit product through the target functional test case, and obtaining a test result of the target integrated circuit product; and determining whether the current test item to be tested passes the test according to the test result. Thus, the test of the test item lacking the test vector can be realized under the condition that the integrated circuit product manufacturer is unwilling to provide or unable to provide the test vector.

The invention discloses a fault simulation result processing method and device and computing equipment, and the method comprises the steps: respectively injecting a plurality of fault test vectors into a chip simulation model for fault simulation processing, and obtaining a plurality of simulation reports; determining at least two to-be-merged simulation reports in the plurality of simulation reports; detecting whether a target fault point with a plurality of different detection results exists or not based on the at least two to-be-merged simulation reports; if so, screening out a target detection result of the target fault point from a plurality of detection results of the target fault point recorded by the plurality of simulation reports to be merged; and according to the target detection result of the target fault point and the detection results of other fault points, combining to obtain a target simulation report. Through the above mode, under the condition that a plurality of fault test vectors are used for fault simulation, the detection results in a plurality of simulation reports can be automatically combined, the problem that manual search and manual calculation are needed is avoided, and the efficiency of fault simulation processing is improved.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

The present invention relates to a method for optimizing the execution of the generation of a crystal-dilithium post-quantum digital signature a for a message M using a private key sk, the digital signature generation comprising: a) generating a polynomial masking vector y having coefficients less than a second predetermined value y1; b) calculating a first polynomial vector w=Ay; c) determining a second polynomial vector w1 and a third polynomial vector w0; d) generating a challenge c based on the message and the second polynomial vector w1; and e) forming a repudiation test comprising testing whether a test vector generated from the vector, the challenge and the private key satisfies a predetermined condition, whereby if the condition is not met, restarting the signature generation from step a); otherwise, generating a signature, wherein steps a), b), c), d), and e) are repeated until the condition is met.

The application discloses a signal processing combination performance verification system based on DSP communication test, relates to the real-time test technical field of a digital signal processor, and specifically comprises: a homomorphism copying module, a slot injection module and a performance judgment module; the dynamic configuration parameters of a current DSP operation core are captured in real time through hardware sniffing of a bus, and the dynamic configuration parameters are mirrored to shadow registers; a peek unit is used to identify the bubble period of a pipeline through prediction logic; at the moment when the main computing unit is in a waiting period, the operation of the shadow register group is enabled by hardware, a preset characteristic test vector is input into a computing engine, and a shadow operation is completed; the real-time data flow of a main path and the reference data flow of a shadow path are compared in time domain and frequency domain by a hardware comparison array, the second derivative of a response time delay is calculated, a comprehensive performance factor is output, online verification of the combination performance of a DSP signal processing is realized, fault types can be accurately distinguished, and the reliability and maintainability of the system are improved.

The invention discloses an integrated chip micromodule distributed temperature real-time monitoring method, which belongs to the field of semiconductor device degradation monitoring, and comprises the following steps: extracting an integrated chip micromodule distributed temperature map; modeling for mapping the actual working temperature through a micro-module test vector; the invention discloses a method for realizing distributed temperature real-time monitoring and power consumption early warning of an integrated chip based on ATE. According to the method, the integrated chip is not invaded, and the performance and the time sequence of the integrated chip micromodule are not influenced; a device distributed temperature value which is difficult to obtain or obtained through an intrusive temperature sensor is measured through a test vector, and a device temperature and a transient power consumption value are obtained by using an artificial intelligence model; the problems of additional time sequence path interference, additional cost or power consumption caused by an intrusive temperature sensor to the design of the integrated chip are effectively solved, the heat distribution condition of the micro-module in the integrated chip can be fed back online in real time, and finally the current degradation level of a device is measured.

This application relates to the field of integrated circuit technology and provides a physical IP verification device, verification method, computer equipment, and medium. The physical IP verification device includes: a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. This allows for the consideration of different simulation needs and scenarios, such as accelerating simulation efficiency and integrating verification. It supports protocol consistency verification, physical layer subsystem-level functional verification completeness, and standardized protocol verification. It provides a rich set of test vectors to meet the interfacing test scenarios and completeness verification needs of different layers, including the transaction layer, data link layer, and physical layer. It supports richly layered debugging interfaces and debugging methods, different physical interface versions and interface data bus widths, and also supports hierarchical and fine-grained low-power management.

The invention discloses a hardware self-test control method, device, system and equipment and a medium. The method comprises the following steps: firstly, obtaining an individual calibration parameter and a first multi-dimensional environment parameter of hardware; calibrating the first multi-dimensional environment parameter according to the individual calibration parameter to obtain a first calibration environment parameter; inputting the first calibration environment parameter into the environment-frequency division mapping model to obtain a first target frequency division coefficient in the current environment; selecting a corresponding test vector set according to the first target frequency division coefficient to carry out hardware self-test to obtain a self-test result; and finally, generating graded early warning information and fault positioning information according to a self-test result. The frequency division coefficient configuration precision can be improved, the test misjudgment rate is reduced, and the test efficiency and safety are improved.

The application discloses a complex electronic hardware compliance verification test system based on simulation vector multiplexing, and belongs to the technical field of electronic hardware testing.The simulation test vector generation module is configured to receive a hardware design requirement document, establish a requirement pin mapping table, encapsulate a simulation excitation vector with timing annotation, generate a test vector file, and design a high-fidelity verification module board card module, so that the board card module is kept consistent with a target product board card, the measured hardware circuit is connected, preset test points monitor signals of the measured hardware circuit, the core control module includes a timing reconstruction engine, the test vector file is read, an actual output vector file is generated, the actual output vector file is verified by an automatic verification closed loop module, a test report including a compliance evidence chain is generated, efficient simulation vector multiplexing can be realized, simulation and actual measurement timing behaviors are consistent and aligned, synchronous linkage of excitation application and response acquisition is realized, and verification efficiency and checking accuracy are improved.

The application is a path planning method and device combining adaptive difference and local search optimization, comprising: initializing an evolution population; taking each individual in the current evolution population as a target vector, performing adaptive mutation, crossover and boundary constraint processing to generate a test vector corresponding to each target vector; calculating the corresponding fitness value respectively, updating the current preferred individual according to the individual corresponding to the smaller value in the fitness value; performing local fine search based on the preferred individual to obtain a fine optimization individual, updating the current evolution population based on the fine optimization individual; cyclically executing the steps of generating a test vector to local fine search until the iteration termination condition is met, and determining and outputting the optimal candidate path corresponding to the multi-dimensional vector of the corresponding last optimal individual of the current evolution population. Through the method provided by the application, a more optimal optimal candidate path is planned in a complex dynamic and static obstacle environment in terms of length, smoothness and safety.

The invention provides a test circuit and a circuit test method, the test circuit and the circuit test method are applied to a to-be-tested circuit, the to-be-tested circuit comprises a pseudo-random vector generator and K scan chains, the test circuit comprises a random constant generator, a low power consumption controller and a first multiplexer, and the random constant generator is used for generating a first test vector; the low-power-consumption controller is used for generating a low-power-consumption control signal, and the low-power-consumption control signal is used for setting each scanning chain as a low-power-consumption scanning chain or a non-low-power-consumption scanning chain according to the correlation degree between each scanning chain in the K scanning chains and a fault in the circuit to be tested; the first multiplexer is used for inputting a first test vector for the first scan chain under the condition that the first scan chain is a low-power-consumption scan chain, or inputting a second test vector for the first scan chain under the condition that the first scan chain is a non-low-power-consumption scan chain, and the second test vector is a random binary sequence. The test circuit provided by the invention can reduce the power consumption of circuit test.

Disclosed is a fail-closed conformance control layer for machine-assisted decision artifacts. The system generates replay-verifiable receipts that commit to a canonical artifact digest, evidence and snapshot identifiers, assumptions, toolchain identifiers, and a policy pack identifier and policy version digest. A deterministic validator evaluates a receipt under the versioned policy pack to output PASS, FAIL, or HOLD with reason codes from a reason-code registry, including time-stamped modeled-variability codes. Downstream side effects are gated in a control path and permitted only on PASS; otherwise they are withheld or routed to remediation or human review. The system may emit portable conformance packs and revalidate receipts over time to detect drift and manage a certification lifecycle. Conformance suites with deterministic test vectors and expected validator outputs may certify validator implementations by issuing signed conformance certificates and publishing a certificate or certificate digest to a verifiable certificate registry for independent verification and procurement acceptance testing.

The invention relates to the technical field of circuit testing, in particular to a chip testing method and system and a storage medium. The chip testing method comprises the following steps: translating symbol information such as a channel name and a test vector label into index values in a compiling period / loading period; and an array data structure based on the indexes is initialized in advance. When the test is executed, the channel object or the test vector address can be directly obtained through a time group index operation instead of analyzing the symbols through character string search and hash calculation during operation in the prior art. In this way, a large amount of redundant runtime calculation is eliminated, the execution time of each test instruction is greatly shortened, and the test efficiency is improved.