985 results about "Test vector" patented technology

A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

The invention relates to the field of SoC chips, in particular to a method and a device for SoC chips, which is used for solving the problem that the occurrence of random vectors and control difficulty are increased because each verification needs to be compiled again when different functions of the same SoC chip are verified in the prior art. The method of the embodiment of the invention comprises the following steps: setting a configuration file of an SoC chip, wherein the configuration file comprises the basic information of the SoC chip and constraint conditions of modules in the SoC chip; according to received instructions, determining the modules referring to the functions of the SoC chip which need to be verified; according to the basic information, the constraint conditions of the determined modules and module function data in the instructions, generating a random test vector; and according to the random test vector, verifying the SoC chip. The embodiment of the invention has the advantages of reducing the complexity of constructing verification systems and maintenance difficulty, increasing the reusability of verification components, lowering verification difficulty and saving time.

Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or “defect artifacts,” that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.

A technique for effectively attenuating EMI noise, which is generated from the electric power system of semiconductor devices, is described. In accordance with the technique, a power supply netlist with an additional electric current source(s) is generated by adding block power supply current waveform data, as extracted from test vector data and a block netlist, to the power supply netlist as extracted from the layout data of the circuit under analysis. A circuit simulation of the power supply netlist with an additional electric current source(s) is then performed in order to calculate power supply current/voltage waveform data. Furthermore, current/voltage spectral data is calculated by the Fourier transformation of the power supply current/voltage waveform data followed by displaying the current/voltage spectral data as the result of the Fourier transformation.

The invention provides a test pattern-based testing system for realizing a functional test on a digital integrated circuit. The functional test is mainly used for testing logical functions of a chip under a certain timing sequence, and a basic principle is that the chip is excited by means of test patterns and whether the response of the chip is consistent with expected response is observed. The functional test can cover failure models of extremely high proportion logic circuits. A debugging technology supported one-step testing system comprises two parts, namely test pattern file conversion software applied to a personal computer (PC) and a digital integrated circuit chip testing machine, wherein the digital integrated circuit chip testing machine consists of architectures of a central processing unit (CPU) and a field programmable gate array (FPGA); the CPU is used for storing and converting pattern files, controlling the testing process, communicating with a host, and the like. A pattern controlling logic circuit is realized by an FPGA, the waveform generation, the control of Pattern random access memory (RAM) and sampling control are finished through the FPGA, and a drive and a comparator are controlled so as to test and control a tested object.

Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each intelligence wrapper contains control logic to decode a command from the processor. Each intelligence wrapper contains logic to execute a set of test vectors on a bounded memory. The processor sends a command based self-test to each intelligence wrapper at a first clock speed and the control logic executes the operations associated with that command at a second clock speed asynchronous with the first speed. The processor loads the command containing representations of a march element and data to one or more of the intelligence wrappers via a serial bus.

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

A digital system having multiple clock domain, each including at least one edge-triggered device, such as a flip-flop, is structured to be submitted to scan testing. Each data path from one clock domain to another includes a latch that is operated by a test clock. During scan testing, when the digital system is logically reconfigured to form one or more scan chains for receiving a test vector, the latches are operated to ensure that the test vector is passed from one domain to another.

The invention discloses a system for detecting malicious circuits in an FPGA (field programmable gate array) chip by power consumption analysis. The system comprises a DC (direct current) stabilized voltage source for supplying DC power to a to-be-detected FPGA chip and an excitation applying FPGA chip; a current probe for measuring a transient current at the power end of the to-be-detected FPGA chip; an oscilloscope triggered by a trigger signal generated by the to-be-detected FPGA chip to collect the current signal measured by the current probe; the excitation applying FPGA chip for applying an excitation signal to the to-be-detected FPGA chip, and transmitting the response signal of the to-be-detected FPGA chip to a computer for further verification and comparison with an expected response value; and the computer for receiving excitation restraint compiled by a user, generating a test vector, and completing response verification, oscilloscope setting, waveform data collection, data analysis and treatment. The invention also discloses a method for detecting malicious circuits in the FPGA chip by using the above system.

The present invention provides a built-in self-testing method of FPGA input/output module. Firstly all input/output modules in FPGA are configured to that a bidirectional IO buffer is used as a circuit to be tested. The logical resource of middle part of FPGA device is configured to a test vector generating circuit. The logical resource surrounding the IO buffer is configured to an output response analysis circuit of scanning chain structure. In testing, the test vector generating circuit generates a pseudo-random exhaustive vector for exerting a test pattern for each circuit to be tested; after executing the test vector, actuating the operation of scanning chain of output response analysis circuit, outputting the built-in self-testing result which is configured this time by the input/output module in the control of test clock by the output response analysis circuit until when the test covers all resources in the input/output module. The method of the invention has the following advantages: simplified built-in self-testing result retrieval mode, reduced test configuration number of times, reduced test cost and increased test efficiency under the precondition of guaranteeing 100% test coverage rate.

A system for automatically retargeting test vectors for application on tester systems having different performance capabilities is provided. The system includes a user selectable mode selector that can be adjustable between different performance modes, e.g. high, medium, and low. In high performance mode, the system allows test vectors to be applied using a high performance test system, e.g. a tester having high pin count. In low performance mode, the same test vectors can be applied but using a low performance test system, e.g. a tester having low pin count. By allowing the same test vectors to be used in a high performance or a low performance test environment, a testing facility can make maximum use of its available testing equipment for efficiently testing a device.

A method and system for remotely testing an integrated circuit installed in an integrated circuit system is presented. The integrated circuit is equipped with test structures for testing functional blocks within the integrated circuit, and a test access mechanism configured to receive test vectors for controlling the test structures. Test vectors are applied, via the parallel port of a remote computer and parallel cable, to pins of the parallel port of the integrated circuit system, which are connected to the signal ports of the test access mechanism implemented in the integrated circuit of interest, thereby allowing remote testing of the integrated circuit while the integrated circuit is installed in its native system.

An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.

The invention provides a universal single event effect detecting method of a memory circuit. The universal single event effect detecting method comprises the following steps of (1) configuring a memory to be detected to be in a write state, and writing into a test vector; and then arranging the memory to be detected in a radiation environment; (2) if a dynamic test is conducted, configuring the memory to be detected to be in a read state, reading out data stored in each address unit and comparing the read-out data with the written-in data, using the quantity of address units with different comparing results as a total error count, and further analyzing a condition that each address unit generates 2-bit or more than 2-bit data flipping; and (3) if a static test is conducted, configuring the memory to be detected to be in a non-read non-write state; after irradiation particles accumulated in an irradiation process reach a standard, sequentially reading out data in each address unit and comparing with the written-in data; and using the quantity of the address units with the different comparing results as the total error count. In the irradiation process, working current of the memory to be detected can be monitored in real time. Latch is implemented when the working current exceeds 1.5 times of normal working current.

Disclosed in the invention is an activity measurement-based hardware trojan detection method, comprising three parts: bench file generation, circuit activity measurement and hardware tojan detection test vector set generation. More specifically, a circuit netlist is analyzed; activity values of internal nodes of the circuit are calculated; lists of circuit nodes with low 0 activity and low 1 activity are generated; and determination and grouping are carried out on the nodes to generate a hardware trojan detection test vector set. According to the invention, different activity threshold values can be arranged; there is no extra hardware cost for hardware trojan detection; and combined logical type hardware trojan can be effectively detected. Besides, the provided method can be applied for target node extraction in a hardware trojan detectable design method.

A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, and having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.

Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

A hardware and software co-test method for FPGA comprises the following steps of: setting up a HW/SW co-test system comprising a PC, a software part, HW/SW communication modules, a hardware accelerator for testing a DUT FPGA which is mapped with a configuration file of DUT; predefining a table of test vectors for FPGA by software part in PC; generating configuration files based on the tables of test vector for I/O module, CLB and routing matrix, and then sending the configuration file into DUT FPGA to configure the FPGA; testing DUT FPGA in terms of the tables of test vector for lo I/O module, CLB and routing matrix, and returning results to the software part; and comparing the test results with expected data in the software part, generating a test report, and during the above steps, the error cells in the FPGA are capable of being automatically positioned.

The invention relates to a method for establishing a large-scale network chip verification platform. The method comprises the following steps of: firstly, establishing a control text document, and then writing an initial function of a random function library, and writing a calling function of the random function library; secondly, establishing a module-level function verification platform, comprising the following steps of: generating a top-level module of the module-level function verification platform, establishing a clock generating module and a reset generating module, establishing an interface signal module, establishing a test vector generating module, establishing a register configuring module and establishing a reference model module of a tested module; and thirdly, establishing a chip-level function verification platform, comprising the following steps of: generating a top-level module of the chip-level function verification platform, multiplexing the clock generating module, the rest module, the interface signal module, the test vector generating module, the register configuring module and the reference model module of the module-level function verification platform, and establishing a CPU simulation model. The method has a strong function, high efficiency, stability and simple structure. By means of the invention, the time for setting up the network chip verification platform can be greatly shortened and the stimulation efficiency can be improved.