307 results about "Test vector" patented technology

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention discloses a method and a device for improving positive and negative recognition accuracy of a test strip and a storage medium. The method comprises the following steps: acquiring image data of C-line and T-line areas of a test strip by using a multispectral camera; performing feature extraction and optimization processing on the acquired multispectral image; the abstraction detection process is a logic circuit model, and a node feature matrix is constructed; randomly injecting a fault into the model, simulating an environment problem, and generating a test vector; training a graph convolutional neural network model by using the failure response data, and adding cavity convolution; the trained model is applied to analyze real-time data, predict faults and evaluate color changes; if the detection is abnormal, accurately distinguishing red types by using a color difference matrix and time sequence analysis; and calculating the confidence coefficient based on the optimized features and the high-precision color information, and determining an object frame. By implementing the method provided by the invention, the problems of low accuracy, weak anti-interference capability and lack of effective fault simulation in the existing test strip detection technology can be solved.

The invention relates to the technical field of chip performance evaluation and test, in particular to a chip performance evaluation and fault diagnosis optimization test method, which comprises the following steps of: generating a test vector library with an optimal coverage rate on the basis of functional module distribution and circuit structure characteristics of chip design; in a chip operation environment, sequentially inputting test conditions by using the test vector library, and simultaneously collecting dynamic performance parameters in real time; based on the dynamic performance data set, establishing a multi-dimensional performance characteristic model comprising performance fluctuation characteristics, a critical state threshold value and hidden fault characteristics; based on a multi-dimensional performance characteristic model, in combination with circuit structure characteristics, a specific fault function module is positioned by reversely tracing the relevance between chip function modules. According to the method, innovative technical support is provided for chip design optimization and operation stability improvement, the fault diagnosis time is remarkably shortened, and the diagnosis precision and reliability are improved.

The embodiment of the invention discloses a processor front-end branch prediction and instruction fetching verification method and device and a storage medium, relates to the technical field of processor function verification, and can reduce the complexity of instruction scene construction and improve the verification efficiency. The method comprises the following steps: acquiring instruction fetching information and a test vector; the fetch information comprises a fetch address range and branch prediction information of the target instruction block, and jump instruction marking information is configured in the test vector; according to the fetch address range and the jump instruction mark information, generating an instruction boundary of each cache line in the fetch address range; respectively associating the branch prediction information and the jump instruction mark information to the instruction boundary of each cache line, and constructing to obtain an instruction stream; the instruction stream is used for simulating execution logic of processor front-end branch prediction and instruction fetching; and decoding simulation verification is carried out based on the instruction stream, and processor front-end branch prediction and instruction fetching accuracy is determined. The method is suitable for a verification scene of processor front-end branch prediction and instruction fetching.

The invention discloses a digital-analog collaborative test method, which comprises the following steps of: in a parameter configuration stage, embedding a trigger mark into a preset vector row to generate a test vector, and writing the test vector into a digital board card; configuring a trigger event corresponding to the trigger signal and first delay time; in the test stage, the digital board card detects whether a to-be-executed vector line has a trigger mark or not; a trigger signal corresponding to the trigger mark is sent to the system board card; the system board card sends the trigger signal to a corresponding simulation board card, and the simulation board card determines first delay time and a trigger event according to the trigger signal; delaying the trigger event for a first delay time and then triggering; the digital board card delays a second delay time after sending the trigger signal and sends test data corresponding to the vector line to the to-be-tested device; in the triggering process of the triggering event, the end time of the second delay time is aligned with the end time of the first delay time. According to the invention, the efficiency of digital-analog collaborative testing can be improved.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

The invention relates to the technical field of chip test vector intelligent generation scheme design, in particular to a failure analysis-oriented chip test vector intelligent generation method and system. The method comprises the following steps: acquiring a chip design netlist, a fault model and a known failure mode; analyzing potential design or manufacturing defects based on the information; and according to an analysis result, a targeted test vector capable of effectively exciting and isolating potential defects is automatically generated. The system comprises a corresponding input module, an analysis module and a generation module. According to the method, the design information, the fault model and the historical failure mode are intelligently fused, automatic and precise generation of the test vector is achieved, and the defects that a traditional method is insufficient in test coverage rate, low in failure positioning efficiency and limited in automation degree are overcome. According to the method, the test completeness and the failure analysis efficiency can be remarkably improved, the dependence on artificial experience is reduced, and an efficient technical means is provided for guaranteeing the reliability of the chip.

The invention provides a system and a method for testing the immunity of a chip of an SRAM (Static Random Access Memory). The system comprises an upper computer, a test board, an FPGA (Field Programmable Gate Array) monitoring unit and an electromagnetic interference tester, the upper computer is used for configuring test parameters of the FPGA monitoring unit and acquiring and displaying a read-write result fed back by the FPGA monitoring unit in real time; the test board is used for bearing a to-be-tested SRAM chip and at least comprises an interference injection network and a signal connection interface; and the FPGA monitoring unit is used for performing read-write test on the to-be-tested SRAM chip according to the test parameters and uploading a read-write result to the upper computer in real time. In the test process, the upper computer configures the FPGA monitoring unit through the test parameters to execute different test vectors, the FPGA monitoring unit communicates with the to-be-tested SRAM chip and feeds back read-write results to the upper computer in real time, the read-write results are visually displayed by the upper computer, and the flexible, controllable, visual and visible immunity test process is achieved.

The invention discloses a register model and register transfer level generation and test method, device, equipment and medium, and relates to the technical field of integrated circuit design verification, and the method comprises the following steps: analyzing a comma separation value table file by using a register generation platform to generate a register model, a register transfer level and a register test vector; the comma separation value table file is a file used for describing register information; generating a general verification methodology environment by using a test environment generation platform, and integrating the general verification methodology environment based on the register model, the register transfer level and the register test vector to obtain a corresponding integrated test environment; and compiling the integrated test environment, if the compiling is successful, running the register test vector in the integrated test environment which is successfully compiled, and outputting a corresponding test result. Therefore, the automation degree of register model verification can be improved, and the verification efficiency of front-end verification is improved.

The invention provides a chip test method, system and device and a storage medium, the chip test device comprises a main control board, a digital test board and a cooperation test board which are mutually connected through a backboard, and the digital test board and the cooperation test board are test board cards of different types. The test operation data of the cooperation test board and the time sequence of the test vector of the digital test board are synchronized; and the main control board synchronously triggers the digital test board and the matching test board through the test instruction, so that the matching test board executes a test operation according to the test operation data, and the digital test board synchronously executes the test operation according to the test vector so as to synchronously test the chip to be tested. The main control board can control different types of board cards to execute tests in a software instruction triggering mode, and due to the fact that the test operation data are synchronous with the time sequence of the test vectors, synchronous matching can be achieved when the digital test board and the matching test board execute the test operation according to the test data of the digital test board and the matching test board. And the synchronization precision of different types of board cards during chip testing is improved.

The invention relates to a storage test vector generation method and device, equipment and a storage medium, and is applied to the field of semiconductor testing, and the method comprises the steps: obtaining a chip manual and a chip test plan of a to-be-tested chip, and generating a chip description file according to the chip manual and the chip test plan; carrying out abstract processing according to the chip description file, and generating a chip abstract model; converting test logic in a test algorithm into a test sequence according to the chip abstract model; and obtaining a target file format requirement of a target ATE equipment platform, and converting the test sequence according to the target file format requirement to generate a storage test vector. The method has the technical effects that the reusability of cross-platform use of the test vector is improved, the test development efficiency is improved, and the time is saved.

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

A method of method of classifying data is disclosed. The method comprises manipulating quantum states of qubits of a quantum computing device based on a first copy of a test vector, a second copy of the test vector, a first training vector and a second training vector, so as to load a modified first copy of the test vector, a modified second copy of the test vector, a modified first training vector and a modified second training vector onto the quantum computing device, wherein the magnitude of the angle between the modified first copy of the test vector and the modified first training vector is equal to the magnitude of the angle between the first copy of the test vector and the first training vector, and where the magnitude of the angle between the modified second copy of the test vector and the modified second training vector is equal to the magnitude of the angle between the second copy of the test vector and the second training vector. The method also comprises performing quantum interference between the modified first copy of the test vector and the modified second copy of the test vector, and the modified first training vector and the modified second training vector, to provide modified quantum states of the qubits, performing a measurement on one or more of the qubits, and classifying the test vector based on the measurement.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention discloses a chip test retrieval method and system based on a large model, and the method comprises the following steps: collecting chip test documents, and constructing a chip test vector knowledge base; receiving user query, and executing search in the knowledge base by using the word vector model structure; richer context information is generated based on a retrieval result and user query, and a test case or a test analysis report is generated through a fine-tuned large model. According to the method, the retrieval capability and the generation capability are effectively integrated, efficient retrieval of test instructions and knowledge and automatic generation of test cases / reports are achieved, and the chip test efficiency and quality are remarkably improved. Meanwhile, the retrieval generation system adopts a Django framework development platform, performs real-time streaming output and real-time feedback of retrieval results by means of the MyWebsocket technology, and writes question and answer data into MySQL. The system comprises a knowledge base construction module, a retrieval module, a generation module, a streaming interaction module and a data storage module. Compared with the prior art, the method has the advantages that the test instruction retrieval accuracy is improved by more than 18%, the test case generation time is shortened by 60%, and the test knowledge is shared and reused.

The invention provides an integrated circuit testability and test point insertion method, device, equipment and medium, and is applied to the field of integrated circuit testability design, and the method comprises the steps: firstly, judging violation setting types (such as one or more combinations of '-from', '-through' and '-to') existing on a path, and then, according to different time sequence violation settings, carrying out the test point insertion according to different time sequence violation settings. Different test point insertion strategies are adopted: for '-from' and '-through' setting, a test point is inserted behind the last non-'-to' path, so that the test point is utilized to prevent X-state backward propagation; and for the '-to' setting, related circuit nodes are masked (hidden or shielded) so as to control the X state not to influence the subsequent test. After the test points are inserted, the derivation difficulty, the operation time and the vector number of automatic test vector generation can be remarkably reduced, meanwhile, the test coverage rate is improved, and the method has wide applicability and operability.

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an aliasing chip testing method and device. Comprising the steps of generating a chip device defect and failure model classification matrix by constructing a chip internal component model; burning the test vector to a chip test device; performing function and performance parameter testing on the 2.5 D / 3D aliasing chip according to the related information of the chip device defect and failure model classification matrix and the firmware program of the test vector; by constructing the mass production failure early warning model, the yield of the multi-layer aliasing chip is improved. According to the test method, the function and electrical performance parameter test of the multi-layer aliasing chip is realized, the function and parameter verification of the chip is realized, the interconnection fault between the internal components of the chip can be detected, and the yield of the chip is improved by feeding back an engineer according to mass production data.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The invention discloses an automatic test vector generation method and system based on backtracking path optimization, and the method comprises the steps: inputting the feature information of each logic gate of a to-be-tested circuit into a trained neural network model, and predicting the state of each logic gate, including success and failure; and performing automatic test vector generation by adopting an ATPG algorithm according to the state of the logic gate, selecting the logic gate to add into a backtracking path for the logic gate with a successful label in the backtracking process, and skipping the logic gate for the logic gate with a failed label. According to the method, backtracking path generation is assisted according to the prediction result, more efficient test vector generation of the ATPG tool is facilitated, and the test time and the backtracking frequency are reduced.

The present invention relates to a method for securing against fault attacks the execution of the verification of a Crystals-Dilithium post-quantum digital signature σ of a message M comprising a challenge seed c̃, a test vector z and a hint vector of polynomials h generated with a secret key sk = (ρ, K, tr, s1, s2, t0), said digital signature verification taking as inputs, said digital signature σ, said message M and a public key pk = (ρ, t1) and comprising a step of ensuring that a fault attack aiming at verifying one of the conditions P1, P2 and P3 does not lead to accept a forged signature, where : ct1.2d=0, ‖ct1.2d‖∞<βand‖LowBitsq(Az−ct1.2d,2γ2‖∞<γ2−β, ‖ct1.2d‖∞<γ2.

The invention provides a test vector generation method and device in circuit design, and the method comprises the steps: obtaining a scanning chain group in the circuit design, the scanning chain group comprises N scanning chains, and each scanning chain in the N scanning chains comprises at least one register; value constraint is carried out on at least one register of each scanning chain in the N scanning chains according to a preset code pattern, the value constraint is used for limiting the value of the at least one register to be 0 or 1, the length of continuous 0 or the length of continuous 1 in the preset code pattern does not exceed Q, and Q is larger than or equal to 1; and according to the register subjected to value constraint, solving to obtain a test vector corresponding to the scan chain group. The method provided by the invention can realize high-precision diagnosis.

The invention discloses a processing method and device and electronic equipment, and the processing method comprises the steps: generating an initial test vector supported by test equipment according to the test equipment and a test case for a to-be-tested chip; based on the initial test vector, performing simulation verification on the to-be-tested chip, and based on a simulation verification result, adjusting the initial test vector until the simulation verification is passed, and forming a target test vector; and generating a test program of the test equipment based on the target test vector.

The invention discloses an automatic test vector generation method and system based on a decision tree, and the method comprises the steps: firstly extracting the node feature data of a to-be-tested circuit, and then obtaining and calculating the backtracking confidence coefficient of each logic gate through a trained decision tree model; the backtracking confidence is a prediction probability value of the decision tree model for successful fault propagation of the logic gate in the backtracking path; and finally, selecting a logic gate with high backtracking confidence as a node to be added into a backtracking path, and generating a test vector according to the backtracking path. According to the method, the number of test vectors can be effectively reduced, the time complexity of fault detection is reduced, and the problems of high backtracking frequency, high resource consumption, noise data interference and the like in a traditional method are solved.

The invention relates to a simulation modeling system based on a UVM. The system comprises a component library management module, an incentive library management module, a top layer generation module, a graphical modeling module, a script generation module, a coverage rate statistics module and a server calling module, wherein the component library management module is used for managing a UVM component model; the incentive library management module is used for managing the incentive model; the top layer generation module is used for generating a corresponding top layer module according to the top layer file; the graphical modeling module is used for modeling according to the UVM component model; the coverage rate counting module is used for counting coverage rate data in the verification test process; the script generation module is used for generating various modeling files; and the server calling module is used for completing simulation of the modeling file. Therefore, the UVM can be directly used to realize random generation of test vectors, automatic comparison of test results and automatic statistics of code coverage rate and function coverage rate, and the FPGA test coverage rate and quality are greatly improved.

According to the chip aging test method, the upper computer and the aging test device, incremental compiling can be carried out on vector files, and due to the fact that the unmodified vector files are not recompiled, the compiling speed can be increased, and then the aging test speed is increased. The chip aging test method comprises the following steps: calculating a check code list of a to-be-compiled vector file group, and determining a revised vector file and a non-revised vector file from the to-be-compiled vector file group according to a comparison result of a check code list of a first historical vector file group and the check code list of the to-be-compiled vector file group, and compiling the revised vector file into a first target vector file, acquiring a second target vector file corresponding to the non-revised vector file from the second historical vector file group, generating an aging test vector program package according to the first target vector file and the second target vector file, and sending the aging test vector program package to the aging test device.

The invention relates to the technical field of data storage, and discloses a method and system for optimizing test data collected by a memory chip based on machine learning, and the method comprises the steps: collecting original test data from a test platform of a to-be-tested memory chip; constructing a convolutional neural network model, learning a mapping relationship between test data features and memory defects through the convolutional neural network model, training the convolutional neural network model through the collected original test data, optimizing parameters of the convolutional neural network model according to a training result through a back propagation algorithm, and obtaining memory defects through the optimized parameters. The performance of the convolutional neural network model tends to be stable; converting a parameter vector output by the convolutional neural network model into a test vector executable by ATE; and taking the generated test vector as a new training sample, feeding back the new training sample to an original test data updating data set, and iteratively training and optimizing the convolutional neural network model. According to the invention, intelligentization of the test process is realized, and hidden defects sensitive to voltage and time sequence can be effectively captured.

This application relates to the field of simulation verification technology, and specifically to a simulation verification management and control method, apparatus, computing device, and storage medium. The method specifically involves: generating a regression test case list for simulation verification based on functionally decomposed test points; the regression test case list includes classification information based on test vectors to categorize regression test cases; performing simulation regression based on the regression test case list to obtain regression records; analyzing the regression records to obtain analysis results; the analysis results include at least one of the following: regression status, failed test case annotation, test case coverage, convergence status, and simulation resource consumption status; and managing simulation verification based on the analysis results. This application embodiment, by performing simulation verification based on test points and analyzing regression records, allows for quantitative management of verification progress, timely supplementation of test cases, and objective and accurate evaluation of module convergence status, which is beneficial for project convergence and enables comprehensive management of simulation verification projects.

The present invention relates to a programmable memory built-in self-test method based on a finite state machine, and the method is implemented by a programmable Mbist control module driven by three counters, an algorithm module, a comparison and analysis module, and a BRAM to be tested. In the present invention, the algorithm module integrates 8 test algorithms and generates characteristic signals according to the characteristics of each test algorithm, thereby improving the coverage of faults. Secondly, the programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters, thereby improving the flexibility of the test. The present invention provides a new programmable memory built-in self-test method based on a finite state machine, which replaces the conventional test method. When the test algorithm needs to be replaced, the proposed test method does not need to reset the Mbist circuit, effectively reducing manpower and configuration time, thereby reducing the test cost.

This disclosure provides a chip testing system, method, and apparatus. The system includes: an instruction sequence module for generating corresponding test instruction sequence identifiers based on a test instruction set; a test vector generation module for configuring a mode based on rate mode configuration information to determine the target number of channels; and generating a test vector for each channel based on the test instruction sequence identifier; and a test signal output module for performing signal conversion processing on the test vectors to generate a target test signal to complete the chip testing.

A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.