Method for establishing large-scale network chip verification platform

A network chip and verification platform technology, applied in the field of verification method and verification platform construction, can solve the problems of less code, more design gates, time-consuming and other problems, and achieve the effect of powerful function and simple structure

Active Publication Date: 2010-06-30
丁贤根
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Coupled with the increase in the number of design gates, the writing of test modules becomes more difficult and time-consuming due to the reduction of design controllability
Verifying correct behavior is also made difficu

Method used

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  • Method for establishing large-scale network chip verification platform
  • Method for establishing large-scale network chip verification platform
  • Method for establishing large-scale network chip verification platform

Examples

Experimental program
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Embodiment Construction

[0046] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0047] 1. First create a control text file (control.txt), whose content is variable name and random type. The random type consists of one or more sets of return value types and weights. If there are multiple sets, separate them with ",". Generally, there are fixed value types that are commonly used, and each time a function is called, a fixed value is returned. Interval value type, each call, the return value is within an interval. Step value type, each time the function is called, the return value will be fixedly increased or decreased by a step length. Sequence value type, each time the function is called, the return value is returned in the order of the sequence. There is also a random value type, which generates a corresponding random value based on a different random seed each time, as well as other user-defined types. For random type...

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Abstract

The invention relates to a method for establishing a large-scale network chip verification platform. The method comprises the following steps of: firstly, establishing a control text document, and then writing an initial function of a random function library, and writing a calling function of the random function library; secondly, establishing a module-level function verification platform, comprising the following steps of: generating a top-level module of the module-level function verification platform, establishing a clock generating module and a reset generating module, establishing an interface signal module, establishing a test vector generating module, establishing a register configuring module and establishing a reference model module of a tested module; and thirdly, establishing a chip-level function verification platform, comprising the following steps of: generating a top-level module of the chip-level function verification platform, multiplexing the clock generating module, the rest module, the interface signal module, the test vector generating module, the register configuring module and the reference model module of the module-level function verification platform, and establishing a CPU simulation model. The method has a strong function, high efficiency, stability and simple structure. By means of the invention, the time for setting up the network chip verification platform can be greatly shortened and the stimulation efficiency can be improved.

Description

(1) Technical field [0001] The invention relates to the field of network chip verification, in particular to a network chip verification method and the construction of a verification platform. (2) Background technology [0002] As large-scale digital network chips reach millions or even tens of millions of gates, the number of chip pins continues to increase, the clock frequency is gradually accelerated, and the chip size is getting smaller and smaller, chip function verification has become a bottleneck in the entire chip development. The time of functional verification accounts for about 70% of the total design time, and requires a dedicated verification team, usually the number of verification personnel is 1 to 2 times the number of designers. This also puts forward higher requirements for chip verification. For functional verification, most of the industry currently adopts the traditional verification process, plus a more efficient advanced verification verification lang...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 张磊磊李枫何慈康郑有为丁贤根
Owner 丁贤根
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