Method for establishing large-scale network chip verification platform

Abstract

The invention relates to a method for establishing a large-scale network chip verification platform. The method comprises the following steps of: firstly, establishing a control text document, and then writing an initial function of a random function library, and writing a calling function of the random function library; secondly, establishing a module-level function verification platform, comprising the following steps of: generating a top-level module of the module-level function verification platform, establishing a clock generating module and a reset generating module, establishing an interface signal module, establishing a test vector generating module, establishing a register configuring module and establishing a reference model module of a tested module; and thirdly, establishing a chip-level function verification platform, comprising the following steps of: generating a top-level module of the chip-level function verification platform, multiplexing the clock generating module, the rest module, the interface signal module, the test vector generating module, the register configuring module and the reference model module of the module-level function verification platform, and establishing a CPU simulation model. The method has a strong function, high efficiency, stability and simple structure. By means of the invention, the time for setting up the network chip verification platform can be greatly shortened and the stimulation efficiency can be improved.

Description

(1) Technical field [0001] The invention relates to the field of network chip verification, in particular to a network chip verification method and the construction of a verification platform. (2) Background technology [0002] As large-scale digital network chips reach millions or even tens of millions of gates, the number of chip pins continues to increase, the clock frequency is gradually accelerated, and the chip size is getting smaller and smaller, chip function verification has become a bottleneck in the entire chip development. The time of functional verification accounts for about 70% of the total design time, and requires a dedicated verification team, usually the number of verification personnel is 1 to 2 times the number of designers. This also puts forward higher requirements for chip verification. For functional verification, most of the industry currently adopts the traditional verification process, plus a more efficient advanced verification verification lang...

AI Technical Summary

Problems solved by technology

Coupled with the increase in the number of design gates, the writing of test modules becomes more difficult and time-consuming due to the reduction of design controllability

Verifying correct behavior is also made difficult by the reduced observability of internal design state

Test modules become difficult to understand and maintain

It becomes more difficult to create and maintain multiple environments, and there is too little reusable code

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