179 results about "Module under test" patented technology

The invention provides an active optical module multi-channel automatic test system and a method. optimal signals emitted by a tested optical module are monitored, and indexes of the incident light power, emission current, bias current, temperature, voltage, extinction ratio, eye diagram allowance, crossing point, OMA (optical modulation amplitude) etc. are measured and calculated; if the above indexes are all in accordance with the standard, the sensitivity of the optical module is tested, the emission optical power of the tested module is enabled to reach the sensitivity of the test standard via the adjustment of an attenuator, and error code tests are conducted; and if there is no error code, indexes of alarm value and alarm recovery etc. of the optical module are tested. According to the test system, an error detector, an optical module test board, an optical power meter, and the attenuator employed by the test system are all multi-channel devices, an optical switch and an optical splitter are combined for time-sharing multiplexing of one oscilloscope, at least 8 modules can be simultaneously tested, the utilization rate of the oscilloscope and the test efficiency of the optical module are greatly optimized, the equipment cost and the manual cost are reduced, and automatic and batch production of the optical modules is realized.

The invention relates to a method for constructing a verification and test platform of network chip module level functions, comprising the construction of a simulation and reference model of the tested modules, which is characterized in that: the method comprises the construction of all modules and documents; the output of an excitation generating model is connected with the inputs of the tested module and the simulation and reference model, a clock and a reset generating module are connected with the tested module and the clock and reset signal of the simulation and reference model, a register initialization module is connected with the register of the tested module and the simulation and reference model, and a CPU simulation module is connected with the CPU of the tested module; the output of the tested module is connected with the simulation and reference model, thus, the network chip module level function verification and test platform can be constructed. The invention has the advantages that the platform can be constructed easily and directly, so the time required to construct the module level function verification and test platform can be shortened greatly in the high performance network chip verification process; meanwhile, the platform constructed by the method has clear structure which is easy to be understood and has improved reliability.

The invention relates to a method for establishing a large-scale network chip verification platform. The method comprises the following steps of: firstly, establishing a control text document, and then writing an initial function of a random function library, and writing a calling function of the random function library; secondly, establishing a module-level function verification platform, comprising the following steps of: generating a top-level module of the module-level function verification platform, establishing a clock generating module and a reset generating module, establishing an interface signal module, establishing a test vector generating module, establishing a register configuring module and establishing a reference model module of a tested module; and thirdly, establishing a chip-level function verification platform, comprising the following steps of: generating a top-level module of the chip-level function verification platform, multiplexing the clock generating module, the rest module, the interface signal module, the test vector generating module, the register configuring module and the reference model module of the module-level function verification platform, and establishing a CPU simulation model. The method has a strong function, high efficiency, stability and simple structure. By means of the invention, the time for setting up the network chip verification platform can be greatly shortened and the stimulation efficiency can be improved.

The invention provides a power semiconductor device loss characteristic test platform and method. The device comprises a DC power supply module used for providing electric energy to a tested module according to a given reference voltage, the tested module comprising at least one tested unit used for simulating a work state of power semiconductor devices, a driving module used for controlling switch states of the power semiconductor devices of the tested unit according to a switch state signal outputted by a main control module, a measurement module used for detecting an electrical state and atemperature state of the power semiconductor devices of the tested unit and a corresponding load module, and the main control module used for analyzing the result measured by the measurement module and controlling the whole test platform to acquire loss characteristics of the power semiconductor devices of the tested unit. The device is advantaged in that switch and state characteristic tests of the multiple power semiconductor devices close to a real work state can be realized, and setting of multiple test conditions including current, voltage and temperature can be carried out.

The invention discloses a system and a method for automatically testing an analog module with a settable input/output (I/O) channel in a programmable logic controller (PLC). The system comprises an upper control computer, a programmable direct current signal source, a digital multimeter, a channel and voltage/current mode switching control plate and a communication interface, wherein the upper control computer sets a testing parameter, issues an instruction to realize output or measurement, receives a test result and makes judgment according to the result; the programmable direct current signal source receives the instruction and the parameter to set the output as a voltage or current mode, sets and outputs a voltage/current signal to an input channel; the digital multimeter receives the instruction to set the measurement as the voltage or current mode, measures the voltage or current signal output by an output channel and returns a measured value to a computer; the channel and voltage/current mode switching control plate switches a test channel and a voltage/current connection mode according to the instruction; and the communication interface transmits the parameter, the instruction and the test result between each device and a tested model. A computer reads the conversion value of the voltage or current measured value of the input channel through the communication interface or transmits a set numerical value to the output channel to convert the set numerical value into a voltage or a current.

A filter module configured for exhaust application, and a method and apparatus for testing the same are provided. In one embodiment, the filter module includes a downstream sampling port configured to allow a technician to sample flow, downstream of the filter module, from the cleanroom side of a filter module. In another embodiment, a shroud adapted to sealing engage a filter module under test is provided and includes a tube, disposed in the shroud, that couples a port to a downstream sampling port of the filter module.

The invention provides a software testing method and system. The method comprises the following steps: performing functional partitioning on a plurality of tested modules in tested software to generate a plurality of tested module sets and generate authority information corresponding to each tested module set; receiving a control command of testing personnel by a testing proxy server; forwarding the control command to the corresponding tested module set by the testing proxy server according to the authority information of the testing personnel; after executing the control command by the tested module set, acquiring output view information related to the control command by the testing proxy server; and transmitting the output view information to the testing personnel by the testing proxy server. According to the method provided by the embodiment of the invention, on one hand, the software which cannot be opened to outsourcing and remote testing personnel for the sake of security and privacy can be tested to expand the testing range and improve the testing efficiency and quality, and on the other hand, the tested software is not required to be provided for the testing personnel such as the outsourcing personnel and the remote testing personnel, so that decompiling cannot be performed to acquire a source code and the security is high.

The invention discloses an FPGA (Field Programmable Gate Array) online verification structure and a method based on a serial communication interface. The structure comprises a software simulation environment, a hardware test environment and a physical channel, wherein the software simulation environment is configured to be in signal interaction with the hardware test environment through the physical channel; the software simulation environment produces test vectors and debug commands of a bus cycle, and receives a feedback signal to display in a wave way; the hardware test environment receives the test vectors and the debug commands, and sends the feedback signal. The verification structure and the method not only can effectively provide an FPGA online verification platform and simulate a working process of an integrated circuit module or a chip, but also has the characteristic of platform reusability, and are not designed aiming at a specific module; in addition, verification personnel can intuitively monitor and configure the port state of a module to be tested.

A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The verification agent interacts with the module under test, including sending signals to the module under test and generating results based on the interaction. The code causes the processor to receive the results and compare the results with expected values. The module under test may be deemed to operate properly if the actual results match the expected values.

A database architecture and method of using a database is disclosed. The database is intended for use with a product stress testing system in which a large number of different modules may be subjected to a variety of stressors including environmental stressors and functional load testing. The database also enables a wide variety of test and communication equipment to be used in an efficient manner to test and communicate with the module being tested. Generic commands may be translated to test and communication equipment specific command strings as well as module specific command strings. Data collected from these various devices by the stress testing system may also be parsed and stored in fields associated with the corresponding module being tested. The product table, result table, process table, and equipment command & communication tables are interrelated through defined data associations. These data entities and their mutual data relationships revolve around the module being subjected to the stress test. In this way the stress test results may be associated with the various products, the results may be mapped against product-specific test criteria, and generic commands may be translated to product-specific commands. A virtual oven may be used as the stress-testing system and includes a logical grouping of modules, a controller, test instruments which are all connected via a network to the database for collection of the data, control of the system, and generating displays and reports.

The invention discloses a detecting device and a detecting method of time sequence parameters of a small package pluggable transceiver. The device comprises a test board, a module to be tested, a standard module, singlechips and an upper computer, wherein the test board is provided with two slots, the module to be tested is plugged in one slot, the standard module is plugged in the other slot, a transmitting terminal of the module to be tested is connected with a receiving terminal of the standard module via optical fiber, a receiving terminal of the module to be tested is connected with a transmitting terminal of the standard module via optical fiber, the singlechips are plugged in parallel on the test board, the singlechips are respectively a control-type singlechip and a bus-type singlechip, time sequence pins of the module to be tested and the standard module are respectively electrically connected with input/output ports of the control-type singlechip via the test board, the control-type singlechip is electrically connected with the bus-type singlechip via a serial bus, and the bus-type singlechip is communicated with the upper computer via a USB conversion chip and a serial conversion chip on the test board. The invention can realize the effects of automated testing, simple operation and high measurement accuracy.

Aspects of a method and system for simulation and verification of communication devices are provided. In this regard, a wireless communication system that comprises at least a wireless signal source and the wireless communication device may be simulated utilizing a plurality of configurable modules that comprises: a module under test, a processor module, and a signal source module. A subset of processor modules may be selected based on test cases to be performed for the simulation. The selection of the subset of processor modules may be performed without recompiling the processor module. A subset of signal source modules may be selected based on characteristics of a signal source to be modeled during the simulation. The selection of the subset of signal source modules may be performed without recompiling the signal source module.

A GPS module test system for automatically calibrating a test signal includes a GPS test fixture, a satellite signal simulator, and a computer. The GPS test fixture carries a GPS module under test and is electrically connected to the same through contact, so as to receive a digital signal generated by the GPS module after the test. The computer receives device information of the GPS module under test through the GPS test fixture, and controls the satellite signal simulator through a GPS signal sample database, so as to generate a GPS analog signal to test the GPS module under test. Thereafter, on receiving the digital signal generated by the GPS module under test and determining the received digital signal is attenuated, the computer automatically gains a transmitted test parameter, so as to transmit the GPS analog signal in a preferable state.

The invention provides a distributed cluster performance test system, method and device. The system comprises an upstream cluster, a tested module, a back end cluster, a network bridge, a pressure tool and a monitoring module. The network bridge is used for receiving a first pressure request sent by the upstream cluster, sending the first pressure request to the tested module, receiving a second pressure request generated by the tested module according to the first pressure request, forwarding the second pressure request to the back end cluster and storing the first pressure request and communication data packs returned by the back end cluster according to the second pressure request. The pressure tool is used for sending preset pressure to the tested module according to the first pressure request, and the tested module forwards the preset pressure to the network bridge, so that corresponding packs in the stored communication data packs are checked and are returned to tested module. The monitoring module and the tested module are placed on the same server. The monitoring module is used for monitoring performance data of the server and carrying out performance analysis according to the performance data. The network bridge is used for simulating a real cluster, performance test accuracy and test efficiency are improved, and cost is saved.

The invention relates to a UVM environment constructing method and system, and belongs to the technical field of universal verification methods. The method includes the steps that according to the number and the type of monitored module interfaces, assemblies corresponding to the interfaces are configured in a graphic input mode, wherein each assembly at least comprises a sequencer, a driver and amonitor, and configuration files of graphic structures are generated; the configuration files of the graphic structures are analyzed, and UVM tree structures and corresponding UVM environment files are obtained; monitored modules are connected, and the UVM verification environment is established. The system comprises a configuration module, an analysis module and a calling module. According to UVM environment constructing method and system, the learning difficulty and the development difficulty of verification engineers are reduced, time of developing the verification environment is saved, verification time is shortened, and the verification efficiency is improved.

The invention belongs to a central control system of an automotive practical training platform. The central control system of the automotive practical training platform comprises tested modules of automotive assemblies, a computer control module,electrical connectors,an acquisition device, an on-off control device and an upper computer. The computer control module to execute tasks is preinstalled in the upper computer. The computer control module using a practical training software integrated development environment as a basic platform is started. The upper computer is connected with the acquisition device, the on-off control device and the tested modules of automotive assemblies through the electrical connectors, and real-time interaction is available. After execution of communicating, control and measurement tasks, test data acquired by the acquisition device in real time are converted into a format of standard protocol and are uploaded to the computer control module for processing. Therefore, learning procedure, examination procedure and assembly parts of a real automotive are integrated into the same system, so that teaching flexibility is improved, and high teaching cost is saved while teaching quality is improved greatly.

The invention provides a method for testing a Linux kernel-grade unit, which comprises the following steps of: compiling a tested module and loading the compiled tested module into a kernel space; building a kernel-grade unit testing frame; building a unit testing module; compiling the kernel-grade unit testing frame and the unit testing module together and loading the compiled module into the kernel space; and outputting a unit testing result.

The invention provides an acceleration simulation stand, comprises cylinder, mechanical transmission device and support. The cylinder drives measured module move in variable motion by mechanical transmission device. The mechanical transmission and measured module are set on the support. The invention is provided with simple operation and low cost so on. It can solve high cost of prior related equipment and complex operation so on well.

The invention provides a method and device for rapidly verifying a chip by multimedia player. The method comprises the following steps: reading a file to be tested from a memory; judging the type of the file and automatically carrying out constraint correction on attribute parameters of the file when the file is a YUV image or an RGB image; when the file is an JPEG image or a video file, carrying out constraint correction on the attribute parameters of the file after decoding the file; setting up corresponding attribute parameters according to the constraint correction result, and inputting the file into a tested module provided with a verification chip to play; and circularly carrying out each testing step and traversing the testing of each file in the memory. By the invention, the image files and the video files are automatically traversed and played so as to simplify the operation of the tester, save the human resources, improve the working efficiency and rapidly verifying the stability of the chip.