89 results about "Module under test" patented technology

The invention provides a verification method and device for a to-be-tested module, and relates to the technical field of chip verification. The reference model generates and stores at least one piece of table look-up information corresponding to a data packet after receiving the data packet every time, and sends a generated first processing result corresponding to the data packet and a data packet identifier to the comparator, the table look-up information comprises a table look-up result, and the table look-up information and the corresponding data packet identifier are correspondingly stored; the to-be-tested module obtains a corresponding target table look-up result from table look-up information stored in the reference model based on a target data packet identifier corresponding to a currently generated second target table look-up request, and then a generated second processing result and the target data packet identifier are sent to the comparator; and the comparator obtains a comparison result according to the first processing result and the second processing result corresponding to the same data packet identifier, and the comparison result is used for determining a verification result. In this way, the situation that the simulation stop time point and the real error output time point cannot be aligned can be reduced.

This specification provides a technical solution for bounded model detection. Using the method and apparatus provided in this specification, the application or module to be verified is uniformly denoted as the module under test. First, the call tree constructed by each verification unit corresponding to the module under test is obtained. Then, each node's corresponding first verification indicator is detected. Based on the first verification indicator, a first type of node that needs independent verification is determined. Next, the call relationships in the call tree are used to verify the first type of node, and other nodes are inlined into their corresponding call scenarios for verification. This effectively reduces the repetitive verification of complex functions and improves verification efficiency.

This invention belongs to the field of wireless communication module production testing technology, and discloses a parallel testing method and system for wireless modules based on fixed-channel broadcast communication. Applied to a factory production testing environment, the method includes: powering on and initializing multiple modules under test (DUTs) on the same panel, and uniformly setting them to a fixed wireless communication mode and channel according to their workstation addresses; setting up a wireless companion device, which operates on the same fixed mode and channel as the DUTs; the companion device cyclically sending specific broadcast test messages; each DUT, upon receiving a broadcast message, reports a response message to the host computer of the tooling; the host computer determines whether the wireless function of the DUT at that workstation is qualified based on whether it receives a correct response message from the corresponding workstation. This method achieves parallel testing at multiple workstations through a one-to-many broadcast communication mode, improving production efficiency and effectively reducing the problem of wireless co-channel interference during simultaneous testing at multiple workstations.

The invention discloses an energy-consuming valve power module cyclic aging test platform and a cyclic aging test method, which are suitable for reliability verification of a direct-current energy-consuming device power module. Through collaborative design of a capacitive power supply and an inductive load, closed-loop utilization of energy is realized, and modularized alternating test logic is adopted, so that the test efficiency is improved. A direct-current power supply is used for providing a current source for a test loop, a test object is a test valve section formed by connecting a plurality of power module units in series, the test loop is composed of two test valve sections, and the two test valve sections are tested objects mutually. The design of the series energy consumption valve power module enables a plurality of tested modules to be subjected to cyclic aging at the same time. According to the invention, the power circulation of the energy consumption branch can be realized, and the data obtained through the test can be applied to key scenes such as health condition evaluation and control logic judgment of the IGCT device.

This invention provides an automated factory testing method, apparatus, equipment, and medium for smart gateway LoRa base stations. The method includes: processing data transmission and reception via an RS485 serial port to verify the accuracy of the transmitted and received information of the smart gateway LoRa base station under test; performing read / write processing on the EMMC module and verifying it; conducting dial-up tests on the communication components to verify the network status of the smart gateway LoRa base station under test; collecting and comparing the current values ​​of each interface of the ADC module; reading the frequency band values ​​of the RF module and comparing them with a preset qualified set; establishing communication between the RF module and the LoRa module under test, and performing communication tests on the LoRa module under test; and outputting an alarm signal when a test anomaly signal is detected. Furthermore, existing automated factory testing solutions for industrial smart gateway LoRa base stations rely too heavily on third-party testing equipment, increase human intervention, have high testing and maintenance costs, and are prone to human error.

The utility model relates to a cooling device of a test board and the test board, the test board is provided with a test area and a controller installation area, the cooling device comprises an insulation heat conduction silica gel pad, a heat dissipation metal layer, a first cooling pipeline, a second cooling pipeline and a cooling pump, the insulation heat conduction silica gel pad is arranged on a controller, and the heat dissipation metal layer is arranged on the first cooling pipeline. The heat dissipation metal layer is arranged on the insulating heat conduction silica gel pad, one end of the first cooling pipeline is arranged on the heat dissipation metal layer, the other end of the first cooling pipeline is connected with the cooling pump, the first cooling pipeline is used for providing cooling liquid for the heat dissipation metal layer under the action of the cooling pump, and one end of the second cooling pipeline is arranged on the heat dissipation metal layer. And the other end of the second cooling pipeline is connected with the cooling pump, and the second cooling pipeline is used for recycling the cooling liquid from the heat dissipation metal layer to the cooling pump. According to the invention, on the premise of maintaining a high-temperature test environment of the tested module, efficient thermal isolation and heat dissipation control can be independently carried out on the controller area, and the temperature of the controller is ensured to be always in a safe range.

A test file generation method, apparatus and device, and a storage medium, the method comprising: analyzing a to-be-tested code file to obtain output information and input information in the to-be-tested code file; the input information is input into a case operation tested module to obtain output information after the case operation tested module outputs operation, and the output information after the operation comprises a code coverage rate; according to the output information after operation and preset output information, a comparison result is obtained, and the preset output information is expected information obtained through calculation according to the logic of the tested code and the input information; and performing output integration according to the comparison result and the code coverage rate, and generating a test file so as to be suitable for various embedded projects, so that the technical problem that the existing test file is tedious to use and not easy to understand is solved, and the effects of simplifying the use complexity and being easy to understand are realized.

The present invention discloses a kind of verification method of DMI-JTAG dual-end communication based on UVM, based on stimulus generation module, multiple driver modules, multiple monitors, comparator and DMI-JTAG module;The stimulus generation module generates the random instruction with constraint that meets JTAG protocol, produces the stimulus of JTAG terminal input, and when detecting that the generated JTAG terminal input is a read instruction, the response stimulus of DMI terminal is automatically generated and has been read back by JTAG terminal;Multiple driver modules drive the JTAG port and DMI port of DMI-JTAG module with the timing that meets JTAG protocol by the generated JTAG terminal input stimulus and DMI terminal input stimulus;Multiple monitors monitor the input and output of DMI-JTAG module and JTAG terminal;Comparator stores the input and output data of JTAG terminal and DMI terminal, and compares respectively.The present invention can verify DMI-JTAG module more conveniently, obtains the original stimulus with higher coverage, and supports input and output simultaneously at both ends of DMI-JTAG module under test.

The invention discloses a test method and system based on an XCP Ethernet, and belongs to the technical field of hardware-in-the-loop testing, the system comprises a test module, an upper computer module and a tested module, the test module and the tested module are in bidirectional electrical connection, the test module and the upper computer module are in bidirectional electrical connection, and the upper computer module is in bidirectional electrical connection with the tested module. The test module comprises a core board, a driving circuit, a processor chip and a programmable chip, the core board is bidirectionally and electrically connected with the driving circuit, the processor chip and the programmable chip are arranged on the core board, and the processor chip and the programmable chip can be bidirectionally connected through an internal system bus. The tested module comprises a controlled power supply module and a vehicle controller module. The XCP protocol stack is integrated in the test module, so that any upper computer software supporting the XCP protocol in the market can be communicated with the test device, on one hand, the development cost of the upper computer software is saved, the development period of the upper computer software is shortened, and on the other hand, the universality of the test device is improved.

Currently, complex FPGA designs typically contain multiple sub-modules below the top-level module. These modules ensure correct functional implementation, but because they are integral parts of the design, they are also subjected to gate-level behavioral simulation during simulation. If a module under test has one top-level module and nine sub-modules, seven of which are library or mature modules, and only two are newly designed modules, then only 30% of the gate-level behavioral simulation computation performed by EDA tools is truly for the part we want to verify. However, due to the existence of the top-level code and the need to verify the interface relationships between modules, the verification of sub-modules cannot replace the verification of the top-level module. If we could allow gate-level behavioral simulation to skip library and mature modules, it would significantly reduce the computational load of gate-level behavioral simulation and improve the speed of FPGA code functional simulation. This invention, for functional verification of FPGA code containing multiple sub-modules, uses a C model to replace the library IP modules or mature modules, preventing these modules from participating in the gate-level behavioral simulation during functional simulation execution, thereby significantly shortening the functional simulation execution time and accelerating the functional verification speed of FPGA code.

The invention provides an automatic test method for a communication module, and relates to the technical field of communication module testing, and the method comprises the steps: obtaining test response information fed back by a tested communication module; determining a configuration permission level when the tested communication module receives the test connection information in the current network mode according to the communication response log and the test response information; dynamically reconstructing a channel switching instruction for testing the tested communication module in the current network mode according to the communication quality identification code, and adjusting a frequency band switching interval of the tested communication module during communication through the channel switching instruction to obtain a dynamic response sequence of the tested communication module during frequency band switching; and automatically testing the network switching process of the tested communication module according to the configuration permission level and the dynamic response sequence. According to the invention, intelligent verification can be carried out on the network switching process of the communication module in the automatic test process, so that the test coverage rate of the communication module in a complex network environment is improved.

The invention provides a function security detection method of a laser radar chip, the chip and a laser radar, and the method comprises the steps: inputting test excitation data into a to-be-tested module of the laser radar chip, and obtaining test result data corresponding to each sub-module; whether the to-be-compared data corresponding to each sub-module is the same as preset expected result data or not is compared, a comparison result corresponding to each sub-module is obtained, the to-be-compared data is test result data corresponding to the sub-module or data obtained after preset processing is conducted based on the test result data, and each expected result data corresponds to one to-be-compared data; and determining whether the function of the to-be-tested module is abnormal or not according to the comparison result of each sub-module. According to the invention, whether the function of the laser radar chip is abnormal can be detected, thereby improving the personal safety and property safety of a user.

The present invention belongs to the field of circuit verification technology, and specifically relates to a dual-MCU-based internal module circuit verification method and system. The method includes a first MCU module sending a first EN signal to drive a circuit module under test to generate an internal signal. A process sampling module collects and samples the internal signal of the circuit module under test to obtain a first sampling signal. The first MCU module and the second MCU module compare and determine whether the first sampling signal is consistent with an expected signal. If they are consistent, it is determined that the circuit module under test is working normally. Otherwise, the first MCU module shuts down and sends a first EN signal. The second MCU module sends a second EN signal and a second signal signal to construct a second sampling signal. Based on the second sampling signal, the circuit module under test is sampled for a second time to obtain a new first sampling signal. Faults are determined based on the new first sampling signal. The present invention can achieve rapid judgment of circuit faults by performing self-calibration verification on the circuit.

This utility model discloses a modular substation testing system, relating to the field of power system automation technology. The system receives test data from the substation via a module under test (DUT). The data is amplified and filtered before being input to a signal conversion circuit, significantly reducing signal noise and loss during measurement. The system processes the data and analyzes the link establishment time. A successive approximation AD chip is then used for conversion. The system collaborates with a host computer to verify the data acquisition accuracy, focusing on circuit design optimization and detailed performance testing. This ensures the tested data can safely and quickly enter the monitoring state, enabling control and data storage of multiple test data sets. The combined data is then sent to the automated testing module for automated testing. This achieves automated testing control using artificial intelligence, improving the efficiency of automated testing.

The application discloses a kind of information processing method, device and application based on simulation waveform in chip simulation, it is related to chip development technical field.The method includes the following steps: obtaining the IP level simulation waveform file of the IP module to be measured;According to the simulation timing of IP level test case, the bus transmission signal is parsed, the change information of bus transmission state with time is obtained, whether the code conversion operation is triggered according to the change of the bus transmission state;When triggering code conversion operation, the corresponding bus configuration information is obtained according to the current bus transmission state, and the corresponding SoC level test case code is formed, and the SoC level test case code is used for the SoC interface bus configuration of the IP module to be measured.The application realizes the automatic conversion of interface bus configuration of test case in different verification environment, can improve the efficiency of transplanting test case in IP level verification environment, so as to shorten the chip development cycle.

The present invention provides an OTA stress test method, system, electronic device, and storage medium, which relate to the field of OTA stress testing. It includes responding to a test startup program, reading a test configuration file of the test startup program; generating multiple upgrade task packages according to the test configuration file parameters, and issuing them to the modules under test specified by the upgrade task packages respectively; repeatedly flashing the ECU according to the upgrade task package until the cumulative number of tests reaches a preset number of tests; obtaining the test results of each module under test, and generating a test report according to the test results. During the test process, the method of the present application can write a configuration file once, and independently test multiple modules under test at the same time. The tester does not need to operate each module under test separately, which reduces the work tasks of the tester, effectively increases the number of tests, and meets the sample quantity requirements of the OTA stress test.

A pressing device for double-sided water-cooling power module aging test equipment comprises a pressing water-cooling mechanism, a crimping suite, a water-cooling plate and a tray, and the pressing water-cooling mechanism firmly presses a power module to be tested by means of elastic force through cooperative work of a fixing terminal and a pressing terminal. The water cooling plate is connected with cooling water circulation through a water inlet and a water outlet so as to take away heat generated in the testing process, the crimping suite changes the crimping force of the crimping terminal on the power terminal of the tested module by adjusting the position of a nut, the water cooling plate is made of a high-thermal-conductivity metal material, and a telescopic heat-conducting interface material is attached to the water cooling plate. The micro gap between the water cooling plate and the power module to be tested is filled, the thermal resistance is reduced, and the heat conduction efficiency is improved. According to the utility model, the problems of compression and heat dissipation in the test of the double-sided water-cooling power module are solved, the test efficiency is remarkably improved through the highly automatic design, and a more efficient and reliable solution is provided for the aging test of the double-sided water-cooling power module.

The application relates to a starting method and device of a converter test system, the converter test system, a computer readable storage medium and a computer program product. The converter comprises a measured module and a measured module connected thereto; the converter test system comprises a power supply module for accessing an external DC voltage, and the power supply module is connected to the measured module and the measured module; the method comprises the following steps: in the case that the capacitor voltage of the power supply module reaches a preset first target voltage, controlling the power supply module to output a preset negative voltage to the measured module via the measured module to charge the measured module; in the case that the capacitor voltage of the measured module reaches a preset second target voltage, controlling the power supply module to output a positive voltage to the measured module, and controlling the measured module to output a measured voltage to the measured module to charge the measured module until the capacitor voltage of the measured module reaches a preset third target voltage, and the charging starting of the converter test system is completed. Therefore, the cost of the test system can be reduced.

The invention provides a test method and a test system, the test method and the test system are applied to a lower computer in the test system, the test system comprises the lower computer, an upper computer connected with the lower computer through a USB link and a tested module physically connected with the lower computer, and at least a daemon process and a production test process are deployed on the lower computer; the method comprises the steps that a daemon monitors whether a USB link has a hot plug event or not; if yes, the daemon process restarts the production testing process; after the production test process is restarted, the test instruction from the upper computer is received through the USB link, the tested module is tested according to the test instruction, the test result is obtained, the test result is sent to the upper computer through the USB link, and the production test efficiency is improved.

The application discloses an embedded power module test fixture and a manufacturing method thereof, relates to the technical field of semiconductor power module testing, and aims to solve the problem of large parasitic parameters of a test fixture and limited testing precision in the prior art. The test fixture comprises a probe card, spring needles, connecting lines and a crimping box. The probe card is a PCB circuit board on which a test circuit diagram is printed, and a needle sleeve, a threaded hole and a cable interface are reserved on the probe card. The spring needles are installed in place through the needle sleeve. One end of the connecting line is connected with the cable interface of the probe card, and the other end of the connecting line is connected with a testing machine. A reinforcing structural member is fixed to the back of the probe card through connecting screws. The crimping box is used for accommodating and fixing the probe card, and makes the welding pads of a measured module contact the spring needles through a crimping action to form a test loop. The application replaces the traditional manual wire welding connection with a PCB printed circuit, greatly reduces the parasitic inductance and resistance of the test loop, and improves the signal reliability.

The invention relates to the technical field of electronic design automation, in particular to an analog signal verification method for digital-analog hybrid simulation, which comprises the following steps: identifying a plurality of verification nodes in an analog module to be tested; configuring an analog-to-digital conversion threshold parameter for the verification node; in a simulation process, monitoring an analog signal value on the verification node in real time, and converting the analog signal value into a digital logic value according to an analog-to-digital conversion threshold parameter; transmitting the digital logic value to a digital verification platform through an emulator interface; the digital verification platform applies the digital logic value to a digital shadow model corresponding to the tested analog module interface; function coverage collection and assertion check are performed based on the signals of the digital shadow model. According to the method, the problem that analog signals cannot be effectively verified through traditional digital-analog hybrid simulation is solved, verification completeness is remarkably improved, design errors can be automatically found in the early stage, existing digital verification platform resources are fully reused, and verification efficiency and reliability of a mixed signal chip are greatly improved.

The invention discloses a module IO port test and diagnosis automation system and method. The system is composed of a module IO detection tool, a to-be-detected module adapter plate and a computer terminal. The module IO detection tool integrates an MCU, an analog multiplexer, a level conversion chip, an LDO and other modules, the module adapter plate to be detected adopts a one-plate multi-adaptation design, and the computer terminal issues a control instruction through a serial port. The system can realize module IO output detection, input detection and diagnosis of influence of IO port pull-up or pull-down on module downloading and starting, and covers multiple links of research and development testing, production pre-testing and after-sales analysis. The method can adapt to various modules without replacing a detection tool, is high in automation degree, and meets the requirements of multi-scene detection.

The invention provides a fault positioning method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the power-on processing of a connected tested module through a power module, and operating the tested module, and enabling the tested module to comprise a plurality of instrumentation codes; in the process that the tested module is in the power-on state, obtaining operation results of a plurality of instrumentation codes in the tested module; if it is determined that the tested module has an operation fault according to the operation result, fault positioning is carried out on the tested module according to the operation result; or if it is determined that the tested module does not have the operation fault according to the operation result, the power supply module is controlled to carry out power-off processing on the tested module. According to the application, automatic power-on and power-off processing of the tested module can be realized, fault positioning can be carried out on the tested module when the tested module is kept in a power-on state, the fault positioning efficiency is improved, and the fault positioning accuracy is improved by carrying out fault positioning through the operation result.

The invention discloses a PCIE (Peripheral Component Interface Express) transmission rate and packet loss rate automatic test method, which comprises the following steps of: customizing a data packet for communication between two tested PCIE modules and a test instruction between test equipment and the tested PCIE modules; a data transmission rate and packet loss rate test program between tested modules and a data instruction interaction program between the test equipment and the tested modules are designed based on a self-defined data packet and a test instruction, and communication instruction transceiving between the test equipment and the tested modules is realized by using an external communication port of the tested modules. Therefore, the test equipment can set the size and the period of the test data and feed back the data transmission rate and the packet loss rate result.

The present invention discloses a test temperature control device and method. The device includes: an incubator for providing a base temperature, where the base temperature is lower than the target temperature; a module under test placed in the incubator and generating heat by itself; a heating module in contact with the module under test and not working initially; a temperature sensor for detecting the temperature of the module under test. When the temperature of the module under test is higher than the target temperature, the incubator reduces the base temperature, the heating module does not work and acts as a radiator due to being in contact with the module under test. When the temperature of the module under test is lower than the target temperature, the heating module starts to work to heat the module under test until the temperature of the module under test reaches the target temperature and stops heating after the temperature of the module under test reaches the target temperature. When the temperature of the module under test is lower than the target temperature by a certain margin, the heating module continues to work to heat the module under test until the temperature of the module under test reaches the target temperature, and this process is repeated continuously. The temperature control of the present invention is more accurate.

The utility model provides a LoRaWAN module test fixture and a LoRaWAN module test system. The test fixture comprises a first communication interface converter, a second communication interface converter, an adapter plate and a LoRaWAN gateway. The first communication interface converter and the second communication interface converter are respectively connected with an upper computer; the first communication interface converter is also connected with the adapter plate; the adapter plate is also connected with the LoRaWAN module to be tested; and the second communication interface converter is connected with the LoRaWAN gateway. According to the utility model, factory testing (including performance testing and pin header testing) and setting of the LoRaWAN module can be automatically completed in a highly integrated manner, and the testing and setting efficiency is remarkably improved.

The invention discloses a pre-call-based test case generation method and device, a medium and equipment. The method comprises the following steps: firstly, collecting a function module contained in a tested program, an execution path of the tested function module and a path constraint corresponding to the execution path, and then randomly generating a pre-call sequence according to the function module contained in the tested program; the method comprises the following steps of: calculating a path constraint evaluation value on a specified execution path after executing each function module of a front call sequence in sequence through scaling random values of input parameters of each function module of the front call sequence and input parameters of each tested function module; and finally, judging whether the parameter sample obtained by random value obtaining can realize reachability judgment of an execution path or not according to the path constraint evaluation value, and if the execution path is reachability, outputting the preposed call sequence and the parameter sample as a test case, thereby obtaining a test result used for testing the tested function module. And the test case set of each execution path of the tested function module can be covered.

The present invention provides a PCIe interrupt verification system, method and device, relating to the technical field of PCIe interrupt verification. The verification system mainly includes: in a UVM verification environment, a comparison module and a module under test are constructed; the module under test includes a PCIe system under test; the PCIe system under test includes a plurality of ports; the ports include interrupt status registers; the comparison module is connected to the module under test through transaction-level modeling, and is used to trigger an interrupt for the module under test according to input parameters; collect the interrupt messages of the module under test, perform interrupt status comparison and interrupt clearing operations, and output a verification result. This solution can comprehensively and automatically combine the trigger and clearing mechanisms of various interrupt sources, thereby restoring the real usage scenario, and simply and reliably realizing system-level interrupt verification; this solution can effectively reduce the verification cost of PCIe switch system interrupt verification, and improve the verification efficiency and verification effect.

This invention discloses an intelligent testing method for FPGA interconnect resources at the billion-gate level, belonging to the field of FPGA testing. The method involves identifying the module under test (DUT) of the internal interconnect resources of the FPGA; extracting its physical connection point information from the XDLRC resource file of the DUT; modeling and parameterizing the physical connection points, presenting the results in a graph dictionary; searching for the optimal routing path based on the graph dictionary, generating a configuration graph, and performing ATE testing to determine if the tested path has any faults. This invention extracts the FPGA's XDLRC resource file, analyzes the structural characteristics of the interconnects, and optimizes the modeling process based on the determinacy of the interconnect metal lines' positions, transforming the interconnect metal lines into points in a mathematical graph model. Compared to the previous modeling optimization, the modeling space is compressed by nearly 50%, and the routing search time is also reduced accordingly. An improved depth-first search algorithm is used, enabling the search function to be implemented with concise code, and parameterized information is added to the search dictionary object.

The invention discloses a method and a device for detecting a core component of a shield tunneling machine, and the method comprises the steps: in a valve group-sensor test mode, controlling a to-be-tested solenoid valve of a relay to act according to a valve group test action instruction, and judging whether the solenoid valve is normal or not according to the state and action of a valve head lamp of the solenoid valve; 4 mA to 20 mA sensing signals of the sensor are obtained, the sensing signals are fed back to the upper computer, a logic operation result is obtained after preset logic operation is conducted through the upper computer, and whether the sensor is normal or not is judged according to the displayed logic operation result; in the PLC module test mode, the tested module is used as a slave station and communicates with the master station control module so as to execute a digital quantity input module test, a digital quantity output module test, an analog quantity input module test and an analog quantity output module test; the DP / NET communication test mode comprises an encoder test sub-mode and a remote controller test sub-mode. Quality problems and assembly problems of electrical core components of the shield tunneling machine can be found in advance, faults can be checked in time, and the quality and efficiency during joint debugging of the whole machine are guaranteed.