47 results about "Module under test" patented technology

This invention belongs to the field of wireless communication module production testing technology, and discloses a parallel testing method and system for wireless modules based on fixed-channel broadcast communication. Applied to a factory production testing environment, the method includes: powering on and initializing multiple modules under test (DUTs) on the same panel, and uniformly setting them to a fixed wireless communication mode and channel according to their workstation addresses; setting up a wireless companion device, which operates on the same fixed mode and channel as the DUTs; the companion device cyclically sending specific broadcast test messages; each DUT, upon receiving a broadcast message, reports a response message to the host computer of the tooling; the host computer determines whether the wireless function of the DUT at that workstation is qualified based on whether it receives a correct response message from the corresponding workstation. This method achieves parallel testing at multiple workstations through a one-to-many broadcast communication mode, improving production efficiency and effectively reducing the problem of wireless co-channel interference during simultaneous testing at multiple workstations.

The invention discloses an energy-consuming valve power module cyclic aging test platform and a cyclic aging test method, which are suitable for reliability verification of a direct-current energy-consuming device power module. Through collaborative design of a capacitive power supply and an inductive load, closed-loop utilization of energy is realized, and modularized alternating test logic is adopted, so that the test efficiency is improved. A direct-current power supply is used for providing a current source for a test loop, a test object is a test valve section formed by connecting a plurality of power module units in series, the test loop is composed of two test valve sections, and the two test valve sections are tested objects mutually. The design of the series energy consumption valve power module enables a plurality of tested modules to be subjected to cyclic aging at the same time. According to the invention, the power circulation of the energy consumption branch can be realized, and the data obtained through the test can be applied to key scenes such as health condition evaluation and control logic judgment of the IGCT device.

The utility model relates to a cooling device of a test board and the test board, the test board is provided with a test area and a controller installation area, the cooling device comprises an insulation heat conduction silica gel pad, a heat dissipation metal layer, a first cooling pipeline, a second cooling pipeline and a cooling pump, the insulation heat conduction silica gel pad is arranged on a controller, and the heat dissipation metal layer is arranged on the first cooling pipeline. The heat dissipation metal layer is arranged on the insulating heat conduction silica gel pad, one end of the first cooling pipeline is arranged on the heat dissipation metal layer, the other end of the first cooling pipeline is connected with the cooling pump, the first cooling pipeline is used for providing cooling liquid for the heat dissipation metal layer under the action of the cooling pump, and one end of the second cooling pipeline is arranged on the heat dissipation metal layer. And the other end of the second cooling pipeline is connected with the cooling pump, and the second cooling pipeline is used for recycling the cooling liquid from the heat dissipation metal layer to the cooling pump. According to the invention, on the premise of maintaining a high-temperature test environment of the tested module, efficient thermal isolation and heat dissipation control can be independently carried out on the controller area, and the temperature of the controller is ensured to be always in a safe range.

A test file generation method, apparatus and device, and a storage medium, the method comprising: analyzing a to-be-tested code file to obtain output information and input information in the to-be-tested code file; the input information is input into a case operation tested module to obtain output information after the case operation tested module outputs operation, and the output information after the operation comprises a code coverage rate; according to the output information after operation and preset output information, a comparison result is obtained, and the preset output information is expected information obtained through calculation according to the logic of the tested code and the input information; and performing output integration according to the comparison result and the code coverage rate, and generating a test file so as to be suitable for various embedded projects, so that the technical problem that the existing test file is tedious to use and not easy to understand is solved, and the effects of simplifying the use complexity and being easy to understand are realized.

The invention discloses a test method and system based on an XCP Ethernet, and belongs to the technical field of hardware-in-the-loop testing, the system comprises a test module, an upper computer module and a tested module, the test module and the tested module are in bidirectional electrical connection, the test module and the upper computer module are in bidirectional electrical connection, and the upper computer module is in bidirectional electrical connection with the tested module. The test module comprises a core board, a driving circuit, a processor chip and a programmable chip, the core board is bidirectionally and electrically connected with the driving circuit, the processor chip and the programmable chip are arranged on the core board, and the processor chip and the programmable chip can be bidirectionally connected through an internal system bus. The tested module comprises a controlled power supply module and a vehicle controller module. The XCP protocol stack is integrated in the test module, so that any upper computer software supporting the XCP protocol in the market can be communicated with the test device, on one hand, the development cost of the upper computer software is saved, the development period of the upper computer software is shortened, and on the other hand, the universality of the test device is improved.

This utility model discloses a modular substation testing system, relating to the field of power system automation technology. The system receives test data from the substation via a module under test (DUT). The data is amplified and filtered before being input to a signal conversion circuit, significantly reducing signal noise and loss during measurement. The system processes the data and analyzes the link establishment time. A successive approximation AD chip is then used for conversion. The system collaborates with a host computer to verify the data acquisition accuracy, focusing on circuit design optimization and detailed performance testing. This ensures the tested data can safely and quickly enter the monitoring state, enabling control and data storage of multiple test data sets. The combined data is then sent to the automated testing module for automated testing. This achieves automated testing control using artificial intelligence, improving the efficiency of automated testing.

The application discloses a kind of information processing method, device and application based on simulation waveform in chip simulation, it is related to chip development technical field.The method includes the following steps: obtaining the IP level simulation waveform file of the IP module to be measured;According to the simulation timing of IP level test case, the bus transmission signal is parsed, the change information of bus transmission state with time is obtained, whether the code conversion operation is triggered according to the change of the bus transmission state;When triggering code conversion operation, the corresponding bus configuration information is obtained according to the current bus transmission state, and the corresponding SoC level test case code is formed, and the SoC level test case code is used for the SoC interface bus configuration of the IP module to be measured.The application realizes the automatic conversion of interface bus configuration of test case in different verification environment, can improve the efficiency of transplanting test case in IP level verification environment, so as to shorten the chip development cycle.

The application relates to a starting method and device of a converter test system, the converter test system, a computer readable storage medium and a computer program product. The converter comprises a measured module and a measured module connected thereto; the converter test system comprises a power supply module for accessing an external DC voltage, and the power supply module is connected to the measured module and the measured module; the method comprises the following steps: in the case that the capacitor voltage of the power supply module reaches a preset first target voltage, controlling the power supply module to output a preset negative voltage to the measured module via the measured module to charge the measured module; in the case that the capacitor voltage of the measured module reaches a preset second target voltage, controlling the power supply module to output a positive voltage to the measured module, and controlling the measured module to output a measured voltage to the measured module to charge the measured module until the capacitor voltage of the measured module reaches a preset third target voltage, and the charging starting of the converter test system is completed. Therefore, the cost of the test system can be reduced.

The invention provides a test method and a test system, the test method and the test system are applied to a lower computer in the test system, the test system comprises the lower computer, an upper computer connected with the lower computer through a USB link and a tested module physically connected with the lower computer, and at least a daemon process and a production test process are deployed on the lower computer; the method comprises the steps that a daemon monitors whether a USB link has a hot plug event or not; if yes, the daemon process restarts the production testing process; after the production test process is restarted, the test instruction from the upper computer is received through the USB link, the tested module is tested according to the test instruction, the test result is obtained, the test result is sent to the upper computer through the USB link, and the production test efficiency is improved.

The application discloses an embedded power module test fixture and a manufacturing method thereof, relates to the technical field of semiconductor power module testing, and aims to solve the problem of large parasitic parameters of a test fixture and limited testing precision in the prior art. The test fixture comprises a probe card, spring needles, connecting lines and a crimping box. The probe card is a PCB circuit board on which a test circuit diagram is printed, and a needle sleeve, a threaded hole and a cable interface are reserved on the probe card. The spring needles are installed in place through the needle sleeve. One end of the connecting line is connected with the cable interface of the probe card, and the other end of the connecting line is connected with a testing machine. A reinforcing structural member is fixed to the back of the probe card through connecting screws. The crimping box is used for accommodating and fixing the probe card, and makes the welding pads of a measured module contact the spring needles through a crimping action to form a test loop. The application replaces the traditional manual wire welding connection with a PCB printed circuit, greatly reduces the parasitic inductance and resistance of the test loop, and improves the signal reliability.

The invention relates to the technical field of electronic design automation, in particular to an analog signal verification method for digital-analog hybrid simulation, which comprises the following steps: identifying a plurality of verification nodes in an analog module to be tested; configuring an analog-to-digital conversion threshold parameter for the verification node; in a simulation process, monitoring an analog signal value on the verification node in real time, and converting the analog signal value into a digital logic value according to an analog-to-digital conversion threshold parameter; transmitting the digital logic value to a digital verification platform through an emulator interface; the digital verification platform applies the digital logic value to a digital shadow model corresponding to the tested analog module interface; function coverage collection and assertion check are performed based on the signals of the digital shadow model. According to the method, the problem that analog signals cannot be effectively verified through traditional digital-analog hybrid simulation is solved, verification completeness is remarkably improved, design errors can be automatically found in the early stage, existing digital verification platform resources are fully reused, and verification efficiency and reliability of a mixed signal chip are greatly improved.

The invention discloses a module IO port test and diagnosis automation system and method. The system is composed of a module IO detection tool, a to-be-detected module adapter plate and a computer terminal. The module IO detection tool integrates an MCU, an analog multiplexer, a level conversion chip, an LDO and other modules, the module adapter plate to be detected adopts a one-plate multi-adaptation design, and the computer terminal issues a control instruction through a serial port. The system can realize module IO output detection, input detection and diagnosis of influence of IO port pull-up or pull-down on module downloading and starting, and covers multiple links of research and development testing, production pre-testing and after-sales analysis. The method can adapt to various modules without replacing a detection tool, is high in automation degree, and meets the requirements of multi-scene detection.

The invention discloses a pre-call-based test case generation method and device, a medium and equipment. The method comprises the following steps: firstly, collecting a function module contained in a tested program, an execution path of the tested function module and a path constraint corresponding to the execution path, and then randomly generating a pre-call sequence according to the function module contained in the tested program; the method comprises the following steps of: calculating a path constraint evaluation value on a specified execution path after executing each function module of a front call sequence in sequence through scaling random values of input parameters of each function module of the front call sequence and input parameters of each tested function module; and finally, judging whether the parameter sample obtained by random value obtaining can realize reachability judgment of an execution path or not according to the path constraint evaluation value, and if the execution path is reachability, outputting the preposed call sequence and the parameter sample as a test case, thereby obtaining a test result used for testing the tested function module. And the test case set of each execution path of the tested function module can be covered.

This invention discloses an intelligent testing method for FPGA interconnect resources at the billion-gate level, belonging to the field of FPGA testing. The method involves identifying the module under test (DUT) of the internal interconnect resources of the FPGA; extracting its physical connection point information from the XDLRC resource file of the DUT; modeling and parameterizing the physical connection points, presenting the results in a graph dictionary; searching for the optimal routing path based on the graph dictionary, generating a configuration graph, and performing ATE testing to determine if the tested path has any faults. This invention extracts the FPGA's XDLRC resource file, analyzes the structural characteristics of the interconnects, and optimizes the modeling process based on the determinacy of the interconnect metal lines' positions, transforming the interconnect metal lines into points in a mathematical graph model. Compared to the previous modeling optimization, the modeling space is compressed by nearly 50%, and the routing search time is also reduced accordingly. An improved depth-first search algorithm is used, enabling the search function to be implemented with concise code, and parameterized information is added to the search dictionary object.

The application discloses a platformized test method and device, electronic equipment, medium and program product, and belongs to the technical field of hardware testing. The method comprises the following steps: configuring test parameters of a tested module, and saving the test parameters in extensible markup language format data; analyzing the extensible markup language format data, and converting test information in the extensible markup language format data into dictionary form data; traversing the dictionary form data, and determining a test parameter list of the tested module; and executing a test case according to the test parameter list, so as to realize the test of the tested module. The tested module in different projects can be converted into the test parameter list in the foregoing manner. When testing, the test case is executed according to the test parameter list, and it is not necessary to manually modify test case parameters. The same module in different projects can be tested by using the same test case, and the platformization of the test case is realized.

The invention relates to a full-automatic test method for railway navigation data storage. The method comprises the steps that a test tool receives current and carries out current conversion; the upper computer sends a switching instruction to the lower computer, and after the USB flash disk is switched to the upper computer, the upper computer empties USB flash disk data and writes test specimen data and a configuration file; switching to the tested module again, and after the tested module reads the configuration file, writing the test specimen data and automatically restarting; switching to the upper computer again, emptying U disk data, and then sending simulation navigation data to the tested module; after sending, switching to the tested module, and storing the stored simulation navigation data into the USB flash disk by the tested module; and after the transmission is finished, the upper computer sends a switching instruction to the lower computer, so that the USB flash disk switch is switched to the upper computer, the stored simulation navigation data is read, comparison is carried out, and result information is output. Compared with the prior art, the system has the advantages of being high in testing capacity and good in system integration.

The utility model relates to the technical field of optical communication, in particular to a portable miniaturized module three-temperature test fixture, which comprises a fixture base, a fixture upper cover arranged at the upper end of the fixture base, a fixture bracket arranged at the lower end of the fixture base, a temperature sensing line pressing rod arranged at the upper end of the fixture upper cover, and a tested module arranged at one end of the fixture upper cover. A test board high-frequency line is arranged at the lower end of the clamp base, air supply is achieved through the direct-through external air pipe installed on the clamp, the size of the clamp is greatly reduced, the overall size of the clamp is 190 mm in length, 150 mm in width and 120 mm in height, the clamp is convenient to carry and disassemble while the module research and development test requirement is met, and under the condition that the test clamp is assembled, the test efficiency is greatly improved. According to the utility model, plugging of the tested optical module and contact of the temperature sensing probe can be completed only by inserting the tested module to the bottom and pressing the temperature sensing line pressing rod, the inner wall of the clamp upper cover is a limiting surface of the tested module, the module touches the limiting surface after being directly inserted to the bottom, and the reliability of pins of the socket of the test board is protected.

This application discloses a method, apparatus, and equipment for testing the performance of a humanoid robot joint module, relating to the field of robotics technology. The method includes: acquiring the identity identifier of the joint module under test; loading corresponding standard test procedures and digital twin models from the cloud based on the identity identifier; controlling the test platform to execute an automated test sequence based on the standard test procedures; synchronously collecting multimodal performance data of the joint module under test through multiple sensors and recording corresponding timestamps; running a lightweight AI model in real time through an edge computing unit to perform preliminary analysis of the multimodal performance data and adjust the test strategy based on the preliminary analysis results; uploading the multimodal performance data with the identity identifier and timestamps to a cloud data lake; performing in-depth analysis of the multimodal performance data through a cloud-based AI analysis engine to generate a test report. This application achieves intelligent testing by constructing an "edge-cloud" collaborative intelligent testing system.

The invention belongs to the technical field of signal transceiving unit test fixtures, and particularly relates to a signal transceiving unit test fixture and an operation method thereof. A mounting surface is arranged on a bottom plate; the guide rails are fixedly mounted on the mounting surface of the bottom plate and are in one-to-one correspondence with the external interfaces, and the axes of guide rail grooves in the guide rails are parallel to the axes of the external interfaces; the longitudinal section of the guide rail groove is an isosceles trapezoid, and the included angle between two waist extension lines is 10-20 degrees; the thickness of the to-be-detected module is greater than the minimum distance of the guide rail grooves and less than the maximum distance of the guide rail grooves; the positioning blocks are fixedly mounted on the left and right sides of the front end of the bottom plate and are used for positioning the test fixture and test equipment; and the locking frame is arranged at the rear end of the bottom plate and is used for locking the test fixture and the workbench. According to the test fixture, interconnection between the signal modulation module and the PXI case and between the signal demodulation module and the PXI case is rapidly achieved, multiple modules can be tested at the same time at a time, the test efficiency is high, and the heat dissipation requirement can be met by installing a heat dissipation fan.

This invention discloses a method, apparatus, device, medium, and program product for chip smoke testing. It includes: acquiring the requirements information of the module under test (DUT); constructing a DUT model based on the DUT requirements information; the DUT model being a behavioral-level functional model; driving the DUT model into the DUT chip design; and performing smoke testing on the DUT chip design. This method meets the standards for IP area evaluation while satisfying the quality requirements for integrating and verifying different IPs on a SoC. It allows for earlier smoke testing of the DUT chip design, advancing the involvement time of the physical design team, significantly compressing the development cycle, and accelerating the overall chip project development progress.

This application relates to the field of joint module testing technology, and more particularly to a load-bearing integrated testing system for integrated joint modules. The main body consists of a temperature chamber and a main control system. The temperature chamber integrates a test circuit and a sensor array. The test circuit is connected to the electrical interface of the joint module under test. The sensor array includes a temperature sensor and a torque sensor. The main control system is configured to execute an automatic scheduling program and a sensor compensation program, matching the test task according to a temperature cycle stage matching rule base, and controlling the test circuit according to the test task. During the temperature environment simulation task and the test task, when the temperature cycle stage is in the cooling phase, the temperature sensor readings are dynamically compensated first; when the test task includes applying a load to the joint module, the torque sensor readings are dynamically compensated secondly. This achieves parallelization and dynamic scheduling of the testing process, while solving the problem of weak dynamic interference suppression capability in existing technologies.

The present application relates to the field of integrated circuit technology, in particular to a FPGA logic resource test method and structure based on a new BIST, comprising the following steps: determining the measured module BUT and comparison module BUC of the internal resource of the FPGA to be measured; designing the BIST circuit structure based on the hardware description language, namely: designing the test vector generator TPG, measured module BUT, comparison module BUC and output response analyzer ORA four modules of the BIST circuit based on the hardware description language through the EDA design software of the FPGA; constraining the measured module BUT and comparison module BUC modules, namely: position constraint is conducted on the measured module BUT and comparison module BUC based on the EDA design software of the FPGA; generating and downloading the bit stream file and conducting the real installation board level test verification. The present application is used for solving the problems of low test efficiency, too many test configuration times, complex built-in self-test structure, test sequence generated by TPG not random or random but not covering the full address and weak generalization of the existing FPGA internal resource test.

The invention belongs to the technical field of automatic test and safety protection, and particularly relates to an HIL automatic test system based on multipath optical coupling isolation relay protection, which comprises an HIL automatic test cabinet, an IO board card and an IO measurement board card are integrated in the HIL automatic test cabinet, and a tested module is arranged in a test circuit between the IO board card and the IO measurement board card. The HIL automatic test cabinet is connected with the power supply module in an external control manner, the multiple groups of optical coupling isolation relay modules are connected in parallel on multiple channels of the IO board card, and each group of optical coupling isolation relay module is also connected in series between the power supply module and the tested module. The optical coupling isolation relay module replaces the IO board card to work in the test of the tested module so as to realize complete isolation protection of the IO board card, and meanwhile, surge protection of the IO measurement board card is realized in a shunting mode, so that a high-precision control mode and a millisecond-level response function of the system are reserved, and the overall load capacity of the system is improved on the basis of low cost.

This invention discloses a testbench simulation verification platform and system, comprising: a stimulus database for collecting and storing simulation source data; upon receiving a parameter configuration instruction from the module under test, determining the stimulus content corresponding to the configuration parameters, and outputting the stimulus content through a parameter interface; the stimulus content being used for simulation testing of the module under test; and a data conversion module for acquiring the output signal of the module under test and converting the output signal into response content in a preset format according to conversion rules. This invention simplifies the simulation process, reduces manual intervention, improves the automation and accuracy of simulation testing, and effectively enhances testing efficiency and reusability.

The embodiment of the invention provides a core particle verification method and device, a medium, a core particle and a computing system, and relates to the technical field of chips. The core particle verification method can be applied to a verification module, and the verification module comprises a preset verification model and a data acquisition interface connected with a tested module in a core particle. The core grain verification method comprises the following steps: acquiring a target message that a core grain communicates with other core grains through a tested module, wherein the target message is a message conforming to a general core grain interconnection standard; under the condition that the target message meets a preset condition, collecting algorithm data of a target calibration algorithm executed by the tested module in a link training process through a data collection interface; and verifying the target calibration algorithm according to the verification model and the algorithm data to obtain a verification result of the target calibration algorithm. Therefore, the calibration algorithm can be verified, and algorithm logic or parameter errors can be found in time, so that the reliability of core particle verification is improved.

This invention relates to a testing device for testing a module under test (DUT). The DUT includes a body and first and second terminals respectively located on both sides of the body. The testing device includes a fixture, a base, and a first testing assembly. The first testing assembly includes a capacitor, a first test piece, and a second test piece. The first test piece includes a horizontally arranged first crimping portion, and the second test piece includes a horizontally arranged second crimping portion. The second crimping portion is stacked on top of the first crimping portion, and the length of the second crimping portion is greater than the length of the first crimping portion. When the base is close to the bearing position, the first crimping portion is crimped onto the first terminal, and the second crimping portion is crimped onto the second terminal to adapt to the DUT with positive and negative terminals respectively located on both sides of the body, while ensuring low interference in the circuit and ensuring the accuracy of the test results.

This invention relates to the field of module testing technology, specifically disclosing an intelligent testing system and method for TFT modules based on multimodal sensing, comprising the following steps: Step S1: Applying electrical excitation to the TFT module under test, and simultaneously acquiring its response electrical signal, optical image of the display area, and temperature distribution data of the working surface under excitation; Step S2: Preprocessing and spatiotemporally aligning the response electrical signal, optical image of the display area, and temperature distribution data of the working surface, and extracting a fusion feature set that simultaneously reflects electrical performance, optical uniformity, and thermal stability through correlation analysis; Step S3: Inputting the fusion feature set into a pre-trained prediction model, wherein the prediction model adopts a long short-term memory network architecture to analyze the evolution law of the fusion features in time series, and outputting the probability that the TFT module has at least one preset defect type; Step S4: Generating an intelligent test report.

This application provides a performance analysis method, apparatus, electronic device, chip, and medium, relating to the field of chip design and development. The method includes: generating at least one set of test configuration schemes based on the performance requirements of the module under test and a preset performance scenario; performing performance simulation of the module under test under the preset performance scenario in parallel based on the at least one set of test configuration schemes to trigger at least one target performance event and acquire at least one performance data point through a preset performance monitoring unit; quantifying and analyzing the at least one performance data point to obtain performance analysis results under the preset performance scenario; and updating at least one set of test configuration schemes based on the performance bottleneck when the performance analysis results show a performance bottleneck, thereby determining the optimal configuration parameters of the optimal test configuration scheme based on the updated at least one set of test configuration schemes. This improves performance tuning efficiency, reduces development cycle and labor costs, and ensures that the module under test achieves optimal resource allocation while meeting performance targets.

The invention relates to a passive checking method and device for an out-of-order instruction transmitting module. The method is applied to an instruction transmitting model and comprises the steps that an instruction distributed to a to-be-tested out-of-order instruction transmitting module by an instruction distribution module is monitored, a transmitting queue of the instruction transmitting model is filled with the instruction, and the instruction carries unique identification information; monitoring a first target instruction transmitted to an instruction execution module by an out-of-order instruction transmitting module; obtaining a second target instruction which is the same as the unique identification information of the first target instruction from an emission queue of an instruction emission model; transmitting the second target instruction in an instruction transmitting model; and checking the out-of-order instruction transmitting module according to the transmitting result of the second target instruction. Through the method provided by the embodiment of the invention, the workload and difficulty of model development are reduced, and when the instruction transmitted by the out-of-order instruction transmitting module has an error, the error instruction and the error occurrence time can be reported immediately, so that the convenience of error debugging is improved.