FPGA (Field Programmable Gate Array) online verification structure and method based on serial communication interface

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) online verification structure and a method based on a serial communication interface. The structure comprises a software simulation environment, a hardware test environment and a physical channel, wherein the software simulation environment is configured to be in signal interaction with the hardware test environment through the physical channel; the software simulation environment produces test vectors and debug commands of a bus cycle, and receives a feedback signal to display in a wave way; the hardware test environment receives the test vectors and the debug commands, and sends the feedback signal. The verification structure and the method not only can effectively provide an FPGA online verification platform and simulate a working process of an integrated circuit module or a chip, but also has the characteristic of platform reusability, and are not designed aiming at a specific module; in addition, verification personnel can intuitively monitor and configure the port state of a module to be tested.

Description

technical field [0001] The invention relates to FPGA simulation debugging technology, in particular to an FPGA online verification structure and method based on a serial communication interface. Background technique [0002] With the continuous innovation of integrated circuit design methods and the continuous improvement of chip manufacturing technology, its functions are becoming more and more powerful, and the difficulty and complexity of design are also increasing. The integrated circuit has entered the SoC stage from the ASIC stage. SoC refers to a system on a chip that integrates functions such as MCU, DSP, analog and digital circuits, memory, I / O interface, signal acquisition and conversion on a single chip. The functions of signal acquisition, conversion, processing, storage, input and output are completed on the chip, thus greatly reducing the space occupation of the system, reducing the communication delay between multiple chips, and improving the performance of th...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to overcome the poor configurability of the verification platform, the low efficiency of the incentive monitoring mechanism and the reusability of the verification platform, and provide a FPGA online verification structure and method based on a serial communication interface. The verification structure and method can be effective Provide an FPGA online verification platform that simulates the working process of integrated circuit modules or chips, and has the characteristics of platform reusability. It is not designed for specific modules, and verification personnel can intuitively monitor and configure the port status of the module under test.

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