68 results about "Software emulation" patented technology

The invention relates to the technical field of software simulation operation simulation, and discloses a software logic simulation operation control method and system in an audio processor. The control method is applied to logic simulation operation control equipment and specifically comprises the following steps that S101, an audio processor simulation operation request sent by a user side is received, a graphical user interface is generated according to the operation request, and the graphical user interface comprises a logic module list area, a design editing area, an attribute bar and an information display area; and the user side drags an icon of a logic circuit element from the logic module list area to the design editing area. Through a highly integrated graphical interface and intelligent interactive design, the design and simulation efficiency of an audio processor logic circuit is remarkably improved, and by adopting a'drag-and-generate 'module instantiation mechanism, an attribute bidirectional real-time synchronization technology and visual connection and signal type inspection, the reliability of the audio processor logic circuit is greatly improved. Therefore, the user can intuitively and quickly construct the complex circuit topology, and the professional threshold is greatly reduced.

The invention provides an automatic simulation test system and method for a semiconductor EAP system, and belongs to the field of semiconductor manufacturing, and the method specifically comprises the steps: defining a test scene through test case coding; constructing a test environment by using the equipment simulation module and the external system simulation module; driving a test process of the tested EAP program through an automatic execution engine and generating real-time output data corresponding to the tested EAP program; and comparing the real-time output data generated by the automatic execution engine with an expected result, and generating a test report. According to the processing scheme, behaviors of equipment and an external system are truly simulated in a software simulation mode, an actual production scene is accurately restored in a test link, dependence on a physical environment is reduced, and test coverage is improved; and moreover, the test scene is solidified through codes and configuration files, so that the versioning management and one-key automatic regression test of the test cases are realized, the test efficiency is remarkably improved, and the quality of secondary development is guaranteed.

The invention discloses a single-stroke breakpoint-free path planning method for a 3D printing variable-wall-thickness honeycomb structure, and the method comprises the following steps: determining the stress distribution condition of an equal-wall-thickness honeycomb structure continuous carbon fiber reinforced silicon carbide ceramic-based composite material through software simulation, and determining a weakest region and a weakest region; variable-wall-thickness honeycomb printing is arranged in the weakest area and the weaker area; the side length and the offset distance of the honeycomb unit are determined, and a 3D printing path is set, specifically, the odd-number-layer path is different from the even-number-layer path, the outer contours of the honeycomb unit are sequentially printed in the vertical direction through the odd-number-layer path, the honeycomb unit does not completely pass through each honeycomb wall of the honeycomb structure, and the honeycomb structure is not completely formed after printing is completed; and when the next even-numbered layer is printed, missing honeycomb walls of the upper odd-numbered layer are passed twice, so that the missing honeycomb walls are complemented, and a complete variable-wall-thickness honeycomb structure is formed. According to the method, weak spots are effectively strengthened in a targeted mode, the material is not prone to damage, and the mechanical property is remarkably improved.

The invention discloses an industrial simulation control method and system based on natural language driving, and belongs to the technical field of industrial simulation. According to an existing industrial simulation control scheme, how to transmit simulation parameters into simulation software is not disclosed, and setting of simulation instructions cannot be completed. According to the industrial simulation control method based on natural language driving, a natural language instruction input by a user is analyzed by constructing a simulation language recognition model, an interaction channel creation model and an instruction mapping model, and a simulation driving channel is established between industrial simulation software and the simulation language recognition model; standardized transmission and cross-platform data interaction of data and commands are realized, and instruction transmission and data sharing are facilitated; and further based on the instruction protocol conversion relationship, the operation command is converted to obtain the execution message, so that automatic setting of different software simulation instructions can be realized, the compatibility and integration problems among different simulation platforms are effectively solved, and the user experience is improved.

The invention provides a glass bottle lightweight forming process optimization system, belongs to the technical field of glass product production, and solves the technical problems that the existing lightweight glass bottle is low in forming efficiency, process parameters cannot be dynamically adapted and the like. Comprising a hardware execution module, a global data sensing module, a digital twinning optimization module, an enterprise-level cloud management module and a man-machine collaborative operation and maintenance module. The global data sensing module comprises an equipment three-dimensional information scanning and collecting unit, an equipment working state sensor network unit, an energy consumption and resource monitoring unit, a data transmission unit, a data storage unit and a carbon footprint accounting unit; the digital twinning optimization module comprises a virtual simulation unit, a software simulation optimization unit and a dynamic feedback optimization unit. According to the invention, an integrated process optimization system integrating an intelligent algorithm, digital twinning, green carbon reduction, flexible production, full-dimensional detection, predictive maintenance and man-machine collaboration is adopted, and efficient, accurate, green and flexible production of lightweight glass bottles is realized.

The invention discloses a digital chip verification method and device, electronic equipment and a computer readable storage medium, the method and device are applied to a verification system, the verification system comprises a software simulation platform and a hardware verification platform, and the method comprises the following steps: determining a to-be-tested code of a target digital chip; utilizing the software simulation platform to generate an excitation signal according to the to-be-tested code, and sending the excitation signal to a hardware verification platform; executing verification operation on the target digital chip by using the hardware verification platform according to the excitation signal to obtain a hardware verification result; when the hardware verification result has abnormal information, determining an abnormal node in the to-be-tested code, and debugging at the abnormal node by using a software simulation platform to obtain a software simulation result; and determining a final verification result of the target digital chip according to the hardware verification result and the software simulation result. By applying the technical scheme provided by the invention, more flexible and efficient digital chip verification can be realized.

This application relates to the technical field of voltage regulation function testing for power banks. It discloses a voltage regulation function simulation testing system and method. This application constructs a voltage regulation function simulation testing system including a simulation clock and a simulation cycle counter. At the software level, it directly simulates the passage of time and the accumulation of charge-discharge cycles during long-term battery use based on user-configured test parameters. The core algorithm layer uses simulation time and / or the number of simulated full-charge cycles to simulate the charging voltage of the power bank over time and the accumulation of charge-discharge cycles, thus completing the voltage regulation function simulation test of the power bank. This method of completing the voltage regulation function simulation test of a power bank through software simulation algorithms greatly reduces the physical testing time required without changing the physical testing environment or replacing the tested object. This significantly shortens the testing cycle while ensuring the test results accurately reflect real-world usage scenarios and have high reliability.

The embodiments of the present application provide a chip simulation test method, device, equipment and system. The chip simulation test method includes: using a hardware simulation system to simulate the first part of the chip running the design program, and performing at least one sampling to obtain at least one sampling data; loading the at least one sampling data into the software simulation system; the software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on the at least one sampling data, so as to simulate the chip running the design program. The embodiment of the present application executes part of the program in the hardware simulation system, and the software simulation system continues to execute the design program based on the collected data, so that there is no need to actually execute the entire process of the design program. The hardware simulation system and the software simulation system can be combined to achieve efficient analysis and debugging, thereby providing good guidance for chip design.

The application provides a process engine-based autonomous operation method and system for an interoperability verification task, a virtual-real combined simulation environment is constructed by including field equipment operation data, laboratory scaled component state information and a software simulation model, an actual operation scene of a road electromechanical equipment interoperability mechanism is simulated, an interoperability verification task is generated according to a preset verification requirement parameter set, a process engine is called to analyze the task and plan an execution process, the task is executed in the virtual-real combined simulation environment according to the execution process, message transmission data, state response data and time synchronization data in the equipment interaction process are collected in real time, interoperability verification results including interaction message integrity description, state response consistency record and time synchronization accuracy description are generated based on the message transmission data, the state response data and the time synchronization data, so that the verification task can be autonomously planned, and a comprehensive and real test environment is provided.

According to the HIC function verification method and verification device, an EMC module with mature functions is arranged in a FLASH space of a CPU subsystem on an original SOC verification platform, and the EMC module is configured as an external host of an HIC module, so that a function verification platform of the HIC module is rapidly established, and no extra chip is needed. After grammar checking and instantiation are carried out on an HIC function verification platform by adopting a VCS command, a VCSrun command is executed to load a simulation file and a test routine to execute function simulation, and a verdei command is used for checking a simulation result, so that RTL codes of an HIC module can be modified, re-edited and re-simulated when BUG or other errors occur, the whole process is carried out in software simulation, and the simulation efficiency is improved. The time consumption of the FPGA process is avoided, and the interaction function of the HIC module and the external host and the function interaction of the HIC module and the internal resources of the SOC system are verified at the same time in the real and complete SOC environment.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The invention provides a steering knuckle structure optimization method and device, a storage medium and an electronic device.The method comprises the steps that CAE simulation is conducted on an initial steering knuckle under multiple design working conditions, and a first coordinate result matrix is obtained through solving; determining a performance parameter set of the initial steering knuckle; adopting the performance parameter set to construct a design safety threshold value of structure optimization; respectively carrying out CAE simulation on the middle steering knuckle under a plurality of design working conditions, and solving to obtain a second coordinate result matrix; calculating according to the second coordinate result matrix and a design safety threshold to obtain a threshold solution domain; and adopting the threshold solution domain and the first coordinate result matrix to calculate and obtain a target coordinate matrix of mass distribution of the target knuckle after structure optimization. Through the embodiment of the invention, the technical problem that the structure of the steering knuckle cannot be optimized through software simulation in the prior art is solved, the design quality is minimized, the size of the steering knuckle is reduced, and the material and the cost of the steering knuckle are saved.

The invention discloses a real-time simulation online automatic analysis system which comprises a man-machine interaction workstation, a real-time simulation machine, a tested object and a module development workstation. Wherein the man-machine interaction work station is used for providing a man-machine interaction environment for software simulation testing; the real-time simulation machine is used for realizing automatic judgment and analysis functions of a software simulation test; the model development workstation is used for developing a simulation model required by the real-time simulation machine; and the tested object is used as a test object for the real-time simulation machine to automatically judge and analyze the test criterion.

The invention discloses a graph processor modeling and analyzing method and device, and belongs to the field of computer system structure aided design. The method comprises the following steps: establishing a unified calculation model decoupled from a storage architecture model; full-link micro-architecture behavior data is obtained through FPGA actual measurement, and a bandwidth constraint model is constructed to determine the optimal parallelism degree of a calculation unit; carrying out closed-loop calibration on bus delay and internal logic parameters of the simulation model by utilizing measured data; and on the calibrated reference model, keeping the optimal parallelism unchanged, and carrying out space evaluation and performance quantitative analysis on various storage architecture schemes. The device comprises an upper computer, an FPGA hardware platform and a communication interface assembly, wherein system-level simulation software and hardware control software are integrated on the upper computer. According to the method, by constructing a software and hardware closed-loop cooperation mechanism, the problems that the degree of parallelism is difficult to reasonably determine and the simulation precision of pure software is insufficient are solved, and high-precision and high-efficiency evaluation of the calculation subsystem and the storage subsystem of the graph processor is realized.

The invention relates to a simulation method and a simulation device for simulating an integrated circuit chip. Based on the method and the device, the idle flag sequence can be dynamically maintained for the plurality of software modules, the idle flag sequence can comprise the idle flag bits corresponding to the plurality of software modules, when the idle flag bit corresponding to each software module is set to be valid, the idle flag bit can indicate that the to-be-processed data waiting for being processed by the software module at present is empty, and moreover, the idle flag bit corresponding to the software module can indicate that the to-be-processed data waiting for being processed by the software module at present. Before the software thread calls any software module, the idle flag bit of the software module can be detected firstly, and then whether the software module is called or not is determined according to the detection result. Therefore, invalid calling of the software module can be prevented from being executed under the condition that any software module does not involve the to-be-processed data of data interaction, so that the software simulation time consumption of the integrated circuit chip can be shortened by reducing the invalid calling of the software module.

The present invention relates to a hardware-based device and method for accelerating legacy software emulation comprising the steps of: disassembling a legacy software code recognising one or more instructions; translating the recognised instructions into an intermediate form by means of substitution tables comprising instruction prefixes; determining execution efficiency by means of at least one performance counter that stores data of the instructions in intermediate form; applying IT security techniques in the instructions in intermediate form; applying execution optimisation techniques of the legacy software code by rearranging and substituting acceleration pattern-based instructions using pre-defined substitution blocks; and translating the instructions in intermediate form into a microcode specific to a machine.

The application discloses a software simulation environment building method, device, medium and program product, and relates to the field of software development. The software simulation environment building method comprises the following steps: obtaining a network resource arrangement instruction; arranging target managed resources according to the network resource arrangement instruction to obtain a target environment network topology; configuring a node image file according to the target environment network topology to obtain a network topology to be instantiated; and performing code testing and verification according to target test code, the network topology to be instantiated and topology node usage state data. The technical scheme of the embodiment of the application can improve the building efficiency of a software development simulation environment and break the strong dependence of simulation environment building and instantiation on manpower.

The invention relates to the technical field of software simulation control, in particular to an intelligent large-screen software control system and method based on distributed seat management. The system comprises a situation virtualization module which is used for receiving real state data or simulator operation data and constructing a virtual copy; the self-adaptive strategy execution module is used for extracting a situation evolution trend vector according to the virtual copy, judging situation state classification and generating a dynamic instruction set; the distributed virtual environment coordination module is used for receiving the dynamic instruction set, adjusting a user interface and managing user interaction authority; the simulation management module is used for controlling the process of the simulator and synchronizing the running data of the simulator to the situation virtualization module; and the unified interaction module is used for carrying out mode state switching on the operation environment and constraining the user interaction operation according to the permission change instruction.

The invention discloses a job-level parallel performance comprehensive measurement method for a heterogeneous system, and relates to the technical field of performance measurement. Comprising the following steps: obtaining static characteristics, micro-architecture characteristics and job-level operation characteristics of software, and extracting corresponding performance characteristic data; selecting a machine learning model, and setting software simulation data to train and optimize the model to obtain a software performance model; testing the software to generate a throughput curve, and analyzing the throughput curve by using the expandability model to obtain an expandability index; constructing a speed-up ratio model based on the Amdall law; and constructing a measurement model about the performance model, the expandability model and the speed-up ratio model, inputting to-be-predicted software parameters into the measurement model, and weighting generated data to obtain a software comprehensive performance measurement index. According to the method, comprehensive and accurate evaluation on the parallel performance of the software operation in the heterogeneous system is realized.

The invention relates to the technical field of scientific calculation visualization, and discloses a post-processing method and system for a CAE software simulation calculation result, and the method mainly comprises the following steps: (1) reading the CAE software simulation calculation result, and verifying parameters in the CAE software simulation calculation result; (2) analyzing simulation data calculated by the CAE software, and splitting the data into data sets; (3) establishing a mapping relation between the data set and the post-processing visual component; (4) configuring data filters possibly existing in the mapping relation; and (5) the visual interface is edited by utilizing a visual editor according to requirements, so that the assemblies with different functions are combined more flexibly, and the effect of meeting different business requirement interfaces can be quickly formed.

The application belongs to the field of coherent synthesis, and discloses a multi-channel laser coherent synthesis SPGD algorithm verification platform based on FPGA, which is used for solving the problem that the MATALAB software simulation SPGD algorithm is not accurate, and the simulation system of the application combines software and hardware, first, the SPGD algorithm and related simulation modules are deployed into the FPGA board card; then, the software simulation light path is established in the computer; subsequently, the FPGA is connected with the computer through the gigabit Ethernet interface to establish the data interaction channel; then, the internal parameters of the SPGD algorithm are set by sending instructions from the computer to the FPGA, and the SPGD algorithm simulation is started; after that, the positive and negative voltage values calculated by the SPGD algorithm are sent to the computer, and after the positive and negative voltage data are received by the computer software simulation light path, the ADC data are calculated and sent to the FPGA; finally, the simulation of the SPGD algorithm is realized through the cyclic data interaction between the FPGA and the computer. The method of the application can simulate the simulation of the SPGD algorithm under complex experimental environment, improve the accuracy of the simulation, and increase the success rate of the experiment.

The invention discloses a computing resource adjustment method and device, electronic equipment, a storage medium and a product. The method is applied to a containerized cluster and comprises the steps that a target container pool is created according to a task running request, a software simulation task is deployed to the target container pool, and the target container pool runs the software simulation task; in the running process of the software simulation task, obtaining a task running log of the software simulation task and resource use data of the target container pool, and determining a task running stage of the software simulation task according to the task running log and the resource use data; if the resource usage data exceeds a resource occupation upper limit corresponding to the task operation stage, determining target configuration information corresponding to the target container pool so as to expand the target container pool according to the target configuration information. According to the technical scheme, the effects that the software simulation task is operated based on the containerized cluster, and the container pool resources are dynamically adjusted according to the task operation condition in the task operation process so as to adapt to the resource requirements in the task operation stage are achieved.

The present invention discloses a virtual-real integration ship energy management strategy verification method, comprising: performing a joint simulation based on AMESim-Simulink, debugging and correcting model parameters; compiling the ship energy management strategy model into corresponding code and downloading it to a controller; compiling the interface S-function function in Simulink, generating real-time code from the model, downloading the model to dSPACE, and combining it with the controller for real-time simulation; materializing part of the power system simulation model, applying the actual working conditions of the ship to the load simulation system, constructing a virtual test scenario that conforms to reality, and performing hardware-in-the-loop simulation testing that integrates virtual and real; comparing the results of software simulation, real-time simulation, and hardware-in-the-loop simulation, and evaluating and verifying them according to preset indicators. The present invention effectively integrates the software simulation model and the small-scale verification platform, and the verification of the ship energy management strategy can be performed in any virtual model or platform device, with flexible operation, which can effectively reduce costs and improve verification efficiency.

The invention discloses a software integration publishing method, system and equipment. The method comprises the following steps: acquiring a software simulation model and a corresponding change file in real time; building and updating the software simulation model based on the change file to obtain a simulation update model; testing the simulation updating model, confirming a preset detection item, compiling and integrating the simulation updating model, and generating a corresponding integrated software package; the integrated software package is released through the continuous delivery port; a software simulation model and a change file are obtained through a Gitlab software system, the software simulation model is constructed and updated, a simulation update model is tested through a Matlab Simulink software system, software integration is carried out after it is confirmed that the simulation update model conforms to a detection item, an integrated software package is automatically generated and released, the software integration release process is simplified, errors caused by manual operation are reduced, and the software integration release efficiency is improved. The publishing efficiency is remarkably improved, mistakenly entering a development environment is avoided, and the stability and reliability of software integration are improved.

The application belongs to the technical field of integrated circuits, and particularly relates to a software and hardware joint simulation platform for processor chip architecture verification. The software and hardware joint simulation platform is an architecture crossing hardware and software; the software part comprises a scheduling module, a submission module, an acquisition module, an execution task table and four annular lock-free queues; the hardware part comprises a data packet preprocessing module, a signal conversion module and two queues. The simulation platform adopts a parallel simulation form of a software simulator and hardware FPGA, simplifies a traditional development process, and allows a hardware core module to directly and cooperatively simulate a software simulated processor chip. The software simulated processor chip can directly provide a real test environment for the hardware core and has rapid simulation capability, thereby improving the integration efficiency of a newly developed or iterated hardware core module in an existing large-scale processor chip.

The invention discloses a programmable controller comprehensive training platform, which relates to the technical field of industrial automation technology training equipment and comprises a hardware practical training platform and a virtual simulation practical training platform. The power supply module, the core control module, the function debugging module and the communication networking module are integrated on the practical training platform body. The virtual simulation practical training platform comprises simulation practical training software running on computing equipment, and the simulation practical training software performs data interaction with the hardware practical training platform through a communication networking module; the core control module comprises a programmable logic controller, and external input and output wires of the programmable logic controller are led out in a visual open wire mode. The function debugging module comprises electric appliance element units which can be freely combined and is used for being connected with the core control module to construct an actual control system; the objective of the invention is to achieve the purposes that a learner visually cognizes an electrical system, constructs hardware according to needs, and completes PLC system installation and debugging and troubleshooting practical training.

The invention relates to the field of drive-by-wire product development, and discloses a drive-by-wire product software development and iterative cross test verification device and method.The drive-by-wire product software development and iterative cross test verification device comprises a rack used for installing test equipment, and an EHB actuator is arranged on the outer side of the rack; an EMB actuator is arranged on the inner side of the rack; the system further comprises a software simulation system, a chassis domain controller and a pedal sensor used for inputting signals to the chassis domain controller. The test system comprises an EMB sub-test system, an EHB sub-test system and an HBBW sub-test system; the test system is connected with the EMB actuator, or the EHB actuator, or the EMB actuator and the EHB actuator according to actual test items; the upper computer is in communication connection with the test system, the software simulation system, the chassis domain controller and the electronic sensor for information interaction. The system can realize multi-working-condition and multi-product cooperative work, the research and development efficiency is improved, and the research and development cost is saved.

The invention provides a method for designing a neuromorphic computing chip of a mesoscopic olfactory neural network, which can be used for constructing a multi-channel parallel computing and storage and computing integrated neuromorphic computing chip. The technical problems that in existing software simulation, a neural network describing dynamics through a differential equation is poor in expansibility, low in calculation speed, incapable of conducting real-time processing and the like are solved. The method comprises the following steps: step 1, constructing a digital logic calculation model of a K0 model of a Friemann K series set of an olfactory neural network; 2, constructing a nonlinear transfer function of the K0 model; 3, constructing a main state machine and a sub-state machine of the K0 model; step 4, constructing a KI network and a KII network; and step 5, constructing a KIII network.

The invention provides a performance analysis method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a test instruction sequence, and converting the test instruction sequence into a physical signal and a program calling signal; the test instruction sequence comprises a plurality of test instructions, and the test instructions are used for testing the function of the to-be-tested design; the physical signal is matched with a hardware simulation model to be tested and designed; the program calling signal is matched with a to-be-tested designed software simulation model; driving a hardware simulation model of the to-be-tested design to operate according to the physical signal to obtain first operation performance data of the to-be-tested design; driving a software simulation model of the to-be-tested design to run according to the program calling signal to obtain second running performance data of the to-be-tested design; and determining a performance analysis result of the to-be-tested design according to the first operation performance data and the second operation performance data. According to the embodiment of the invention, the total project period can be shortened, the performance analysis efficiency is improved, and the performance analysis complexity is reduced.

The invention discloses an electric power system sample imbalance correction method based on a correction gradient direction, and the method comprises the steps: 1), obtaining a large number of training samples through PSD-BPA software simulation, extracting the power angle and speed deviation of each generator in an electric power system as characteristic quantities, and constructing an original transient stability evaluation sample set with the stability of the samples as labels; 2) constructing stable samples and unstable samples into a sample set according to a set proportion, and standardizing the samples in the sample set; 3) according to the direction propagation process in the training process of the stacked sparse automatic encoder, respectively calculating the synthetic gradients of the stable sample, the unstable sample and the total sample; and 4) adjusting the total gradient direction to the bisecting gradient direction of the stable sample and the unstable sample, and then carrying out a back propagation process. According to the method, the tendency problem of TSA model evaluation caused by different unbalance degrees can be adaptively corrected, and compared with a traditional method, the method has a better correction effect and is suitable for further popularization and application.