23 results about "Hardware abstraction" patented technology

Implementations are described herein for detecting deepfakes in digital media while preserving the privacy of the source computing device. In various implementations, sensor fingerprints and / or security tokens that signal software-introduced alterations, e.g., introduced by hardware abstraction layers (HALs) or virtual machines (VMs) may be utilized to detect such deepfakes. These signals may be used, separately and / or in combination, for various purposes, such as flagging digital content to a user as being a deepfake, preventing or blocking receipt and / or playback of digital content deemed to be a deepfake, allowing an end user to disable aspect(s) (e.g., layers) of digital content that are determined to be synthetic, etc.

An agent is deployed on an computing system to modify performance characteristics associated with servicing workloads independent of underlying hardware of the computing system. A service tier to be used for servicing workloads for a particular client by the computing system is received. An indication of the service tier to be used for servicing the workloads for the particular client is transmitted to the computing system. The indication causes the agent to modify the performance characteristics of the computing system when servicing the workloads in accordance with the service tier.

The invention is suitable for the technical field of computer system starting, and provides an OpenSBI starting method and system of an RISC-V SoC based on an FPGA, the system comprises a hardware abstraction layer, a boot loading layer, a privilege management layer and a kernel execution layer, and each layer realizes data interaction and process connection through a standardized interface; through the hierarchical design of FPGA hardware initialization, SPL / U-Boot firmware loading, OpenSBI privileged mode configuration and kernel startup, modular management of a startup process is realized, the system coupling degree is reduced, multiple storage medium and operating system types are supported, hardware abstraction is realized through an OpenSBI standard interface, subsequent extension of new peripherals or upgrading of an RISC-V architecture version is facilitated, and the development of the RISC-V architecture is facilitated. The standardized starting process reduces the adaptation workload of hardware and firmware, and debugging and rapid iterative development are facilitated.

The present invention provides a high-performance microservice execution environment for hybrid operation of software microservices and hardware microservices. Various microservices implemented based on software and hardware can be integrated through microservice orchestration to achieve a high-performance application system. In particular, by integrating modules implemented based on hardware, the data processing ability of the application can be improved, and the difficulty of building a high-performance application can be simplified. In application fields such as smart cities, compute-intensive and data-intensive tasks have become common computing requirements. Application systems based on the microservice architecture are simple, flexible, and highly available. However, for compute-intensive applications, development still needs to be carried out for dedicated acceleration devices. To effectively utilize the hardware acceleration capability, the hardware needs to be abstracted into microservice modules and can interact with other services to achieve application construction and simplify the application customization process. This invention proposes a microservice operation environment that combines software and hardware. By defining a common interaction interface, it provides service discovery, service proxy, concurrent access control, and solves the management problem of hardware microservices compared to software microservices, realizing a general microservice operation environment and improving the overall operation efficiency of the system for building a computing power platform for smart cities.

This application provides a multimodal automatic testing system and method, relating to the field of industrial process control system testing technology. The multimodal automatic testing system includes a computing and control unit, a PXI chassis, a signal conditioning chassis, an interface connection unit, a power supply unit, and a human-machine interaction unit. The system is equipped with an automatic testing software platform, including modules for test case management, script generation and parsing, hardware abstraction and channel mapping, signal generation and scheduling, data acquisition and result judgment, log recording and report generation, and human-machine interaction and control. This application can achieve unified simulation and acquisition of multimodal signals on a single platform, featuring high testing accuracy, high automation, strong versatility, and cross-platform adaptability, effectively improving the coverage and execution efficiency of domestically produced DCS platform testing.

The invention relates to the technical field of low codes, in particular to a low-code service configuration engine and a configuration method thereof. The device comprises a relation unit execution module used for defining and executing an input-operation-output relation unit; the JSON configuration analysis module is used for analyzing a configuration file in a JSON format, the configuration file comprises version information, variable initialization configuration and task configuration, and system behaviors are defined in a declarative configuration mode; the hardware abstract interface module is used for providing an operation interface irrelevant to hardware and realizing complete abstraction of hardware operation through a callback mechanism; the backup storage module is used for storing and backing up the configuration file by adopting two storage slots, and each storage slot is provided with a configurable storage space; and the real-time multi-task execution module is used for task scheduling and execution based on RTOS and supports multi-task parallel execution, conditional branching and loop control. According to the invention, the development complexity of the industrial control system is reduced, and non-technical personnel can quickly configure complex control logic.

The invention relates to the technical field of airborne system hardware abstraction, and discloses a hardware abstraction method and system for an airborne system, computer equipment and a medium, and the method comprises the steps: abstracting each physical equipment in the airborne system from different types of physical equipment into abstract equipment with the same interface, shielding the physical difference between different types of equipment, and improving the hardware abstraction efficiency. And forming the same abstract device with the same function. And meanwhile, analyzing and counting the interfaces of different types of physical equipment of each type of physical equipment to form a group of uniform interfaces of the abstract equipment. For the upper software, the method shields the physical difference of different hardware of different manufacturers, obviously improves the development efficiency and cross-platform portability of the upper software, and facilitates the development and transplantation of the upper software; for manufacturers, the method unifies the interface requirements of different models of aircrafts, and facilitates formation of lineage design and research and development of products with unified functions and different performances.

The invention provides a hardware abstraction layer reconstruction method and device based on a programmable logic platform, and the method comprises the steps: obtaining a GPIO pin level combination of an extension module, decoding the GPIO pin level combination to obtain an equipment type identifier, activating a corresponding peripheral sub-module in a unified peripheral IP logic module, carrying out the drive mapping table searching and initialization configuration of a target peripheral logic unit, and carrying out the hardware abstraction layer reconstruction. And finally, parameter configuration is carried out through an AXI-Lite control bus, and data transmission is carried out through an AXI-Stream data bus and an AXI-DMA module. According to the method, a complete closed-loop process of plug-and-identification, identification-and-drive and drive-and-use is realized, the technical problems that in a traditional programmable logic platform, manual drive configuration is needed for module expansion, and a unified hardware abstraction mechanism is lacked are solved, and a solution which is efficient, low in cost and friendly to beginners is provided for teaching.

The invention provides a multi-dimensional self-adaptive large model inference engine method and system, and relates to the technical field of artificial intelligence, and the method comprises the steps: collecting hardware identification information of calculation hardware, and calling a hardware fingerprint database for matching to generate a hardware type result and a hardware characteristic parameter; constructing a hardware abstraction layer, loading a hardware abstraction driving plug-in according to a hardware type result, and virtualizing computing hardware into a unified logic computing power unit through a hardware abstraction interface; when a large model reasoning task is triggered, dynamically routing to a back-end executor according to a hardware type result by querying a back-end registry; on the basis of hardware characteristic parameters and a hardware abstract interface, a hardware compiling tool chain is called through a rear-end executor, graph optimization and operator fusion are executed on a large model calculation graph, and therefore self-adaptive deployment and efficient reasoning of a large model on heterogeneous hardware can be achieved; the problems that in the prior art, heterogeneous hardware is insufficient in compatibility, configuration is tedious and rigid, and compilation optimization barriers and performance losses are caused during model cross-platform migration are solved.

The invention discloses a robot operating system based on KaiHong OS, a robot control method, computer equipment and a medium. The system comprises an operating system layer, a middle layer and an application layer, the operating system layer adopts a KaiHong OS and provides hardware abstraction, bottom layer driving, bottom layer task scheduling, compiling and equipment driving functions; the middle layer is used for carrying out secondary packaging on the operating system layer and providing standard interfaces which are uniform in format and modularized; and the application layer manages the whole robot operating system through the node manager, and splits and combines the functions of the robot operating system by taking nodes as units. According to the method, the KaiHong OS is used as the OS layer support of the robot operating system, the KaiHong OS is connected with the underlying hardware, the KaiHong OS is operated on the computer hardware, an application layer is kept unchanged, a developer can conveniently develop the robot on the KaiHong OS, and the development efficiency of the robot is improved.

The embodiment of the invention provides a cross-platform component adaptation method and related equipment, and belongs to the technical field of terminals. The method comprises the following steps: acquiring hardware feature data and interface definition data; the hardware feature data and the interface definition data are from a plurality of data sources; the hardware feature data and the interface definition data originate from components configured across platforms; performing data processing on the hardware feature data and the interface definition data to respectively obtain a hardware abstract model and an adaptive descriptor; inputting the hardware abstract model and the adaptive descriptor into a driving rule matching engine, and generating a code driving template according to the hardware abstract model and the adaptive descriptor through the driving rule matching engine; and generating a corresponding deployment driving code according to the code driving template. According to the embodiment of the invention, the automation degree and reliability of transplanting the component between different devices and operating systems can be effectively improved while the workload required by manually writing the bottom driver is reduced.

This application relates to a method for generating cross-architecture computationally intensive fusion operators based on hardware abstraction. It constrains and determines the operator subgraph according to preset legality rules, establishes a unified semantic abstraction, defines the fusion operator as a coordinate-driven pure function, and encapsulates auxiliary tensor memory access handles and layout geometry information through runtime context. A backend normalization layer is used to semantically reinterpret the accumulator layout and thread organization of different hardware vendors during compile time, and cross-platform vectorization primitives are invoked to mask the differences in backend instruction set architectures. Arithmetic logic is downgraded to a sequence of instructions executed within a scalar scope. The abstract vector view is first decomposed into independent scalar elements, arithmetic instructions are generated in the scalar dimension, the calculation results are then reorganized into a vector register, and finally, an address expression is constructed by deriving the effective step size to handle broadcast and indexing logic, generating fusion code that can access the underlying vendor's computationally intensive kernel, thus improving development efficiency.

The invention discloses a multi-device cooperation system for a conference system, and relates to the technical field of comprehensive communication, the multi-device cooperation system comprises an application layer, a core abstraction layer, a driving layer, a kernel layer and a hardware layer, the application layer operates conference application software, the core abstraction layer is a unified hardware abstraction interface layer, and provides a standardized device interface for the application layer; the driving layer and the kernel layer provide hardware driving, a dynamic priority allocation algorithm, an interrupt response and memory sharing mechanism and CPU / co-processing resource scheduling, and the hardware layer comprises a camera, a microphone, a sound box and an FPGA acceleration chip; the method has the advantages that multi-thread communication delay is effectively reduced, system fluency is guaranteed, multi-device cooperation efficiency of the conference machine in a real-time video cooperation scene is improved, high-resolution video streams and low-delay audio transmission are supported, and audio and picture synchronization errors are reduced.

The present application relates to the field of data communication detection technology, and in particular to a fuzzy dynamic scheduling data communication detection system based on a virtual-real interaction scenario, wherein the system comprises a hardware interface layer, a data interaction layer, and a simulation application layer; a hardware abstraction interface module is deployed in the hardware interface layer; a dynamic priority scheduler, a lightweight binary encoder, and an adaptive transmission controller are set in the data interaction layer, and the simulation application layer is connected to the simulation platform through a timestamp synchronization mechanism; wherein the data flow is designed based on a bidirectional ring buffer structure, the raw data received by the hardware interface layer is stored in the input buffer after verification, the data interaction layer extracts the data from the buffer, processes it, and sends it to the simulation application layer, and the feedback instruction is sent to the actuator through the reverse path. Thus, the problems of protocol redundancy, low resource efficiency, and insufficient dynamic adaptability in the prior art are solved.

The application relates to the technical field of robot performance control, in particular to a multi-channel dance collection and playing system based on unified time base and double-path scheduling, which comprises a unified time base collection module, a double-path playing scheduling module and a hardware abstract adaptation module; the unified time base collection module is used for taking a monotone clock as a reference to establish a timestamp binding relationship for action data and audio files of all execution channels; the double-path playing scheduling module supports two playing paths of multi-thread concurrency and single-thread sequence, and can automatically optimize a thread model according to the number of channels; the hardware abstract adaptation module realizes automatic identification and driving adaptation of different hardware devices through a defined unified interface and an adapter mode. Through audio clock main driving and unified time base mapping, the time base deviation is controlled within 5 ms in 2 hours of continuous operation, the synchronization error is reduced by 65% compared with a traditional scheme, and the application has the advantages of high-precision synchronization, flexible adaptation and safety and reliability.

The invention discloses a game behavior processor of an embedded AI processing unit, which adopts a heterogeneous computing architecture to realize task unloading and cooperative processing, and comprises a hardware acceleration layer which integrates a CPU (Central Processing Unit), an NPU (Network Processing Unit), a GPU (Graphic Processing Unit) and a computing power resource pool of a special DSP (Digital Signal Processor); the intelligent behavior processing stack comprises an input layer, a memory and emotion layer, a core logic layer and an execution layer which are connected in sequence; the cross-layer security monitoring layer is used for covering a security protection and exception handling mechanism of the whole stack; wherein the hardware acceleration layer provides computing power scheduling support for the intelligent behavior processing stack through a hardware abstract interface. According to the method, revolutionary upgrading of a game embedded system is achieved through heterogeneous computing architecture reconstruction and dynamic energy efficiency scheduling, a closed loop based on emotion computing and a mixed decision architecture are adopted, traditional game AI mechanical limitation is broken through, game behaviors are made to better fit emotion logic, and the sense of reality and immersion of AI roles are enhanced.

The embodiment of the present application provides a method for constructing a hardware abstraction layer of a chip platform, the method comprising: scanning the hardware feature information of the chip platform, constructing a hardware feature analysis model, classifying and annotating the hardware feature information to extract device interfaces, resource attributes and operation features, establishing a feature vector library of hardware components, and using a hierarchical clustering algorithm to group the hardware components to form a function category tree; training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters to generate a hardware abstraction rule library; loading the hardware abstraction rule library in a hardware abstraction layer engine, dynamically monitoring resource usage status and updating allocation strategies, and returning hardware operation results to the application layer through a unified interface; the present application can deeply understand hardware features, construct an intelligent interface encapsulation strategy, and realize efficient resource scheduling through technologies such as reinforcement learning.

The invention relates to a hardware perception-based Transform model hierarchical reasoning framework, the framework comprises a framework adaptation layer, a scheduling layer, a communication adaptation layer and a hardware support layer, and the specific implementation method comprises the following steps: step 1, hardware abstraction is carried out; 2, initializing the model adapter; and step 3, carrying out model layering combination according to the hardware capability and the model structure. And 4, dynamically optimizing the hierarchical reasoning plan and checking before execution. And step 5, uniformly collecting intermediate results generated by each device in a scheduling layer. According to the method, unified abstract modeling is carried out on the heterogeneous hardware environment, and the hierarchical structure characteristics of the Transform model are combined, so that cross-device dynamic hierarchical combined reasoning is realized. Through the six steps, deep fusion between the Transform model structure and the hardware capability is realized, so that model reasoning can realize high throughput, low delay and high stability in a complex and dynamic multi-device environment.

The application is suitable for the technical field of computer system starting, and provides an OpenSBI starting method and system of a RISC-V SoC based on FPGA, the system comprises a hardware abstraction layer, a boot loading layer, a privilege management layer and a kernel execution layer, and each layer realizes data interaction and process connection through a standardized interface; through the layered design of FPGA hardware initialization, SPL / U-Boot firmware loading, OpenSBI privilege mode configuration and kernel starting, the modular management of the starting process is realized, the system coupling degree is reduced, various storage media and operating system types are supported, the hardware abstraction is realized through the OpenSBI standard interface, it is convenient to extend new peripherals or upgrade the RISC-V architecture version in the future, the standardized starting process reduces the adaptation workload of hardware and firmware, and it is convenient to debug and quickly iterate and develop.

This disclosure relates generally to framework for simulation and cross-platform deployment of a Spiking Neural Network (SNN). models In conventional approach, SNN model created in hardware-agnostic framework suffer performance issues when deployed in a hardware-specific platform as the current standards for interoperability of the models among multiple frameworks maps only interfaces and does not consider difference in behavior due to different order of atomic computations, decay rates of current and voltage, and the reset mechanisms for membrane potential. The present disclosure overcomes this by creating a hardware abstract library having different flavors of middleware synaptic neuron corresponding to different hardware-specific software frameworks. The variation due to decay rates of current and voltage, and the reset mechanisms for membrane potential are determined and atomic instructions are parameterized using the variations. The hardware abstract library is created for each hardware-specific software framework by determining an order of execution of the atomic instructions.

The invention relates to a method for realizing an in-memory computing standard extension instruction set based on an RISC-V instruction set, which comprises the following steps: a programming model realization step: abstracting in-memory computing hardware into a software-visible architecture register by adopting a hierarchical decoupling mode, the architecture register comprises a storage register for mapping internal storage into a two-dimensional data layout and a calculation register for mapping an in-storage calculation cluster into a three-dimensional data layout; and an instruction set implementation step: converting hardware abstraction and interface specifications in the programming model into commands which can be executed by hardware through specific instructions and operation codes. According to the hierarchical decoupling programming model, upper-layer compiling and lower-layer micro-architecture implementation can be independently developed, the software stack development cost and difficulty are reduced, and the hardware development and iteration process is accelerated. Due to the unified programming model, different in-memory computing hardware designs can adopt the same abstract operator library and compiling tool chain, and the portability and reusability of codes are improved.

The application relates to a hardware abstraction-based tensor calculation compilation optimization method and system, and the method comprises the following steps: a hardware model is constructed to describe hardware-related information; an optimization abstraction method commonly used in operator optimization is constructed, the backend optimization of an operator by a compiler is decomposed into flexible combinations of a plurality of optimization abstraction methods; based on the hardware model and optimization abstraction method selection rules, a suitable optimization abstraction method combination is selected, a code generation skeleton is constructed; parameters in the code skeleton which are not determined are searched, a parameter search space is pruned by using the hardware model, and the pruned optional parameters are saved; and target code suitable for a target calculation platform is generated according to an intermediate representation after optimization by using the optimization abstraction method. Compared with the prior art, the application has strong adaptability, a flexible optimization mechanism and efficient tuning capability, and is particularly suitable for executing high-performance tensor calculation tasks on a multi-heterogeneous calculation platform.

The application discloses a multi-platform hardware-aware adaptive quantization system, comprising a unified hardware abstraction module, a model analysis module, a multi-objective Pareto optimization module, a constraint satisfaction solving module, an automatic quantization execution module and a runtime dynamic adjustment module. The unified hardware abstraction module generates a standardized hardware feature description file through theoretical modeling and on-chip test correction, supports CPU, GPU and NPU platform adaptation; the model analysis module calculates single-layer sensitivity based on a Hessian matrix, introduces inter-layer error coupling analysis and calculates coupling sensitivity score; the multi-objective Pareto optimization module adopts an NSGA-II algorithm for heuristic pre-pruning and constraint domination, and realizes multi-dimensional Pareto optimal solution of precision, delay, power consumption and memory. The constraint module filters user preference schemes, the automatic execution module outputs a quantization model, and the runtime module dynamically re-optimizes based on real-time feedback. The system solves the problems of non-uniform hardware modeling, no inter-layer cooperation, multi-objective imbalance and no dynamic adaptation in the prior art.