135 results about "Hardware software" patented technology

Systems and methods to leverage and manage data and knowledge in a M2M or Internet of Things (IoT) network are provided. More particularly, a cognitive intelligence platform for an IoT network that provides autonomic decision support system at or near real-time and executes a dynamic runtime is provided. The hardware, software and communication design of the platform replicates the structural and operational model of the human nervous system to achieve cognitive intelligence through adaptation, collaborative learning, knowledge sharing and self-adjustment. Further, in one embodiment, the cognitive intelligence platform has three logical processing layers of increasing complexity, each of which has agents that use statistical and machine learning techniques and algorithms to resolve situational needs and update knowledge. Furthermore, each processing layer of the platform has a basic level of intelligence and additionally the hierarchy of layers aggregates the learning and intelligence at each layer.

Various embodiments of the present invention are directed to a method, in a computer system, for a hardware/software interface system to manipulate a plurality of discrete units of information having properties understandable by said hardware/software interface system (“Items”). The method uses a base schema comprising at least one of an Item as a base Item from which all other Items are derived, and at least one of a property as a base property from which all other properties are derived. Furthermore, an Item may comprise a property for referencing Categories to which the Item is a member. The Item may also comprises a property for a unique identification of that Item in the hardware/software interface system.

A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.

A method for determining wagers by applying a chip denomination representation, having at least one angle associated with at least one color transition, against a working chip template. A related system includes, but is not limited to, circuitry and/or programming for effecting the foregoing-referenced method; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the foregoing-referenced method embodiments depending upon the design choices of the system designer.

A system and method for detecting an intrusion or a bug in a vehicle data transmission system. A hardware-software complex (HSC) is used to find a bug or intrusion device in a vehicle electronic system. The HSC is connected to CAN-buses in the vehicle and also scans radio waves, which can be used to transmit data to a bug. This complex is a self-teaching CAN-system used to monitor and block harmful commands in the vehicle. Each vehicle (of each model, type and settings) has its own reference bus data (parameters), which is used to detect added modules and malicious data sent over the vehicle's CAN bus.

An improved method and apparatus for time stamping events occurring on a large scale distributed network uses a local counter associated with each processor of the distributed network. Each counter resets at the same time globally so that all events are recorded with respect to a particular time. The counter is stopped when a critical event is detected. The events are masked or filtered in an online or offline fashion to eliminate non-critical events from triggering a collection by the system monitor or service/host processor. The masking can be done dynamically through the use of an event history logger. The central system may poll the remote processor periodically to receive the accurate counter value from the local counter and device control register. Remedial action can be taken when conditional probability calculations performed on the historical information indicate that a critical event is about to occur.

IoT embedded systems as well as cloud computing infrastructure may merge processor soft cores with programmable logic (FPGAs) to yield a heterogeneous hardware-software processing ecosystem through which the embedded systems and infrastructure customize and adapt their computational power to the specific application in use. The embedded systems and cloud computing infrastructure with dynamic reconfiguration will bring neuroplasticity to the interconnected space of IoT embedded systems, enabling high-performance, customized, secure-by-design cloud computing services. A cloud server of IaaS is employed to evaluate the performances and efficiencies of embedded systems according to its hardware architectures, so that the computing service allow one reconfigurable system download its hardware architecture file or bitstream into other embedded systems via the cloud server.

A portal is comprised of a plurality of portlets. Each portlet accesses hardware and software to gather data. Each portlet offers information to the portal page. Each portlet's information has a specific content type and markup. A subset of portlets are determined stackable if the subset of portlets have in common one or more of the same hardware, software, content type or markup. Once a subset of portlets is determined stackable, the user's preference for stacking the portlets is obtained by loading a user profile or asking the user. If the subset of portlets are stackable and the user desires the subset of portlets stacked, then the subset of portlets are stacked such that the stack of portlets present a first portlet and a control for selecting a second portlet from within the subset of portlets that is not currently presented.

Systems and methods for securing an embedded system are disclosed. An embedded system comprises a hardware subsystem including physical components of the embedded system, a software subsystem including a software application and a program code, and a programmable logic subsystem programmed to monitor one or more parts of the hardware and software subsystems and interactions thereof to detect tampering of the embedded system. The programmable logic subsystem is capable of being activated by a security function in the software subsystem or by a special hardware component in the hardware subsystem. The activation of the programmable logic subsystem facilitate a coupling of the hardware, software, and the programmable logic subsystems. The program code can be used to dynamically re-program the programmable logic subsystem.

A method of performing encrypted WLAN communication is provided that comprises the steps of performing a connection set-up for the encrypted WLAN communication and performing data frame encapsulation and/or decapsulation during the encrypted WLAN communication. The connection set-up is performed by executing software-implemented instructions, and the data frame encapsulation and/or decapsulation is performed by operating single-purpose hardware. In embodiments, corresponding single-purpose hardware devices, integrated circuit chips, computer program products and computer systems are provided. The embodiments may provide an improved hardware/software architecture for 802.11i security enhancement.

The invention relates to an AADL (architecture analysis and design language) model extension based software system security verification and assessment method, which is provided in order to overcome defect of difficulty in direct processing of system models, high computation cost and high redundancy in computation in existing AADL model based verification and assessment. The method includes: establishing relationship between risk factors and an AADL architecture model to form a mechanism generating model; extracting model elements, generating a time state fault tree, a hardware software impactanalysis tree and a common cause time-dependent analysis tree according to the model elements, and backstepping a risk generation route according to the tree structure from bottom to top; setting physical resource properties and capacity of each physical device; calculating the failure probability of each physical device according to labeled risk factor probability of each physical device; converting an AADL security model into a timed automata; calling a formal verification tool UPPAAL for analysis and verification of the timed automata. The method is applicable to security assessment of software and hardware systems.

The invention discloses a die design-and-produce system, based on KBE and WEB techniques, comprising a program storage digit computer server and a plurality of terminals connected with the server, wherein the server comprises a die design-and-produce knowledge system module, a CAD design module, a die CAE analyzing module, a CAM processing module and a die 3D check module. The invention researches, collects and finishes advanced die design technique, advanced die processing technique, die check technique, and die mould reuse technique, builds a basic frame of the knowledge platform, and processes some experiments on the die knowledge, researches the knowledge obtain, classify and present technique, uses computer program to build a knowledge system project integrated with design, produce, check an reuse, to obtain an cooperated hardware-software platform integrated with knowledge system, design, produce and check.

The invention discloses a method for simplifying a rail transit train operation control system, and belongs to the technical field of rail transit control. The method particularly includes 1), improving a process for designing a universal safety computer platform; 2), simplifying vehicular application or ground application of the rail transit train operation control system. The method has the advantages that the designed universal safety computer platform is implemented on the basis of hardware/software difference design principles and hierarchical diagnosis principles, and functions for simultaneously implementing a plurality of application control logics are supported in the aspect of software on the basis of double-determinacy principles; a plurality of traditional rail transit operation control logic processing functions can be simultaneously supported by a logic processing layer of the universal safety computer platform designed by the process, so that the quantity of equipment of the traditional rail transit train operation control system can be reduced, and the reliability of the operation control system can be improved; the universal safety computer platform designed by the process can be migrated to rail transit train operation control systems with different requirements, so that development and safety assessment workload can be reduced, and the development and safety assessment cost can be lowered.

The invention discloses a method and a system for automatically obtaining the physical positions of display units in a wall splicing system. The method comprises the following steps: for each display unit, generating pictures with unique identification information; displaying the generated pictures by corresponding display units; obtaining a whole image of the wall splicing system; processing the whole image of the wall splicing system, identifying the identification information of the picture displayed by each display unit, and calculating according to the position coordinates of the pictures displayed by the display units in the whole image of the wall splicing system so as to obtain the physical positions of the corresponding display units in the spliced wall. The physical position information of each display unit in the spliced water on the wall splicing system can be obtained, the method is convenient and quick without adding extra hardware software, the allocative efficiency can be improved during initial configuration of the system, and manual configuration of the units one by one is avoided.

A multi-tasking system level Hw/Sw co-verification platform is disclosed. The platform comprises a verification hardware system including a replaceable processor core, a peripheral device required by an OS, a programming logic unit, and a SIP for implementing a complete system, a configurable hardware abstract layer for lowering a coupling with the verification hardware system in a lower level by means of an abstract description of hardware, a configurable device driver for driving hardware of the verification hardware system by means of the configurable hardware abstract layer, an OS for running on the verification hardware system so as to provide an environment and allowing applications to run thereon, and a configurable application for running functions of the verification hardware system.

A system and method for deriving a process-based specification for a system is disclosed. The process-based specification is mathematically inferred from a trace-based specification. The trace-based specification is derived from a non-empty set of traces or natural language scenarios. The process-based specification is mathematically equivalent to the trace-based specification. Code is generated, if applicable, from the process-based specification. A process, or phases of a process, using the features disclosed can be reversed and repeated to allow for an interactive development and modification of legacy systems. The process is applicable to any class of system, including, but not limited to, biological and physical systems, electrical and electro-mechanical systems in addition to software, hardware and hybrid hardware-software systems.

The invention relates to an off-chip Nor Flash bus interface hardware encryption device which comprises an EMI (external memory interface), a data reading decryption passage, a data reading bypass passage, a data writing passage and an AES (advanced encryption standard) encryption engine, wherein the EMI is used for CPU (central processing unit) extensible external memories, the three passages connects the EMI with external Nor Flash memories, the AES encryption engine is connected between a CPU and the data reading decryption passage and used for plaintext data encryption, and the data reading decryption passage comprises an address analyzing unit, an address comparing unit, an indication control unit, a cipher text buffer unit, an AES decryption engine, a plaintext buffer unit and a secret key storage unit. Hardware-software combination is used to provide data encryption for off-chip Nor Flash memories. The device supports a bypass function, data can be written into off-chip Nor Flash memories in plaintext and read in plaintext, so that data storage flexibility is achieved. By the device which is flexible in extensibility, easy to design, high in reliability and safety and the like, Nor Flash bus interface encryption is achieved.

Methods and apparatus are disclosed for virtualizable, forward-compatible hardware-software interfaces. Embodiments may be used in a driver whether it is a physical driver or a virtual driver. Commands are queued from the driver and fetched to the device. An actions table is accessed to determine if drivers are permitted to perform commands. Events are queued for the drivers responsive to commands. If drivers are not permitted to perform a command, device firmware may forward the command to a privileged driver to perform the required command. If a driver is only permitted to perform a command with assistance the command is forwarded for corrections and execution. If a command is to be dropped, a completion event may be queued as if the command had executed. Drivers may have no indication of which actions were taken. The actions table may be changed for hardware/software modifications or dynamically according to configuration changes.

Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, various features and capabilities for debugging programs executed using transactional memory are absent from conventional debuggers. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, there are challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution. For instance, when execution is halted for debugging, a user may request to view a transactional variable or memory location. The transactional variable or memory location may have a pre-transaction value and a tentative value. Allowing a user to only view one of the values reduces the capacity of a user to reason about the behavior of the code.