26 results about "Built-in self-test" patented technology

Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and / or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.

The invention discloses a DFT (Discrete Fourier Transform) architecture planning and automatic generation system based on a graphical interface, which relates to the technical field of integrated circuit computer aided design, and comprises the following steps: providing a graphical editing interface, and forming a DFT architecture schematic diagram by dragging and connecting preset DFT primitives; the DFT primitive library comprises a test access component, a built-in self-test component, a system internal test component, a logic test component, a signal processing component and a clock management component; performing hierarchical analysis and function label identification on the DFT architecture schematic diagram, and generating a structured intermediate representation containing node information, connection information and an entity association index; through graphical dragging, parameterized configuration and automatic script generation, DFT engineers are liberated from tedious manual script writing, the time of DFT architecture design and script generation is shortened from the human day / human week level to the hour level, and the efficiency is obviously improved.

The application relates to a testing device and method for a multi-channel high-speed low-delay interconnection interface of a silicon medium layer. The device comprises a standard testing port for interactive testing instructions, an asynchronous bypass port for directly accessing IO ports of channels of a physical layer of the interconnection interface, a built-in self-test engine for realizing loopback testing and data checking between different layers, a redundant data channel for repairing a damaged data channel, and a delay chain testing circuit for testing functions and linearity of a delay chain. The device is used for embedding and distributing testing and repairing logics in the physical layer and the link layer, realizing internal testing control without an external controller, testing and rapidly screening a sample, and ensuring the performance of the sample.

The present application relates to the technical field of digital chips, and discloses a self-test method, an integrated circuit, a chip, a sensor, and a device. The self-test method of the present application comprises: after a power-on phase and before a startup phase of an integrated circuit, performing a first logic built-in self-test; and before a first operation phase of the integrated circuit, performing a second logic built-in self-test, the first operation phase being after the startup phase. In embodiments of the present application, before each of a startup stage and an operation stage, a corresponding logic built-in self-test is performed, so that it is ensured that a corresponding logic built-in self-test of an automotive grade chip is completed before each stage, thereby improving the operating efficiency of the automotive grade chip, and saving the startup time of the automotive grade chip; additionally, a logic built-in self-test is performed by means of a self-test function inside the automotive grade chip, so that it is unnecessary to change the circuit structure inside the chip or an algorithm, and the costs and the accuracy of the self-test of the automotive grade chip are also considered.

The application discloses an AI accelerator chip PE matrix built-in self-test repair method, and relates to the technical field of AI accelerator chip circuit structure design. The built-in self-test method generates a scan test excitation by using a scan test generator, transmits and outputs a response through a configurable PE operation unit, judges whether the output response is correct or not by using an output response comparator, and judges the row and column addresses of a faulty PE unit by using a fault PE diagnostic device. The built-in self-repair method replaces and repairs the faulty PE unit by using an RPE redundant operation unit, and distributes the corresponding data bus to the RPE redundant operation unit according to the row and column addresses by activating the data bus and the weight data bus distributor. The application realizes the self-test of the PE operation unit and the self-repair of the faulty PE operation unit with a small additional circuit area ratio, thereby improving the yield of the AI accelerator chip and reducing the chip manufacturing cost.

The present application discloses a memory device having a plurality of memory cells, each configured to store data of different values using different resistance states. The memory built-in self-test system may prompt the memory device to perform a memory read operation on memory cells that store data in different resistance states, determine a separation between the different resistance states of at least a subset of the memory cells, and determine a memory read operation based on the separation between the different resistance states of the at least a subset of the memory cells. Detecting that one or more of the memory cells have a degraded tunneling layer in the magnetic tunnel junction. The built-in repair analysis circuit may perform repair of a group of memory cells including at least one of the detected memory cells based on detecting the memory cells having the degraded tunneling layer in the magnetic tunnel junction.

The invention discloses a logic built-in self-test circuit and a related test method thereof.A chip module level circuit comprises an input port and a module register, and the input port is connected with the input end of the module register; the logic built-in self-test circuit comprises a signal blocking circuit which is connected between an input port and the input end of a module register, the signal blocking circuit comprises a selector and a test register, the first input end of the selector is connected with the input port, the second input end of the selector is connected with the output end of the test register, and the first input end of the selector is connected with the input port; the output end of the selector is connected with the input end of the module register; and the controller is connected with the selection end of the selector, is connected with the scanning input end, the scanning enabling end and the clock end of the module register, and is connected with the scanning input end, the scanning enabling end and the clock end of the test register. According to the scheme, the unknown state signal of the input port can be blocked, and the chip module level circuit can be tested.

Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I / O pad, and a first multiplexer. The data register is configured to output a signal. The I / O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I / O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

The application provides a trimming method of eFlash parameters, comprising the following steps: S1: collecting a vector set of initial trimming values, a vector set of high-voltage start-up modes of built-in self-test and a vector set of erase and write operation modes to form a file in HEX format; S2: transmitting a built-in self-test instruction set by using the file in HEX format; S3: starting high-voltage of built-in self-test, and testing analog parameters in a default state by a parameter test module; S4: correcting a trimming value of an SRAM address; S5: starting high-voltage of built-in self-test, and measuring analog parameters corresponding to the SRAM address by the parameter test module; S6: repeating S4-S5 to complete measurement of analog parameters of all SRAM addresses, and if a difference between a measured value and a corresponding trimming value is out of a preset range, the measured value of the address is erased, and the trimming value is written into the address.

The present application relates to the field of integrated circuit technology, in particular to a FPGA logic resource test method and structure based on a new BIST, comprising the following steps: determining the measured module BUT and comparison module BUC of the internal resource of the FPGA to be measured; designing the BIST circuit structure based on the hardware description language, namely: designing the test vector generator TPG, measured module BUT, comparison module BUC and output response analyzer ORA four modules of the BIST circuit based on the hardware description language through the EDA design software of the FPGA; constraining the measured module BUT and comparison module BUC modules, namely: position constraint is conducted on the measured module BUT and comparison module BUC based on the EDA design software of the FPGA; generating and downloading the bit stream file and conducting the real installation board level test verification. The present application is used for solving the problems of low test efficiency, too many test configuration times, complex built-in self-test structure, test sequence generated by TPG not random or random but not covering the full address and weak generalization of the existing FPGA internal resource test.

The invention belongs to the technical field of electronics, and provides a built-in self-test circuit and method for a high-speed interface intellectual property core, and the circuit comprises a pseudo-random binary sequence generator which is used for generating corresponding code pattern data; the serializer is used for converting the code pattern data into serial data; a signal transceiving unit; the deserializer is used for deserializing the serial data to obtain deserialized data and a coding clock signal; the synchronization module is used for performing delay compensation on the deserialized data according to the coding clock signal, and performing time alignment on the data after delay compensation and the pseudo-random binary sequence code pattern data to obtain an aligned data pair; and the comparator is used for carrying out logic judgment on the aligned data pairs and determining whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit is simple in structure, does not additionally occupy salient point resources, and improves the self-test efficiency and accuracy of the high-speed interface IP in the BIST mode.

A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

The invention provides a memory built-in self-test method and device, a test system and electronic equipment. The memory built-in self-test method comprises the following steps: acquiring a test start enable signal based on an I2C communication protocol; generating a plurality of groups of test vectors in response to the test start enable signal; based on a working clock signal of the memory, sequentially writing each group of test vectors into the memory, and reading corresponding output data from the memory; performing consistency comparison on the output data and the expected write-in data to generate memory test information; and outputting the memory test information based on an I2C communication protocol. The method has comprehensive fault detection capability, can realize detection of various types of faults such as fixed faults, partial coupling faults, jump faults, adjacent image sensitive faults and the like, and remarkably improves the fault coverage rate. In addition, the operation process is simple and easy to implement, compatibility is high, work can be carried out without the help of additional testing tools, and the overall testing efficiency is high.

This invention belongs to the field of electronic technology and provides a built-in self-test circuit and method for high-speed interface IP intellectual property cores. The built-in self-test circuit includes: a pseudo-random binary sequence generator for generating corresponding code pattern data; a serializer for converting the code pattern data into serial data; a signal transceiver unit; a deserializer for deserializing the serial data to obtain deserialized data and an encoded clock signal; a synchronization module for performing delay compensation on the deserialized data according to the encoded clock signal and aligning the delay-compensated data with the pseudo-random binary sequence code pattern data to obtain aligned data pairs; and a comparator for performing logical decisions on the aligned data pairs to determine whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit of this invention has a simple structure, does not occupy additional convex resources, and improves the self-test efficiency and accuracy of high-speed interface IP in BIST mode.

The invention discloses a built-in self-test method for detecting and positioning an ILV hard fault in an M3D circuit, which is used for detecting an interlayer interconnection ILV of a monolithic three-dimensional integrated circuit and comprises the following steps of: 1) initializing a test and setting a test mode; 2) applying full '0' excitation, and detecting a fixed fault of the through hole ILV; 3) applying full '1' excitation, and further detecting a fixed fault of the through hole ILV; 4) storing a fixed fault detection result into a scan chain; 5) applying bit-by-bit '1' excitation, detecting a bridging fault of the ILV, and moving a bridging fault detection result into the scanning chain while moving a fixed fault detection result out of the scanning chain; according to the method, special requirements for arrangement of the ILV are avoided, fixed faults and bridging faults in the ILV can be effectively detected and positioned, the time for occupying the ILV in a test mode is short through the time sequence design of parallel detection and shifting operation, and therefore the test efficiency can be improved.

The invention provides a test system capable of modulating attenuation and an operation method thereof. The test system comprises an adjustable and variable attenuation circuit, a control circuit and a device under test (DUT). The tested device is connected to the adjustable attenuation circuit and the control circuit. The tested device comprises a transmitting end and a receiving end. The variable attenuation circuit has a variable impedance. When the device under test executes a built-in self-test (Built-in Self-Test, BIST), the device under test outputs test pattern data (Test Pattern) from a sending end. The device under test generates a determination result based on the test pattern data received from the receiving end. The control circuit receives the judgment result and generates and outputs an attenuation control signal to the adjustable attenuation circuit based on the judgment result. The variable attenuation circuit adjusts the variable impedance based on the attenuation control signal.

A memory device is configured to store data using a write voltage having a voltage level corresponding to a write trim. The memory built-in self-test system may prompt the memory device to perform a memory write operation to store data using a selected write trimmed test value, determine a case where the memory device fails to store data correctly using a write voltage corresponding to the selected write trimmed test value, and determine that the memory device does not use the write voltage corresponding to the selected write trimmed test value. A write trim of the memory device is set based at least in part on a determination that the memory device fails to correctly store the data. The memory built-in self-test system is configured to iteratively select one or more test values for a write trim based on a determination that the memory device fails to correctly store the data.

The invention discloses a TSV rapid test and diagnosis circuit based on BIST, and the circuit comprises a TSV receiving and transmitting array and an interconnection pair bidirectional test circuit which are connected between a core particle of a transmitting end and a core particle of a receiving end, and each TSV of the TSV receiving array is connected with a defect automatic recognition module. The interconnection pair bidirectional test circuit is designed based on a built-in self-test technology, the interconnection pair bidirectional test circuit controls and generates a test vector and a reference vector at a sending end and a receiving end respectively, the test vector is transmitted to the TSV receiving array through the TSV sending array, the TSV receiving array outputs a received response signal and the reference vector to the defect automatic identification module, and the defect automatic identification module is used for identifying the defect. And the defect automatic identification module carries out comparison to obtain TSV interconnection information. The circuit has the advantages of being rapid in design and easy to transplant, the defect positioning speed can be remarkably improved, the built-in self-testing technology is used, the defect type can be automatically recognized, and the circuit does not depend on external testing equipment.

This application relates to the field of digital chip technology, disclosing a self-testing method, integrated circuit, chip, sensor, and device. The self-testing method of this application includes: performing a first logic built-in self-test after the integrated circuit power-on stage and before the startup stage; and performing a second logic built-in self-test before the first operating stage of the integrated circuit, wherein the first operating stage is after the startup stage. This application embodiment includes corresponding logic built-in self-tests before each stage (including the startup stage and the operating stage), ensuring that the automotive-grade chip has completed the corresponding logic built-in self-test before each stage, improving the operating efficiency of the automotive-grade chip and saving its startup time. Simultaneously, by performing logic built-in self-tests through the self-testing function within the automotive-grade chip, there is no need to change the chip's internal circuit structure or algorithm, thus balancing the cost of the automotive-grade chip with the accuracy of the self-test.

The invention relates to a comparator built-in self-test (BIST) circuit. An integrated circuit includes a comparator, a clock generator, and control circuitry. The comparator has a first input, a second input, and an output configured to provide an output clock. The clock generator is configured to generate a differential periodic signal formed by a first periodic signal and a second periodic signal. The clock generator provides the first periodic signal to the first input of the comparator and the second periodic signal to the second input of the comparator, and the clock generator is configured to vary an amplitude of the differential periodic signal based on a control input. The control circuitry is configured to measure hysteresis of the comparator by providing the control input to the clock generator to vary the amplitude of the differential periodic signal in an incremental manner until a predetermined number of state changes of the output clock are detected.

This disclosure provides a built-in self-testing method and device, comprising: obtaining a first initial address of a storage area containing data to be written; masking at least one bit of the first initial address to activate multiple storage areas; writing test data into the corresponding storage area according to a first compressed write address; obtaining a second initial address of a storage area containing data to be read; masking at least one bit of the second initial address to activate multiple storage areas; reading the test data corresponding to the multiple storage areas according to the first compressed read address, and compressing the test data during the reading process; calculating ideal read data based on the test data and a preset compression rule; comparing the read data from the memory with the ideal read data to obtain a test result. This setup improves testing efficiency.

The high-precision ADC provided by this invention has a built-in self-test circuit for its static characteristics, comprising: in the sample-and-hold phase, sampling the input external common-mode signal Vcm to obtain a sampled common-mode signal; in the first quantization phase, sampling and amplifying the sampled common-mode signal based on the positive input signal Vip, and reducing the output impedance to obtain a first amplified common-mode signal; in the second quantization phase, sampling and amplifying the sampled common-mode signal based on the negative input signal Vin, and reducing the output impedance to obtain a second amplified common-mode signal; wherein the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are averaged to obtain a high-precision test signal. In this invention, the sampling common-mode signal is quantized based on a pair of differential signals, and the results of the two quantizations are summed, thus eliminating sampling thermal noise.

The present application relates to field programmable gate array system technical field, disclose a kind of field programmable gate array system testing device and method, testing device includes built-in self-test state machine and multiple built-in self-test circuits, built-in self-test circuit is configured on corresponding function module;Built-in self-test state machine is used to receive bit stream data;Built-in self-test state machine is also used to determine first test route based on bit stream data, for controlling built-in self-test circuit generates test excitation signal;Built-in self-test state machine is also used to control built-in self-test circuit and corresponding test excitation signal is sent to the function module to be measured;Built-in self-test state machine is also used to receive at least one test result output by the function module to be measured, for determining whether corresponding function module to be measured is normal based on test result.The present application can only be tested to the function module required by the specific application needed to be completed by field programmable gate array system, to reduce test time.

The application discloses a kind of embedded Flash memory self-test system and method based on MBIST and LBIST, it is related to integrated circuit test technical field, for solving the technical problem that existing external automatic test equipment tests Flash memory, leading to test difficult to cover chip internal complex connection path, and cannot carry out integrity verification in real time;The embedded Flash memory self-test system based on MBIST and LBIST of the application, including embedded Flash memory module, memory built-in self-test module, logic built-in self-test module and control and state register module;Memory built-in self-test module is used to execute Flash memory test and report error;Logic built-in self-test module is used to test logic circuit;Control and state register module is used to control the test trigger of memory built-in self-test and logic built-in self-test to Flash memory.

The invention provides a three-dimensional stacked chip and a redundancy repair method, a three-dimensional stacked memory comprises a logic control chip and a plurality of memory chips, and the logic control chip comprises a built-in redundancy analysis module and a plurality of built-in self-test modules; the built-in self-test module is configured to perform parallel test on all memory chips and send first fault information corresponding to a first memory chip obtained by test to the built-in redundancy analysis module; the built-in redundancy analysis module is configured to generate a corresponding first redundancy repair strategy based on the received first fault information; and the built-in self-test module and the built-in redundancy analysis module are further configured to perform serial test on other memory chips with faults in sequence and generate corresponding repair strategies. According to the scheme of the invention, the repair process of parallel test-repair-serial test and repair is designed, the hardware area overhead can be greatly saved, and the wafer stacking yield of the storage unit fault is effectively improved.

The application relates to a built-in self-test method, architecture and system of an in-memory computing macro unit, comprising the following steps: performing a first test mode: inserting a computing activation vector and a computing enabling instruction in an MBIST test algorithm to perform a computing test after a read operation to detect coupling faults between a storage array and bit multiplication logic; and judging whether storage read results and computing results are correct, if yes, entering a second test mode or judging that self-test is correct and detection is completed, otherwise diagnosing a fault position based on a detection result. The test method provided by the application inserts a computing enabling instruction and a computing activation vector in a traditional MBIST algorithm, verifies an additional multiply-accumulate computing operation after a read operation, and can further effectively detect data coupling between a storage unit and a computing unit under the premise of covering traditional storage fault types, so that the fault coverage is improved.