75 results about "Built-in self-test" patented technology

The invention relates to a built-in self-test circuit and a memory. The built-in self-test circuit comprises a storage array, a command / address generation module, a processing module and a repair module. After entering the self-test mode, the command / address generation module generates and sends an internal test command and an internal test address according to a preset test mode. The processing module writes preset data into a storage unit corresponding to the internal test address in the storage array according to the internal test command and a preset test mode, and reads storage data from the storage unit corresponding to the internal test address in the storage array; and generating and outputting a fault mark according to a comparison result of the storage data read each time and the corresponding written preset data. And the repairing module latches the internal test address corresponding to the currently read storage data as an error address according to the fault mark, and repairs the storage unit corresponding to the error address after the self-test mode exits. According to the invention, internal automatic detection and automatic repair can be realized.

The invention discloses a built-in self-test repairing method for a PE matrix of an AI accelerator chip, and relates to the technical field of circuit structure design of the AI accelerator chip. According to the built-in self-test method, a scan test generator is adopted to generate scan test excitation, an output response is transmitted through a configurable PE operation unit, an output response comparator is adopted to judge whether the output response is correct or not, and a fault PE diagnostor is adopted to judge a row and column address where a fault PE unit is located; according to the built-in self-repairing method, an RPE redundant operation unit is used for replacing and repairing a fault PE unit, and a corresponding data bus is distributed to the RPE redundant operation unit through an activation data bus and a weight data bus distributor according to row and column addresses. According to the invention, the self-test of the PE arithmetic unit and the self-repair of the failed PE arithmetic unit are realized with a relatively small extra circuit area proportion, so that the yield of the AI accelerator chip is improved, and the manufacturing cost of the chip is reduced.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention discloses a self-detection circuit and a storage device, the storage device comprises a storage circuit, a control circuit and a self-detection circuit, the self-detection circuit is coupled between the control circuit and the storage circuit, and the self-detection circuit comprises a built-in self-test module and a built-in self-test interface; wherein the built-in self-test module is connected to the control circuit through a built-in self-test interface and a first customized bus, and the built-in self-test module is configured to receive a test instruction from the control circuit through the first customized bus and the built-in self-test interface, and execute a self-test operation based on the test instruction to detect a damaged storage unit in the storage circuit, and corresponding dead pixel information is generated and stored in the storage circuit. Through the above mode, the self-detection circuit provided by the invention can perform dead pixel automatic test on the damaged storage unit in the storage circuit, reduces external operation, can obtain dead pixel information in the storage circuit in real time, and is high in automation degree, generalization degree and parallelization degree.

The invention discloses a memory repairing method and device, an access method and device, electronic equipment and a medium. The memory comprises a plurality of object storage units, the plurality of object storage units are arranged into a plurality of cache lines, the plurality of cache lines are divided into a plurality of paths, the cache lines with the same index in the plurality of paths are taken as a group, and the repairing method comprises the following steps: carrying out built-in self-testing on the plurality of object storage units; in response to the fact that the built-in self-test detects dead pixels in the multiple object storage units, address information of the dead pixels is determined, and the address information comprises group information (index) indicating a group where the dead pixels are located and path information (way) of a path where the dead pixels are located; and performing first repair on the defective pixel based on the group information and the path information. According to the method, under the condition that hardware resources are not increased, repairing of the memory dead pixels is achieved in a finer-grained mode, and the repairing capacity is improved. And moreover, the implementation mode is simple, and the index of the storage unit in the memory cannot be greatly impacted.

The invention provides a built-in self-test circuit, a built-in self-test method and a memory. The method comprises the following steps: generating initial test data through a data module; receiving a flipping signal through a flipping module, if the flipping signal is in a first state, performing negation processing on the initial test data, and generating and outputting target test data; and if the flip signal is in the second state, directly outputting the initial test data as target test data.

The invention belongs to the technical field of testability design of integrated circuits, and discloses a 3D IC MBIST test method based on an intelligent algorithm, and the method comprises the steps: carrying out the isomorphic grouping through analyzing the space coordinates, hierarchical affiliation and multi-dimensional attributes of a memory; establishing a three-dimensional layout relationship based on the improved interlayer distance model; the hierarchical clustering algorithm is adopted to merge memory clusters according to spatial proximity, and a grouping architecture with the minimum controller number is constructed; a dynamic test scheduling model is established in combination with a multi-target simulated annealing algorithm, and test time is optimized under power consumption constraint through a temperature attenuation mechanism. According to the method, three-dimensional collaborative optimization is carried out on spatial layout, time sequence constraint and power consumption budget, the contradiction between area overhead and test efficiency of a traditional memory built-in self-test scheme in a 3D IC is solved, and lamination test challenges under the condition that the test temperature is limited are effectively handled; and the test economy and reliability of the heterogeneous integrated chip are obviously improved.

The invention provides a test method for a BIST system of a memory, and belongs to the field of integrated circuits. The test method comprises the following steps: a page buffer test step: a test machine sends a page buffer test command to a controller through a bus, and the controller controls a BIST circuit to test a page buffer and confirms whether the page buffer is damaged; a storage array test step: the test machine sends a storage array test command to the controller through the bus, and the controller controls the BIST circuit to test the storage array; a judgment step: judging whether the storage array is repairable or not by the BIST circuit; a temporary storage step: after the test is completed, the BIST circuit temporarily stores a test result in the page buffer; and a writing step: the controller sends the test result temporarily stored in the page buffer to a test machine through the bus, the test machine sends the test result to the controller through the bus, and the controller writes the test result into the one-time programmable memory. According to the test method, the occupied area of the chip can be reduced, and power consumption is reduced.

The invention relates to the field of integrated circuit testing, provides an SRAM (Static Random Access Memory) fault testing structure, and particularly relates to an IEEE (Institute of Electrical and Electronic Engineers) 1687 standard and an SRAM self- According to the method, a common fault model of an SRAM (Static Random Access Memory) is analyzed, improvement is performed on the basis of a March C-algorithm, and a March C-pro algorithm capable of covering most common faults of the SRAM is derived; a modularized SRAM self-test structure is designed based on a March C-pro algorithm, so that the design cost caused by built-in self-test of a memory and possible additional interface requirements are avoided; a multi-layer network structure based on the IEEE 1687 standard is designed, access to an embedded instrument is achieved, an SRAM self-test module is connected, and an SRAM test in the SOC is achieved.

The invention relates to the technical field of field-programmable gate array systems, and discloses a test device and method for a field-programmable gate array system, the test device comprises a built-in self-test state machine and a plurality of built-in self-test circuits, and the built-in self-test circuits are configured on corresponding function modules; the built-in self-test state machine is used for receiving bit stream data; the built-in self-test state machine is also used for determining a first test route based on the bit stream data, and is used for controlling the built-in self-test circuit to generate a test excitation signal; the built-in self-test state machine is also used for controlling the built-in self-test circuit to send a test excitation signal to the corresponding function module to be tested; the built-in self-test state machine is further used for receiving the test result output by the at least one to-be-tested function module and determining whether the corresponding to-be-tested function module is normal or not based on the test result. According to the invention, only the function module required by the specific application which needs to be completed by the field programmable gate array system can be tested, so that the test time is reduced.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

The invention provides a memory built-in self-test method, a controller and a circuit, and relates to the technical field of memory testing, and the test method comprises the following steps: S1, starting to write 0 in an ascending order from the lowest address; s2, reading 0 for the lowest address, and then writing 1 and reading 1 in an ascending order; s3, reading 1 for the lowest address, and then writing 0 and reading 0 in an ascending order; s4, reading 0 for the lowest address, and then writing 1 in an ascending order; s5, reading 1 for the highest address, and then writing 0 and reading 0 in a descending order; s6, reading 0 for the lowest address, and then writing 0 in an ascending order; s7, reading 0 for the highest address, and then writing 1 and reading 1 in a descending order; and S8, reading 1 from the lowest address in an ascending order. The invention also provides a memory built-in self-test controller and a memory built-in self-test circuit. Based on the newly proposed March-E algorithm, the test speed and the fault coverage rate can be improved and the power consumption can be reduced with relatively low area overhead.

Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and / or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.

The invention discloses a method for designing a high-yield magnetic random access memory system under an irradiation condition, and the method comprises the steps: carrying out the detection and repair of soft and hard errors based on a 2T-2M self-reference structure in combination with an error detection and correction circuit based on a Hamming code and a built-in self-test-self-repair system, inhibiting the generation of the soft and hard errors in an irradiation environment, and improving the reliability of the system. And the yield of the memory is effectively improved. The built-in self-test-self-repair system comprises a built-in self-test circuit with a fault diagnosis function and a built-in redundancy self-repair circuit, and a sequential logic unit in the system calls a sequential logic standard unit library designed by adopting a dual-modular redundancy anti-radiation reinforcement method.

The invention provides a built-in self-test system of a memory, and belongs to the field of integrated circuits. The memory of the present invention comprises: a memory array including a plurality of memory cells for storing data; the controller is electrically connected with the storage array through the multiplexer and is electrically connected with the test machine table through a bus; the built-in self-test system comprises a built-in self-test circuit which is electrically connected with the controller and is electrically connected with the storage array through the multiplexer, and the built-in self-test circuit is used for testing the storage array; the page buffer is electrically connected with the controller and the built-in self-test circuit, and is used for caching the written data when the data is written into the storage array and temporarily storing a test result when the BIST is carried out on the storage array; and the one-time programmable memory is electrically connected with the controller and is used for finally storing the test result. According to the BIST system of the memory, the occupied area of a chip can be reduced, and the power consumption is reduced.

Techniques for secure built in self test are described. Some examples include a secure test pattern generator to generate a secure test pattern using a pseudo-random function (PRF) circuitry; a scan out hash engine to hash a scan out of a circuit to be tested; and a comparison circuit to compare the hashed scan out to a known value to verify the hash.

The invention belongs to the technical field of integrated circuit design and test, and discloses a built-in self-test circuit and method for ILV fault positioning optimization in a 3D IC, and the circuit comprises a BIST mode generation module, a signal transmission module, a fault capturing module, and a fault positioning module. The ILV fault can be efficiently detected and positioned by generating test modes for different fault types, controlling one-way propagation of signals and scanning and capturing fault signals. The method is suitable for high-density irregular ILV layout, extra test ports are not needed, compared with a traditional test method, the method is short in test time and high in fault positioning precision, meanwhile, consumption of hardware resources is reduced, and the reliability and production efficiency of a 3D integrated circuit are further improved.

The embodiment of the invention provides a detection method and device for a storage unit of a chip, and the method comprises the steps: generating a scanning mode entering instruction, and calling a joint test behavior organization interface to control the chip to enter a scanning mode based on the scanning mode entering instruction; in a scan mode, generating a scan chain for the storage unit through the register; the scan chain comprises a first storage built-in self-test scan chain which is generated for the register and aims at the native storage unit, and a second storage built-in self-test scan chain which aims at the customized storage unit; when it is judged that the storage unit has a fault, scanning data aiming at the storage unit is obtained through the first storage built-in self-test scanning chain and the second storage built-in self-test scanning chain, and a first count value is obtained by resetting a counter; the storage unit is detected based on the scanning data and the first count value, multiple diagnosis modes can be provided for detecting the storage unit, and therefore the detection efficiency of the on-chip storage unit is improved.

The invention relates to the technical field of circuits, in particular to a memory built-in self-test circuit generation method and device and electronic equipment. The method comprises the following steps: acquiring a parameter configuration file of which the text format is Excel; wherein the parameter configuration file comprises first configuration information of the static random access memory, second configuration information of the joint test behavior organization and an algorithm for detecting a fault in the memory; calculating the matching degree between parameters in each cell in the parameter configuration file and each pre-configured theoretical algorithm; determining a target algorithm based on the matching degree; wherein the target algorithm comprises any one of theoretical algorithms; and inputting the algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written by adopting a SpinalHDL programming language, and generating a memory built-in self-test circuit corresponding to the target algorithm.

The present invention belongs to the technical field of integrated circuit testability design, and discloses a 3D IC MBIST test method based on an intelligent algorithm. It performs isomorphic grouping by parsing the spatial coordinates, hierarchical attribution, and multi-dimensional attributes of memories; establishes a three-dimensional layout relationship based on an improved interlayer distance model; uses a hierarchical clustering algorithm to merge memory clusters according to spatial proximity, and constructs a grouping architecture with a minimized number of controllers; combines a multi-objective simulated annealing algorithm to establish a dynamic test scheduling model, and optimizes the test time under power consumption constraints through a temperature attenuation mechanism. The method of the present invention performs three-dimensional collaborative optimization of spatial layout, timing constraints, and power consumption budget, solves the contradiction between area overhead and test efficiency faced by traditional memory built-in self-test schemes in 3D ICs, effectively copes with the stacked layer test challenges under limited test temperature conditions, and significantly improves the test economy and reliability of heterogeneous integrated chips.

The present invention relates to a programmable memory built-in self-test method based on a finite state machine, and the method is implemented by a programmable Mbist control module driven by three counters, an algorithm module, a comparison and analysis module, and a BRAM to be tested. In the present invention, the algorithm module integrates 8 test algorithms and generates characteristic signals according to the characteristics of each test algorithm, thereby improving the coverage of faults. Secondly, the programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters, thereby improving the flexibility of the test. The present invention provides a new programmable memory built-in self-test method based on a finite state machine, which replaces the conventional test method. When the test algorithm needs to be replaced, the proposed test method does not need to reset the Mbist circuit, effectively reducing manpower and configuration time, thereby reducing the test cost.

The invention discloses a DFT (Discrete Fourier Transform) architecture planning and automatic generation system based on a graphical interface, which relates to the technical field of integrated circuit computer aided design, and comprises the following steps: providing a graphical editing interface, and forming a DFT architecture schematic diagram by dragging and connecting preset DFT primitives; the DFT primitive library comprises a test access component, a built-in self-test component, a system internal test component, a logic test component, a signal processing component and a clock management component; performing hierarchical analysis and function label identification on the DFT architecture schematic diagram, and generating a structured intermediate representation containing node information, connection information and an entity association index; through graphical dragging, parameterized configuration and automatic script generation, DFT engineers are liberated from tedious manual script writing, the time of DFT architecture design and script generation is shortened from the human day / human week level to the hour level, and the efficiency is obviously improved.

The present invention relates to the field of chip technology, and specifically discloses a chip curing method, device, equipment and storage medium for improving the utilization rate of wafers. Among them, the method includes the following steps: equally dividing the die after redundant replacement into multiple storage areas; performing built-in self-test on the die to obtain the result information of each storage area, and the result information is used to mark whether the corresponding storage area is available; curing the available storage areas in the die according to the result information. This method divides the die into multiple storage areas, obtains the result information of all storage areas, and then cures the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding cured storage areas, so that even if there are a certain number of unavailable storage areas in the die, the capacity specification can still be adjusted downward for use, so as to improve the utilization rate of wafers.

Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.

The application relates to a testing device and method for a multi-channel high-speed low-delay interconnection interface of a silicon medium layer. The device comprises a standard testing port for interactive testing instructions, an asynchronous bypass port for directly accessing IO ports of channels of a physical layer of the interconnection interface, a built-in self-test engine for realizing loopback testing and data checking between different layers, a redundant data channel for repairing a damaged data channel, and a delay chain testing circuit for testing functions and linearity of a delay chain. The device is used for embedding and distributing testing and repairing logics in the physical layer and the link layer, realizing internal testing control without an external controller, testing and rapidly screening a sample, and ensuring the performance of the sample.

The application discloses a memory test method and a test system. The memory test method is used for controlling the test state and test flow of each to-be-tested memory through at least two layers of loop control and read-write sequence operation. The at least two layers of loop control include: algorithm loop, each algorithm loop controls the execution of all algorithm steps of one to-be-tested memory, and the test flow of the corresponding to-be-tested memory is ended after the execution of all algorithm steps; address loop, the test address is traversed in the execution process of each algorithm step, each traversed address is executed the read-write sequence operation, and the address loop is ended after the traversal of the test address is completed. The application realizes algorithm atomization, so that the MBIST memory built-in self-test architecture can realize a more flexible test process.

The present application relates to the technical field of digital chips, and discloses a self-test method, an integrated circuit, a chip, a sensor, and a device. The self-test method of the present application comprises: after a power-on phase and before a startup phase of an integrated circuit, performing a first logic built-in self-test; and before a first operation phase of the integrated circuit, performing a second logic built-in self-test, the first operation phase being after the startup phase. In embodiments of the present application, before each of a startup stage and an operation stage, a corresponding logic built-in self-test is performed, so that it is ensured that a corresponding logic built-in self-test of an automotive grade chip is completed before each stage, thereby improving the operating efficiency of the automotive grade chip, and saving the startup time of the automotive grade chip; additionally, a logic built-in self-test is performed by means of a self-test function inside the automotive grade chip, so that it is unnecessary to change the circuit structure inside the chip or an algorithm, and the costs and the accuracy of the self-test of the automotive grade chip are also considered.

The invention provides a method for performing a self-test on a memory. The method may include determining an operation mode of a memory built-in self-test (MBIST) unit based on a state of the memory; in response to the operation mode being a start mode, configuring the MBIST unit to execute a first type of memory self-test; and in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically execute a second type of memory self-test.

The invention provides a semiconductor memory which comprises a built-in self-test module, an internal control module and an address repair module, the built-in self-test module is used for receiving a mode register write instruction sent by an external control module and generating a parallel test instruction according to the mode register write instruction, and the internal control module is used for receiving the parallel test instruction and repairing the parallel test instruction according to the parallel test instruction. And simultaneously testing the plurality of storage libraries according to the parallel test instruction to obtain a fault address. The repair address module is used for decoding the fault address to determine the address of the fault storage area, sending the address of the fault storage area to the internal control module, receiving repair resource information sent by the internal control module, generating a repair identifier according to the repair resource information, and sending the repair identifier to the internal control module; the repair resource information is determined by the internal control module according to the address of the fault storage area, so that the fault storage area can be replaced based on the repair identifier, and the yield of the semiconductor memory is improved.

The present disclosure provides a memory, a built-in self-test method and a test system. The memory includes a counter for counting erroneous data bits obtained by data verification. During the built-in self-test process of the memory, a flag pulse signal is generated each time a data error is detected, and the flag pulse signal is counted using the counter.