42 results about "Built-in self-test" patented technology

The invention relates to the field of integrated circuit testing, provides an SRAM (Static Random Access Memory) fault testing structure, and particularly relates to an IEEE (Institute of Electrical and Electronic Engineers) 1687 standard and an SRAM self- According to the method, a common fault model of an SRAM (Static Random Access Memory) is analyzed, improvement is performed on the basis of a March C-algorithm, and a March C-pro algorithm capable of covering most common faults of the SRAM is derived; a modularized SRAM self-test structure is designed based on a March C-pro algorithm, so that the design cost caused by built-in self-test of a memory and possible additional interface requirements are avoided; a multi-layer network structure based on the IEEE 1687 standard is designed, access to an embedded instrument is achieved, an SRAM self-test module is connected, and an SRAM test in the SOC is achieved.

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

Temperature-aware built-in self-test (BIST) control system for selectively controlling activation of BIST circuits in a processor-based system to maintain temperature limit and related methods. The temperature-aware BIST control system is configured to selectively control the number of BIST circuits in the processor-based system activated during the same time based on a temperature limit indicator related to a sensed temperature(s) in the processor-based system and whether such is within a defined temperature threshold(s) and / or temperature change rate threshold(s), which may be programmable. In this manner, the safety manager circuit can dynamically and selectively control the number of BIST circuits activated based on temperature according to the BIST control policy(ies) to reduce or avoid circuit failures due to excess temperature, while at the same time maximizing the staggering (i.e., overlapping) of BIST circuit activations to maximize testing speed.

Techniques for secure built in self test are described. Some examples include a secure test pattern generator to generate a secure test pattern using a pseudo-random function (PRF) circuitry; a scan out hash engine to hash a scan out of a circuit to be tested; and a comparison circuit to compare the hashed scan out to a known value to verify the hash.

The invention discloses a DFT (Discrete Fourier Transform) architecture planning and automatic generation system based on a graphical interface, which relates to the technical field of integrated circuit computer aided design, and comprises the following steps: providing a graphical editing interface, and forming a DFT architecture schematic diagram by dragging and connecting preset DFT primitives; the DFT primitive library comprises a test access component, a built-in self-test component, a system internal test component, a logic test component, a signal processing component and a clock management component; performing hierarchical analysis and function label identification on the DFT architecture schematic diagram, and generating a structured intermediate representation containing node information, connection information and an entity association index; through graphical dragging, parameterized configuration and automatic script generation, DFT engineers are liberated from tedious manual script writing, the time of DFT architecture design and script generation is shortened from the human day / human week level to the hour level, and the efficiency is obviously improved.

Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.

The application relates to a testing device and method for a multi-channel high-speed low-delay interconnection interface of a silicon medium layer. The device comprises a standard testing port for interactive testing instructions, an asynchronous bypass port for directly accessing IO ports of channels of a physical layer of the interconnection interface, a built-in self-test engine for realizing loopback testing and data checking between different layers, a redundant data channel for repairing a damaged data channel, and a delay chain testing circuit for testing functions and linearity of a delay chain. The device is used for embedding and distributing testing and repairing logics in the physical layer and the link layer, realizing internal testing control without an external controller, testing and rapidly screening a sample, and ensuring the performance of the sample.

The application discloses a memory test method and a test system. The memory test method is used for controlling the test state and test flow of each to-be-tested memory through at least two layers of loop control and read-write sequence operation. The at least two layers of loop control include: algorithm loop, each algorithm loop controls the execution of all algorithm steps of one to-be-tested memory, and the test flow of the corresponding to-be-tested memory is ended after the execution of all algorithm steps; address loop, the test address is traversed in the execution process of each algorithm step, each traversed address is executed the read-write sequence operation, and the address loop is ended after the traversal of the test address is completed. The application realizes algorithm atomization, so that the MBIST memory built-in self-test architecture can realize a more flexible test process.

The present application relates to the technical field of digital chips, and discloses a self-test method, an integrated circuit, a chip, a sensor, and a device. The self-test method of the present application comprises: after a power-on phase and before a startup phase of an integrated circuit, performing a first logic built-in self-test; and before a first operation phase of the integrated circuit, performing a second logic built-in self-test, the first operation phase being after the startup phase. In embodiments of the present application, before each of a startup stage and an operation stage, a corresponding logic built-in self-test is performed, so that it is ensured that a corresponding logic built-in self-test of an automotive grade chip is completed before each stage, thereby improving the operating efficiency of the automotive grade chip, and saving the startup time of the automotive grade chip; additionally, a logic built-in self-test is performed by means of a self-test function inside the automotive grade chip, so that it is unnecessary to change the circuit structure inside the chip or an algorithm, and the costs and the accuracy of the self-test of the automotive grade chip are also considered.

The invention provides a method for performing a self-test on a memory. The method may include determining an operation mode of a memory built-in self-test (MBIST) unit based on a state of the memory; in response to the operation mode being a start mode, configuring the MBIST unit to execute a first type of memory self-test; and in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically execute a second type of memory self-test.

The present disclosure provides a memory, a built-in self-test method and a test system. The memory includes a counter for counting erroneous data bits obtained by data verification. During the built-in self-test process of the memory, a flag pulse signal is generated each time a data error is detected, and the flag pulse signal is counted using the counter.

The application discloses an AI accelerator chip PE matrix built-in self-test repair method, and relates to the technical field of AI accelerator chip circuit structure design. The built-in self-test method generates a scan test excitation by using a scan test generator, transmits and outputs a response through a configurable PE operation unit, judges whether the output response is correct or not by using an output response comparator, and judges the row and column addresses of a faulty PE unit by using a fault PE diagnostic device. The built-in self-repair method replaces and repairs the faulty PE unit by using an RPE redundant operation unit, and distributes the corresponding data bus to the RPE redundant operation unit according to the row and column addresses by activating the data bus and the weight data bus distributor. The application realizes the self-test of the PE operation unit and the self-repair of the faulty PE operation unit with a small additional circuit area ratio, thereby improving the yield of the AI accelerator chip and reducing the chip manufacturing cost.

The present application discloses a memory device having a plurality of memory cells, each configured to store data of different values using different resistance states. The memory built-in self-test system may prompt the memory device to perform a memory read operation on memory cells that store data in different resistance states, determine a separation between the different resistance states of at least a subset of the memory cells, and determine a memory read operation based on the separation between the different resistance states of the at least a subset of the memory cells. Detecting that one or more of the memory cells have a degraded tunneling layer in the magnetic tunnel junction. The built-in repair analysis circuit may perform repair of a group of memory cells including at least one of the detected memory cells based on detecting the memory cells having the degraded tunneling layer in the magnetic tunnel junction.

The invention relates to a built-in self-test system and method for an MTP memory, belongs to the technical field of chip testing, and solves the problems that the existing built-in self-test function is single and cannot be applied to different memory areas at the same time. The address generator is used for generating an address signal; the mode generator is used for obtaining a test operation signal according to the area selection signal, the mode selection signal and the test sequence selection signal, starting the mode state machine and entering a corresponding test state; the signal generator is used for starting the signal state machine and entering a corresponding signal state according to the test state signal and the preset time of the time sequence counter; the MTP memory is used for starting testing according to the address signals, the test operation signal and the signal state, acquiring test data of each address signal and returning the test data to the comparator; and the comparator is used for comparing the test data of each address signal with the received address signal and the test operation signal, and feeding back a comparison result to the mode generator. And various and flexible built-in self-testing is realized.

The invention discloses a logic built-in self-test circuit and a related test method thereof.A chip module level circuit comprises an input port and a module register, and the input port is connected with the input end of the module register; the logic built-in self-test circuit comprises a signal blocking circuit which is connected between an input port and the input end of a module register, the signal blocking circuit comprises a selector and a test register, the first input end of the selector is connected with the input port, the second input end of the selector is connected with the output end of the test register, and the first input end of the selector is connected with the input port; the output end of the selector is connected with the input end of the module register; and the controller is connected with the selection end of the selector, is connected with the scanning input end, the scanning enabling end and the clock end of the module register, and is connected with the scanning input end, the scanning enabling end and the clock end of the test register. According to the scheme, the unknown state signal of the input port can be blocked, and the chip module level circuit can be tested.

Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I / O pad, and a first multiplexer. The data register is configured to output a signal. The I / O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I / O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

The application relates to a built-in self-test circuit and a memory. The built-in self-test circuit comprises a storage array, a command / address generation module, a processing module and a repair module. After entering a self-test mode, the command / address generation module generates and sends internal test commands and internal test addresses according to a preset test mode. According to the internal test commands, the processing module writes preset data into the storage units corresponding to the internal test addresses in the storage array according to the preset test mode, and reads storage data from the storage units corresponding to the internal test addresses in the storage array; according to the comparison result of the storage data read each time and the preset data corresponding to the writing, a fault flag is generated and output. According to the fault flag, the repair module latches the internal test address corresponding to the current read storage data as an error address, and repairs the storage units corresponding to the error address after the self-test mode is exited. The application can realize internal automatic detection and automatic repair.

The invention relates to a built-in self-test method, architecture and system oriented to an in-memory computing macro-cell, and the method comprises the steps: executing a first test mode: inserting a computing activation vector and a computing enabling instruction in an MBIST test algorithm, and carrying out a computing test after a read operation to detect a coupling fault between a storage array and bit multiplication logic; and judging whether the storage reading result and the calculation result are correct or not, if so, entering a second test mode or judging that the self-test is correct and completing the detection, and otherwise, diagnosing the fault position based on the detection result. According to the test method provided by the invention, the calculation enabling and the calculation activation vector are inserted in the traditional MBIST algorithm, and the additionally executed multiply-accumulate calculation operation is verified after the read operation, so that the test efficiency is greatly improved on the premise of covering the fault type of the traditional memory. The specific fault of data coupling between the storage unit and the calculation unit can be further effectively detected, and the fault coverage rate is increased.

The application provides a trimming method of eFlash parameters, comprising the following steps: S1: collecting a vector set of initial trimming values, a vector set of high-voltage start-up modes of built-in self-test and a vector set of erase and write operation modes to form a file in HEX format; S2: transmitting a built-in self-test instruction set by using the file in HEX format; S3: starting high-voltage of built-in self-test, and testing analog parameters in a default state by a parameter test module; S4: correcting a trimming value of an SRAM address; S5: starting high-voltage of built-in self-test, and measuring analog parameters corresponding to the SRAM address by the parameter test module; S6: repeating S4-S5 to complete measurement of analog parameters of all SRAM addresses, and if a difference between a measured value and a corresponding trimming value is out of a preset range, the measured value of the address is erased, and the trimming value is written into the address.

The present application relates to the field of integrated circuit technology, in particular to a FPGA logic resource test method and structure based on a new BIST, comprising the following steps: determining the measured module BUT and comparison module BUC of the internal resource of the FPGA to be measured; designing the BIST circuit structure based on the hardware description language, namely: designing the test vector generator TPG, measured module BUT, comparison module BUC and output response analyzer ORA four modules of the BIST circuit based on the hardware description language through the EDA design software of the FPGA; constraining the measured module BUT and comparison module BUC modules, namely: position constraint is conducted on the measured module BUT and comparison module BUC based on the EDA design software of the FPGA; generating and downloading the bit stream file and conducting the real installation board level test verification. The present application is used for solving the problems of low test efficiency, too many test configuration times, complex built-in self-test structure, test sequence generated by TPG not random or random but not covering the full address and weak generalization of the existing FPGA internal resource test.

The invention belongs to the technical field of electronics, and provides a built-in self-test circuit and method for a high-speed interface intellectual property core, and the circuit comprises a pseudo-random binary sequence generator which is used for generating corresponding code pattern data; the serializer is used for converting the code pattern data into serial data; a signal transceiving unit; the deserializer is used for deserializing the serial data to obtain deserialized data and a coding clock signal; the synchronization module is used for performing delay compensation on the deserialized data according to the coding clock signal, and performing time alignment on the data after delay compensation and the pseudo-random binary sequence code pattern data to obtain an aligned data pair; and the comparator is used for carrying out logic judgment on the aligned data pairs and determining whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit is simple in structure, does not additionally occupy salient point resources, and improves the self-test efficiency and accuracy of the high-speed interface IP in the BIST mode.

A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

The present application discloses a self-test circuit and a storage device, wherein the storage device includes a storage circuit, a control circuit, and a self-test circuit, wherein the self-test circuit is coupled between the control circuit and the storage circuit, and the self-test circuit includes a built-in self-test module and a built-in self-test interface; wherein the built-in self-test module is connected to the control circuit via the built-in self-test interface and a first custom bus, and the built-in self-test module is configured to receive a test instruction from the control circuit via the first custom bus and the built-in self-test interface, perform a self-test operation based on the test instruction to detect damaged storage cells in the storage circuit, generate corresponding bad pixel information, and store it in the storage circuit. In this way, the self-test circuit of the present application can automatically test the damaged storage cells in the storage circuit for bad pixels, reduce external operations, and obtain bad pixel information in the storage circuit in real time, and has a high degree of automation, generalization, and parallelization.

The present invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method, and a testing system. A built-in self-test (BIST) test process and first to third configuration registers are embedded in the memory testing device. Therefore, only a prescribed test stimulus needs to be applied on a test host to automatically implement testing of corresponding functional parameters of the three-dimensional stacked memory chip. During testing, switching of functional parameters, test directions, and test modes only needs to be implemented by adjusting configuration values in the first to third configuration registers. Thus, the test process of the functional parameters of the memory is optimized, greatly saving test time and test costs.

The invention provides a memory built-in self-test method and device, a test system and electronic equipment. The memory built-in self-test method comprises the following steps: acquiring a test start enable signal based on an I2C communication protocol; generating a plurality of groups of test vectors in response to the test start enable signal; based on a working clock signal of the memory, sequentially writing each group of test vectors into the memory, and reading corresponding output data from the memory; performing consistency comparison on the output data and the expected write-in data to generate memory test information; and outputting the memory test information based on an I2C communication protocol. The method has comprehensive fault detection capability, can realize detection of various types of faults such as fixed faults, partial coupling faults, jump faults, adjacent image sensitive faults and the like, and remarkably improves the fault coverage rate. In addition, the operation process is simple and easy to implement, compatibility is high, work can be carried out without the help of additional testing tools, and the overall testing efficiency is high.

This invention belongs to the field of electronic technology and provides a built-in self-test circuit and method for high-speed interface IP intellectual property cores. The built-in self-test circuit includes: a pseudo-random binary sequence generator for generating corresponding code pattern data; a serializer for converting the code pattern data into serial data; a signal transceiver unit; a deserializer for deserializing the serial data to obtain deserialized data and an encoded clock signal; a synchronization module for performing delay compensation on the deserialized data according to the encoded clock signal and aligning the delay-compensated data with the pseudo-random binary sequence code pattern data to obtain aligned data pairs; and a comparator for performing logical decisions on the aligned data pairs to determine whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit of this invention has a simple structure, does not occupy additional convex resources, and improves the self-test efficiency and accuracy of high-speed interface IP in BIST mode.

Aspects of the present disclosure relate to an integrated circuit that operates a method for functionally secure processing using hardware integrity verification of one or more electronic components. The device can use CRC checksum calculation on the eFuse. In addition, security mechanisms such as triple module redundancy, hardware logic, memory built-in self-testing, or software built-in self-testing may be used in conjunction to ensure the integrity of the eFuse.

The invention discloses a built-in self-test method for detecting and positioning an ILV hard fault in an M3D circuit, which is used for detecting an interlayer interconnection ILV of a monolithic three-dimensional integrated circuit and comprises the following steps of: 1) initializing a test and setting a test mode; 2) applying full '0' excitation, and detecting a fixed fault of the through hole ILV; 3) applying full '1' excitation, and further detecting a fixed fault of the through hole ILV; 4) storing a fixed fault detection result into a scan chain; 5) applying bit-by-bit '1' excitation, detecting a bridging fault of the ILV, and moving a bridging fault detection result into the scanning chain while moving a fixed fault detection result out of the scanning chain; according to the method, special requirements for arrangement of the ILV are avoided, fixed faults and bridging faults in the ILV can be effectively detected and positioned, the time for occupying the ILV in a test mode is short through the time sequence design of parallel detection and shifting operation, and therefore the test efficiency can be improved.

A built-in self-test (BIST) method includes the following operations: a transmitting unit selects a standard sequence, uses the standard sequence and a header corresponding to the standard sequence to generate a test sequence, and transmits the test sequence to a receiving unit via a path under test; and a receiving unit parses the received test sequence to extract the header and a received sequence, obtains the standard sequence corresponding to the header based on the parsed header, and compares the standard sequence with the received sequence to obtain a test result for the path under test.