24 results about "Memory faults" patented technology

The invention discloses a memory diagnosis method and device, equipment and a medium, which are applied to the technical field of servers, and the method comprises the following steps: acquiring a memory data sequence collected according to a preset time interval within a recent preset duration; memory data features are extracted based on the memory data sequence, and the memory data features comprise change trend features; inputting the memory data features into a target memory state prediction model to obtain a memory state prediction result of a future preset duration corresponding to the memory data sequence; wherein the target memory state prediction model is obtained by training a memory data sequence feature sample and a memory state label, and the memory state label represents a memory state of a future preset duration corresponding to the memory data sequence feature sample. Therefore, the memory fault can be predicted in real time, so that problems can be positioned and solved, and the server performance is improved.

This application provides a fault processing method and a computing device. The method is applied to the computing device, and the computing device includes an out-of-band management module and processor firmware. The method includes: The out-of-band management module obtains memory information of a memory; the out-of-band management module determines fault information of the memory based on the memory information, where the fault information includes a fault location, and location precision included in the fault location is located at least at a row address of a fault; the out-of-band management module sends the fault information to the processor firmware; and the processor firmware isolates a memory at the fault location based on the fault information. In the foregoing method, a location that is in the memory and at which the fault occurs can be accurately determined, so that processing precision of the memory fault is improved.

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

Systems, methods, and computer-readable storage devices can include fabric networks for isolating and correcting failures in the fabric network and device failures. The fabric network connects to a group of devices and a host. The group of devices includes at least a target data device, other data devices, and a parity device. A redundant array of independent devices (RAID) engine, which is coupled to the one group of devices, performs an access operation. The fault tolerant engine is provided in a leaf switch of the fabric network. A routing processor determines a path for a request received from the host to the target data device. The routing processor is coupled to the fault tolerant engine, and the routing processor is provided in the leaf switch.

The application belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to an integrated circuit memory fault management method and system based on an NPU processor architecture. First, multi-dimensional detection is carried out specially for the memory size, storage area and handshake protocol effectiveness of a physical address, which changes the status of passive transmission of abnormal signals in the traditional scheme. Then, according to the fault detection result, a control signal is reversely output to intervene in the mapping logic, so as to effectively avoid fault diffusion caused by continuous transmission of abnormal addresses, and when an address abnormality is detected, subsequent physical addresses can be forcibly relocated to a preset safe address area, reliable safety backup is provided, and the running stability is improved.

The invention discloses a computer operation fault rapid identification processing method, and relates to the technical field of data analysis, and the method comprises the following steps: S100, setting a first test parameter according to a mapping relation between a driving square wave and a write-in signal, and testing a memory based on an improved SDRAM test algorithm and the first test parameter to obtain a test result; a cross cubic network of memory addresses is constructed, a numerical matrix is constructed according to the cross cubic network, first calculation is performed based on the numerical matrix, and a fault address and a fault type are output. According to the method, accurate coordinates are provided for subsequent redundancy repair through automatic classification, the number of test steps is reduced by driving the mapping relation between square waves and write-in signals and exciting time sequence and amplitude coupling faults at a time, three-dimensional addresses are subjected to redundancy through the cross cubic network, and the storage fault recognition speed and accuracy are remarkably improved.

The application provides a memory fault detection method and device based on a target fault type, which comprises the following steps: determining a fault type to be detected existing in a memory, and constructing a fault detection sequence library of the memory; determining a corresponding target detection sequence from the fault detection sequence library for any target fault type in the fault type to be detected; performing sequence recombination based on a write operation type for each target detection sequence to obtain an overall write operation detection sequence, inserting a read operation sequence element to obtain a fault detection sequence to be optimized, and finally performing screening processing based on the read operation sequence element to obtain a final fault detection sequence for detecting any target fault type in the fault type to be detected. Through the application, the defect that the test coverage rate for a specific fault type cannot reach 100% due to the fact that the memory fault detection method in the prior art is difficult to detect all fault types of the memory because of the numerous fault types of the memory is overcome.

The invention relates to the technical field of computing devices, in particular to a memory fault isolation method and a computing device.In the starting stage of the computing device, fault identification information corresponding to at least one memory is read, and the fault identification information is used for determining whether an unavailable fault exists in the corresponding memory or not; based on the fault identification information corresponding to the at least one memory, determining a first memory with an unavailable fault; and isolating the first memory. In the embodiment of the invention, the memory fault is pre-checked, the system operation problem is avoided, and the system starting safety and stability are improved.

The invention relates to the technical field of memory fault repair, and particularly discloses a local and global redundancy optimization repair method and system based on data mining, and the method comprises the steps: collecting historical fault data of a memory, cleaning the historical fault data, and extracting fault bit features; carrying out clustering analysis on the extracted fault bit features by adopting a clustering algorithm, and dividing a high-frequency fault region of the fault bit; constructing a distance model of the fault bit and the redundant unit, wherein the distance model fuses the physical distance and the logic distance of the fault bit and the redundant unit; when a new fault bit is detected, preferentially allocating a local redundancy unit with a closer logic distance and / or physical distance based on the distance model for repairing, and updating a resource occupation state of a local redundancy pool; and if the local redundant unit of the area where the new fault bit is located is exhausted, selecting an optimal resource from the global redundant unit according to the distance weight based on the distance model to repair.

This application provides a memory fault processing method: a faulty first storage cell is determined, the first storage cell is isolated, a pressure test is performed on the first storage cell to obtain a fault level of the first storage cell, and a corresponding operation is performed on the first storage cell based on the fault level of the first storage cell, where when the fault level of the first storage cell indicates that the first storage cell is at a first risk level, the operation performed on the first storage cell includes de-isolating the first storage cell. After a faulty storage cell is isolated, a pressure test may be performed on the storage cell to obtain a real fault level of the storage cell. When the fault level of the first storage cell is the first risk level, the first storage cell may continue to be used.

The invention discloses a memory fault processing method and device, a controller, a system, a medium and a product, and relates to the field of fault processing, when a target memory has an IO overtime fault, the memory controller controls to close an IO retry function of the target memory; according to the method and the device, the first target requests of the target memory are received, the first target requests of the target memory are stopped, the first target requests of the current target memory are directly stopped, the IO requests which are not processed in the current target memory can be rapidly processed, and then an error processing thread can be called to carry out fault processing. By closing the IO retry function of the target memory, the time consumed by IO repeated retry is avoided, the IO request which is not processed completely is compressed for timeout fault detection, and the time consumed by retry is avoided, so that an error processing thread can be quickly awakened, the fault processing duration is greatly shortened, and the influence caused by overlong-time request blockage is avoided.

A system can respond to detection or prediction of an uncorrectable error (UE) in memory based on fault-aware analysis. The fault-aware analysis enables the system to generate a determination of a specific hardware element of the memory that is faulty. In response to detection of an error, the system can correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration. Based on a determination of the specific component that likely caused the UE, the system can identify a region of memory associated with the detected UE and mirror the faulty region to a reserved memory space of the memory device for access to data of the faulty region.

Methods and apparatuses directed to memory fault detection mechanisms within die architectures. In some examples, a die package includes decoder logic that receives multiple data words, and a first error correcting code for each of the data words. The decoder logic generates, for each of the data words, a second error correcting code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error status based on the first error correcting code and the second error correcting code that corresponds to each of the data words. The die package also includes error generation logic that receives the error status for the data words from the decoder logic, and generates error data based on a combination of the error statuses for the data words. The error generation logic can store the error data in a memory device.

The present disclosure provides a distributed memory pool fault processing method, system, device and program product, and relates to the technical field of computers. The distributed memory pool fault processing method comprises: in response to an uncorrectable memory fault triggered by a memory operation instruction, determining a physical address that has failed; based on the physical address that has failed and the correspondence relationship between the memory page and the physical address range, determining a first memory page containing the physical address; finding the copy position of the first memory page in the fault processing program table, and determining the corresponding second memory page in the copy position; in the case that the fault processing strategy is remapping, remapping the virtual address accessed by the memory operation instruction from the first memory page to the second memory page; and based on the memory operation instruction, accessing the stored data through the second memory page in the same execution thread.

The present application relates to the field of storage test, and provides a kind of adaptive memory test method, system, equipment, product and medium, including according to sampling ratio sampling, obtain edge phase;Obtain two-dimensional probability eye diagram, construct full convolution inference network, the resolution of two-dimensional probability eye diagram is promoted by full convolution inference network, obtain fine two-dimensional probability eye diagram;The error of fine two-dimensional probability eye diagram is zero probability and offset standard deviation, determine eye diagram adjustment strategy, to adjust fine two-dimensional probability eye diagram, obtain adjustment two-dimensional probability eye diagram;The timing margin and eye diagram offset of adjustment two-dimensional probability eye diagram are calculated, and the compensation strategy is determined according to timing margin and eye diagram offset, and the phase compensation amount is obtained according to the compensation strategy;According to the selection of compensation strategy, determine the area failure probability, generate fault area mark by area failure probability, generate memory fault report according to fault area mark and phase compensation amount, complete memory test.

A memory fault diagnosis device, a System on a Chip (SoC), and a Bloom filter update method and a memory accessibility determination method can operate to diagnose memory faults in a minimum time by using a Bloom filter to detect failed memory areas and thereby determine memory accessibility in a minimum time.

This invention discloses an ECC fault-tolerant structure and memory fault-tolerant design method covering the entire communication path, relating to the field of on-chip memory technology. It addresses the technical problem that existing on-chip memory EDAC technology's protection scope is limited to the on-chip memory cell itself, and introduces additional errors during data transmission, making it difficult to guarantee data integrity. The ECC fault-tolerant structure covering the entire communication path includes a host module, an interconnect bus, and storage components. The host module is configured with an ECC codec. The host module is used to implement access control of the storage components. The interconnect bus is used to implement access routing between the host module and the storage components and establish a connection between them. The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage component. The interconnect bus routes the access to the corresponding storage component based on the access address.

The embodiment of the application discloses a memory error processing method, device, terminal and storage medium, and belongs to the memory field, and comprises the following steps: when a memory fault occurs, it is judged whether a read-write action occurs in a CPU execution context; when the CPU execution context is executed, an interrupt context is acquired, and it is judged whether the memory fault is in a write stage by using the interrupt context; when the write stage is executed, a page table entry is acquired, and it is judged whether it is a file mapping according to the page table entry; when the file mapping is executed, a physical page frame corresponding to the memory fault is determined, all page table entries related to the physical page frame are determined through reverse mapping, a physical page frame entry in the page table entry is atomically deleted, and a physical memory page corresponding to the virtual address is deleted from a file page cache; a free physical memory page is allocated, added to the file page cache, and initialized for a read operation; and the virtual memory and the free physical memory page of the file page cache are associated through the page table entry.

The embodiment of the invention provides a memory fault information collection method and device and a storage medium, relates to the field of data storage, and can avoid fault information report omission. The method is applied to the server, the server comprises a memory, an out-of-band controller and an in-band controller, and the method comprises the steps that in the running process of the server, the in-band controller conducts fault detection on the memory and sends detected fault information to the out-of-band controller; in the restarting process of the server, if the starting mode of the server is cold restarting, the in-band controller determines whether newly-added fault information is stored in a memory or not, and the newly-added fault information is fault information which is not stored in the out-of-band controller; and if the newly added fault information is stored in the memory, the in-band controller sends the newly added fault information to the out-of-band controller.

The embodiment of the invention discloses a memory error processing method and device, a terminal and a storage medium, and belongs to the field of memorys.The memory error processing method comprises the steps that when a memory breaks down, whether a read-write action occurs when a CPU executes a context or not is judged, when the context is executed for the CPU, an interrupt context is obtained, and whether the memory breaks down or not is in a writing stage or not is judged through the interrupt context; in the writing stage, obtaining a page table item, and judging whether file mapping is performed or not according to the page table item; when file mapping is carried out, determining a physical page frame corresponding to a memory fault, determining all page table entries related to the physical page frame through reverse mapping, carrying out atomic deletion on the physical page frame entries in the page table entries, and deleting a physical memory page corresponding to the virtual address from a file page cache; distributing an idle physical memory page, adding a file page cache, and initializing a read operation; and associating the virtual memory with an idle physical memory page of the file page cache through a page table item.

The invention provides a fault processing method, system and device for a distributed memory pool and a program product, and relates to the technical field of computers. The fault processing method for the distributed memory pool comprises the following steps: in response to an uncorrectable memory fault triggered by a memory operation instruction, determining a physical address with the fault; determining a first memory page containing the physical address based on the physical address with the fault and the corresponding relation between the memory page and the physical address range; searching a copy position of the first memory page in the fault processing program table, and determining a corresponding second memory page in the copy position; under the condition that the fault processing strategy is remapping, the virtual address accessed by the memory operation instruction is remapped to the second memory page from the first memory page; and accessing the stored data through the second memory page based on the memory operation instruction in the same execution thread.

The application relates to a cloud host continuous availability method, device, electronic equipment and storage medium. The cloud host continuous availability method comprises the following steps: S1, a sampling test module acquires a server memory CE value; S2, a sampling collection module is responsible for periodically collecting the memory information sampled by the sampling test module, recording the server memory CE value, and comparing the server memory CE value with a preset threshold value; S3, a pre-warning reminding module judges a memory pre-fault according to a preset CE value judgment logic, sends an alarm when a pre-warning reminding threshold value is triggered, and triggers a migration management module to send a cloud host hot migration instruction; and S4, the migration management module receives the alarm of the pre-warning reminding module, triggers a fault processing threshold value, and sends a migration management command to perform virtual machine migration. According to the cloud host continuous availability method, system downtime caused by real memory faults can be avoided in advance, and the continuous availability of business is ensured.

The invention belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to an integrated circuit memory fault management method and system based on an NPU processor architecture, firstly, multi-dimensional detection is specially carried out for the memory size, a storage area and handshake protocol effectiveness of a physical address, and the current situation that abnormal signals are passively transmitted in a traditional scheme is changed. According to a fault detection result, a control signal is reversely output to intervene mapping logic, fault diffusion caused by continuous transmission of an abnormal address is effectively avoided, and when the address is detected to be abnormal, a subsequent physical address can be forcibly relocated to a preset security address area, a reliable security support is provided, and the operation stability is improved.