20 results about "Memory failure" patented technology

This application relates to a method, apparatus, and memory for detecting memory failures. The memory failure detection method performs error detection on read data from the memory array to identify failed cells. When repair triggering conditions are met, a repair operation is performed on the failed cell. The success of the repair is verified. If successful, the failed cell is marked as a normal memory cell and continues to be used. If not, redundant cells are used to replace the failed cell. Performing repair operations on failed cells can repair soft-failure cells, avoiding the replacement of a large number of normal cells by redundant cells, thus consuming redundant resources. This allows limited redundant cells to replace unrepairable hard-failure cells, improving the effective utilization rate of redundant cells and preventing redundant resources from being prematurely consumed by repairable soft-failure cells, thus delaying the depletion rate of redundant resources and extending the working life of the memory.

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

This specification provides a server memory fault detection method, system, and electronic device, capable of early detection and warning of memory faults, ensuring the stability of server system operation. The method includes: monitoring a target server; when the target server triggers a system interrupt signal, collecting basic error information of the memory units corresponding to the system interrupt signal; parsing the basic error information to determine the corresponding memory unit attribute information stored in an internal database; querying and detecting the data content in the internal database to determine the information frequency of the memory unit attribute information corresponding to multiple memory units within a preset time period; determining whether a memory fault exists in the corresponding memory unit based on the information frequency; and when a memory fault is determined to exist in the memory unit, generating corresponding alarm information based on the memory unit attribute information and reporting it.

The application provides a memory fault processing method and device, a storage medium and an electronic device, the method comprising: in response to a memory fault processing instruction, obtaining a heap memory dump file generated by a virtual machine corresponding to the memory fault processing instruction when a memory fault occurs; determining class information of each java class in the heap memory dump file; determining a target java class in each java class according to the class information of each java class; determining a target instance object occupying the most memory and an associated instance object referenced by the target instance object in all instance objects of the target java class; and analyzing the target instance object and the associated instance object to determine fault information having an association relationship with the memory fault. The method provided by the application can quickly and accurately determine factors causing the memory fault.

The utility model relates to industrial automation technical field provides a kind of multifunctional automation monitoring industrial computer, the multifunctional automation monitoring industrial computer includes main controller CPU, FLASH data storage unit and RTC real-time clock unit, wherein, the main controller CPU is electrically connected with FLASH data storage unit and RTC real-time clock unit respectively, the FLASH data storage unit uses double NORFLASH data storage structure, for local double backup storage to acquisition data;The RTC real-time clock unit is used to provide time reference and timestamp record.The utility model has organic integration and electrical connection by main controller CPU and double NORFLASH data storage structure and RTC real-time clock unit, realizes the local synchronous double backup storage and accurate timestamp record of acquisition data, avoids the data loss risk caused by memory failure under single storage mode, and ensures the time traceability of monitoring data, improves the reliability and stability of data storage.

This invention belongs to the field of server testing technology, specifically providing a method, apparatus, and system for detecting server memory slot faults. The method includes the following steps: Powering on the server, configuring the BMC (Browser Control Center) to detect the GPIO status of the memory slots on the motherboard; when the GPIO status is high, determining a memory slot fault and configuring the BMC system event log to display the memory slot status information; during the boot process, configuring the BIOS to obtain memory slot status information from the BMC and, based on the obtained information, masking the faulty memory slots; during self-test, testing the memory in normal memory slots; after self-test completion, displaying the number of detected memory modules and the location information of the masked memory slots on the POST (Power-On Self-Test) interface. This method can accurately detect whether the fault is a memory module or a memory slot fault, enabling users to handle faults more accurately, improving user convenience and enhancing the user experience.

The embodiment of the application relates to the technical field of big data analysis and artificial intelligence, in particular to a memory fault prediction method, an electronic device and a computer readable storage medium. The memory fault prediction method comprises the following steps: obtaining a plurality of log data of a to-be-tested memory; wherein the plurality of log data at least comprises memory error information address data; performing feature engineering construction according to the plurality of log data to obtain a feature data table corresponding to each of the plurality of log data; splicing the feature data table corresponding to each of the plurality of log data to obtain a feature splicing data table; obtaining a fault prediction result of the to-be-tested memory according to the feature splicing data table and a pre-trained fault prediction model; wherein the fault prediction model is obtained by training a pre-collected training data set, and samples in the training data set comprise a plurality of log data of a plurality of memories, so that the accuracy of predicting memory faults can be improved.

This application discloses a memory fault handling method, electronic device, storage medium, and program product, relating to the field of server operation and maintenance technology. This application identifies fault modes such as row failures through multi-dimensional feature recognition and performs reverse mapping based on geometric physical addresses to achieve preventative batch isolation of multiple pages on the same physical row. This avoids the problem of repeated operating system jitter or even crashes caused by fault propagation in related solutions. By establishing a soft-first-hard-later filtering mechanism, PPR requests are suppressed for faults that have been successfully isolated by soft methods, avoiding the consumption of effective and irreversible hardware repair resources. Simultaneously, a dynamic gating strategy based on the remaining resource status repairs only high-risk faults when resources are exhausted, extending the lifespan of the memory module. The operating system feeds back the soft isolation execution results to the firmware, solving the blind spot of no one taking over after soft isolation failure in related solutions, ensuring that each memory risk point has a definite final handling status, and effectively reducing the risk of server downtime.

The present application relates to a kind of machine learning code library memory fault injection vulnerability detection methods based on bit flip, comprising the following steps: S1, add extension function to programmable compiler, insert detection instruction to sensitive code in machine learning code library, to detect the code point position at risk with dynamic analysis method;S2, using machine learning model and data set under actual application scenario, collect running data, calculate and find risk sensitive code point position, i.e. the imbalance degree of sensitive instruction is calculated and analyzed, determine the risk sensitive instruction set vulnerable to memory fault injection vulnerability;S3, by injecting bit flip into actual memory hardware, obtain the fault injection vulnerability distribution profile of actual memory hardware;S4, match piece by piece, obtain vulnerability sensitive instruction set.The beneficial effect is to reduce or remove the risk and harm caused by tampering machine learning code library, ensure the security and integrity of machine learning model.

Described are systems and methods for memory failure analysis based on bitline threshold voltage distributions. An example method of implementing a failure type prediction model includes: receiving, by a processing device, a first failure-related dataset reflecting a first bitline threshold voltage distribution associated with a first memory device; determining, based on the first failure-related dataset, a first failure type distribution for the first memory device; creating a training dataset comprising the first failure-related dataset and the first failure type distribution; and training, using the training dataset, a failure type prediction model to determine, for a second memory device, a second failure type distribution based on a second failure-related dataset comprising second bitline threshold voltage data associated with a second memory device.

The memory failure storage unit repair method, device, equipment and medium provided by the embodiments of the present disclosure comprise: in response to receiving an activation operation submitted by a target object, obtaining a target row address corresponding to the activation operation; determining a target storage array to which a word line receiving the target row address belongs according to address information of a first address interval in the target row address; when the target row address is the same as a failure row address, determining a target redundant word line receiving the target row address according to the target storage array to which the word line receiving the target row address belongs. The use of the redundant word line of the storage array in which the failure word line is located to repair the failure storage unit is avoided, thereby increasing tRCD within the chip and affecting the read-write efficiency of the chip.

The application relates to the technical field of server fault protection, in particular to an AI prediction and dynamic repair protection system for server memory faults, which comprises a data acquisition module, a feature extraction module, a state modeling module, a risk prediction module and a repair decision module. The data acquisition module continuously acquires memory running original data streams from a server cluster; the feature extraction module extracts multi-dimensional abnormal fluctuation features from the original data streams and integrates the multi-dimensional abnormal fluctuation features into a multi-dimensional abnormal feature vector; the state modeling module constructs a time-varying memory health state field with a timestamp, a server node number and a feature component value as axes by using the multi-dimensional abnormal feature vector; the risk prediction module applies a space-time convolution network to identify a fault propagation mode and outputs a risk field; and the repair decision module generates an active repair decision based on the risk field. The system can realize accurate prediction and active protection of memory faults and guarantee stable operation of the server cluster.

This disclosure provides a memory fault injection device, method, and related apparatus, relating to the field of computer technology, particularly to the fields of autonomous driving, data processing, and memory fault injection. The specific implementation scheme includes: at least one fault injection module, which establishes an electrical connection with the fault injection point of the memory under test via a probe module. The fault injection point is a physical contact point located on the signal transmission path between the memory controller and the memory chip of the memory under test; and a controller, which responds to an injection signal and controls the fault injection module to perform fault injection on the memory under test.

The present embodiment relates to a memory failure analysis method that is performed by a memory test apparatus. The memory failure analysis method includes setting a test area of a memory under test (MUT), inputting a test pattern to the set test area, receiving a test result from the MUT, and an updating operation including operation (a) of storing failure information extracted from the test result and operation (b) of compressing, updating, and storing failure information, which is stored in a failure accumulator, using the stored failure information, wherein a first failure detector and a second failure detector alternately perform operation (a) and operation (b), and the test area is a non-linear area.

This disclosure provides an antifuse memory array circuit and a memory. The antifuse memory array circuit includes: an antifuse memory array comprising multiple antifuse memory cells arranged in an array and multiple bit lines, each bit line being coupled to a column of antifuse memory cells; and a level setting circuit coupled to each bit line, configured to set the level of each bit line to a preset level when the antifuse memory array is in an idle state. Since the level of each bit line is determined in the idle state, the antifuse memory array is prevented from burning out due to excessive transient current when transitioning from an idle state to an operating state, thereby reducing the memory failure rate.

The application discloses a memory fault processing system and method, electronic equipment and program product, and relates to the technical field of computers. The system comprises a management controller, a basic input / output system and an operating system connected through a bus. The basic input / output system responds to a configuration request, acquires first error data and interacts with the operating system. The management controller constructs isolated first and second processes, listens to acquisition parameter adjustment signals in the error data acquisition process and adjusts adaptively. The first process acquires first error data through the bus and second error data through an out-of-band interface, the second process predicts memory faults accordingly and sends signals, the first process triggers fault repair operations, and the operating system performs fault page isolation operations. The application can solve the problems of related technologies, such as the influence of high-frequency data acquisition operations on device performance, increased energy consumption and resource waste, realize low-interference memory fault prediction and repair, and effectively improve memory reliability and availability.

This invention discloses a memory fault handling system, method, electronic device, and program product, relating to the field of computer technology. The system includes memory, a management controller, and a central processing unit (CPU). The CPU reads system operation data from the memory via a physical link and determines memory error information. The management controller constructs two isolated processes. During the process of the first process collecting memory error information through an out-of-band interface, it listens for a trigger signal to adjust the collection parameters and adjusts the initial data collection parameters according to the signal type of the trigger signal. The second process receives the memory error information sent by the first process and triggers a fault repair operation when a memory fault is predicted based on the memory error information. This invention can solve the problems of high-frequency data collection operations affecting device performance, increasing energy consumption, and wasting resources in related technologies, enabling low-interference memory fault prediction and repair, and effectively improving memory reliability and availability.

This application provides a memory fault handling method and apparatus. The method includes: acquiring memory fault data; inputting the memory fault data into a pre-trained fault prediction model to obtain a fault identification result; and if the fault identification result is a restartable and repairable fault, restarting the device under test. This application reduces the repair time for memory faults in the device under test and improves the efficiency of memory fault handling by directly repairing the memory fault through restarting after determining that the memory fault is a restartable and repairable fault type, thereby ensuring the effective implementation of user transactions.