125 results about "Memory failure" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention discloses a memory fault processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers.The method comprises the steps that when a memory line fault exists in a memory of a target system, an isolation operation is triggered for a target physical address, the target physical address at least comprises the physical address of the fault line with the memory line fault in the memory, the technical problem of system downtime caused by the fact that the memory line fault cannot be rapidly processed in the related technology is solved, the isolation process is started for the target physical address in time when the memory line fault is detected, and the system downtime is reduced. Performance reduction and data error accumulation caused by the fact that the fault line continues to participate in data reading and writing are avoided, and then the technical effect of reducing the risk of system downtime is achieved.

The disclosure herein describes training and using an uncorrectable error (UE) state prediction model based on telemetry error data. Sets of UE state labels and non-UE state labels are generated from a first set of collected telemetry data, wherein the UE state labels each reference a UE and telemetry data of an interval prior to the referenced UE. Statistical features are extracted from telemetry data of the sets of UE state labels and non-UE state labels, and the extracted statistical features are used to train a UE state prediction model. A second set of collected telemetry data is obtained, and a UE event is predicted based on the second set of collected telemetry data using the trained UE state prediction model. A preventative operation is performed on a memory page of the system based on the predicted UE event, whereby the predicted UE event is prevented from occurring.

The invention discloses a memory fault management system and method, a server and electronic equipment, and relates to the technical field of computers, the memory fault management system comprises a processing circuit of a hardware memory, a hardware layer and a processor are arranged on the processing circuit, and the processor is further divided into a kernel layer, a user layer and an input and output layer. Through cooperative work of the hardware layer and each software layer, hierarchical detection, classified processing and automatic isolation of memory error data are realized, and server downtime caused by memory fault error data is effectively prevented. And meanwhile, through a linkage mechanism of a kernel mode and a user mode and in combination with visual display, the monitorability and maintainability of memory errors are enhanced, operation and maintenance personnel can quickly position and repair problems conveniently, and the operation and maintenance cost of the system is reduced.

A memory mapping method includes: obtaining a memory failed row address of a first memory; obtaining, by a matching and searching circuit, an address mapping table, where the address mapping table includes a mapping relationship between the memory failed row address and a memory remapping row address corresponding to the memory failed row address; and when an access target of the first memory is the memory failed row address, obtaining, based on the address mapping table, the memory remapping row address to which the memory failed row address is mapped, where a memory area indicated by the memory remapping row address is in reserved space of the first memory.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The file system comprises a plurality of first file systems, and the plurality of first file systems are mounted on different partitions of the same storage medium or mounted on different storage media; and the second file system is mounted on the plurality of first file systems and is used for carrying out fault-tolerant verification on the consistency data in the memory metadata of the plurality of first file systems among the plurality of first file systems. Thus, the second file system is overlaid on the original first file system, fault-tolerant verification can be carried out on the consistency data in the memory metadata of the first file system between the first file systems, redundant backup does not need to be carried out on the consistency data in the first file system, the memory overhead is reduced, and the memory efficiency is improved. The memory failure is covered with low memory overhead.

The embodiment of the invention provides a fault prediction method, a fault processing method and a fault processing system.The fault prediction method comprises the steps that a memory error event of a cloud server is obtained, and the memory error event has corresponding event information; based on the event information, extracting a first distribution feature of the memory error event in a basic storage unit of the cloud server memory; determining a second distribution feature of the memory error event in the instance according to the first distribution feature and an affiliation relationship between the basic storage unit and the instance; and on the basis of the second distribution feature, a fault prediction model is utilized to determine a predicted fault instance, and the fault prediction model is obtained based on sample distribution feature training of the sample memory fault event on the instance. By determining the distribution characteristics of the instance granularity, fault prediction of the instance granularity is realized based on the distribution characteristics of the instance granularity, and the refinement degree of fault prediction is improved.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

A Redundant Array of Independent Disks (RAID) scheme can be used to allow recovery from a memory failure. RAID 6 can be used to recover data from up to two catastrophic failures. Typically, a hardware encoder is used to generate parities of the RAID 6 protection scheme, and a separate hardware decoder is used in the data recovery process. In an example data storage device described herein, some of the components of the hardware encoder are used to perform the data recovery process, thereby eliminating the need for a separate, additional hardware component.

The invention discloses a memory fault information processing method, a memory fault prediction method and electronic equipment, and relates to the field of information processing.The memory fault information processing method comprises the steps that a preset interrupt processing program based on UEFI is triggered, and fault information of a memory is obtained, the fault information represents at least one of recoverable faults and unrecoverable faults of the memory; generating target information according to the fault information; and uploading the target information to a target controller.

This application relates to a method, apparatus, and memory for detecting memory failures. The memory failure detection method performs error detection on read data from the memory array to identify failed cells. When repair triggering conditions are met, a repair operation is performed on the failed cell. The success of the repair is verified. If successful, the failed cell is marked as a normal memory cell and continues to be used. If not, redundant cells are used to replace the failed cell. Performing repair operations on failed cells can repair soft-failure cells, avoiding the replacement of a large number of normal cells by redundant cells, thus consuming redundant resources. This allows limited redundant cells to replace unrepairable hard-failure cells, improving the effective utilization rate of redundant cells and preventing redundant resources from being prematurely consumed by repairable soft-failure cells, thus delaying the depletion rate of redundant resources and extending the working life of the memory.

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

The application provides a memory fault area identification method and device, electronic equipment and storage medium. The method comprises the following steps: checking whether the current memory configuration of a system is changed compared with the memory configuration at the last operation; if the current memory configuration is not changed, obtaining a current suspicious memory area list of the system, wherein the current suspicious memory area list records the fault addresses of the current suspicious memory area; and performing shielding processing on the corresponding memory area according to the current suspicious memory area list. By shielding the fault memory area, the use of the fault memory area by the system is isolated, and the reliability of the system is effectively improved.

The present application relates to the technical field of memories, and provides a memory fault processing method, an apparatus, a memory controller, a chip and a device. The method comprises: on the basis of a first sampling time policy, performing correctable error (CE) fault sampling on a memory to obtain CE fault data, the CE fault data comprising address information of a CE fault in the memory; on the basis of the CE fault data, processing the fault of the memory; and, on the basis of a second sampling time policy, performing CE fault sampling on the memory, the first sampling time policy being different from the second sampling time policy. The present application can avoid effects of UCE faults of memories on computing devices as much as possible.

This invention belongs to the field of computer firmware technology, specifically relating to a method for recording server memory faults. The method of this invention, after a server memory is missing or a memory fault occurs, obtains the server memory fault status by checking logs, thereby quickly locating the problem of the server's inability to boot normally, while minimizing the consumption of BMC system resources.

A chip, a method of controlling memory failure repair, an electronic device, a non-transitory computer-readable storage medium, and a computer program product are provided. The chip comprises a power supply management unit, a repair management unit and a repair execution unit, wherein the power supply management unit is configured to provide a repair starting signal for a first power supply domain in a plurality of power supply domains through a power-on condition of the first power supply domain; the repair management unit is configured to determine first information at least according to a repair starting signal for the first power domain, and the first information comprises information indicating that a memory of the first power domain needs to be subjected to memory fault repair at present; sending a starting signal and first information to a repair execution unit; and the repair execution unit is configured to perform memory fault repair on the memory in the first power domain according to the starting signal and the first information.

The application provides a non-associated grouping memory failure unit analysis method, first, the position information of all memory failure units is obtained through a chip tester to form a fault bit map; then, based on the position information characteristics in the fault bit map, all the failure units in the fault bit map are grouped based on a grouping principle to form a multi-failure group and a single-failure group; then, based on the repair principle of the memory failure unit, the failure units in each group are analyzed for repair to determine whether the failure units of the memory chip can be repaired; if the failure units of the memory chip can be repaired, a repair solution is given. The application divides all the failure units of the memory chip into independent multi-failure groups and single-failure groups based on the non-associated grouping memory failure unit analysis method, and then analyzes and finds the redundancy repair solution of each failure group, which can more reasonably allocate the redundancy resources and effectively improve the repair efficiency of the memory failure units.

Methods and apparatus relating to a memory failure detection mechanism within a die architecture. In some examples, a die package includes decoder logic that receives a plurality of data words, and a first error correction code for each of the data words. The decoder logic generates, for each of the data words, a second error correction code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error state based on the first error correction code and the second error correction code corresponding to each of the data words. The die package also includes error generation logic that receives the error state for the data word from the decoder logic and generates error data based on a combination of the error states for the data word. The error generation logic may store the error data in a memory device.

The present disclosure provides a memory fault processing method, device and equipment and storage medium. The memory fault processing method comprises: obtaining interrupt information, the interrupt information being used to represent that an abnormality occurs in the running process of the terminal device; when the interrupt information is preset interrupt information, determining that the abnormality is a memory fault abnormality; and storing memory fault information into a pre-established abnormality information table. The present disclosure sets a preset interrupt information representing a memory fault abnormality, compares the interrupt information obtained when the terminal device has an abnormality with the preset interrupt information, to quickly determine whether the abnormality type of the terminal device is a memory fault abnormality, thereby saving the time cost of abnormality troubleshooting; and stores the memory fault information corresponding to the memory fault abnormality into the pre-established abnormality information table, so as to facilitate the user to quickly determine the position of the memory fault abnormality by reading the abnormality information table, thereby saving the analysis time cost, and facilitating the user to timely process the memory fault abnormality.

A memory fault handling method, comprising: predicting in a memory a region that is at risk of faults, so as to obtain a first region; determining a usage type of the first region, wherein the usage type is a user-mode memory or a kernel-mode memory; when the usage type of the first region is the kernel-mode memory, using redundant resources in the memory to repair the first region; and when the usage type of the first region is the user-mode memory, using a second region in the memory to repair the first region, wherein the second region is a region that is not at risk of faults in the memory, and the second region does not belong to the redundant resources. In this way, on the basis of the usage of a risky region in a memory, redundant resources are selectively used for repair, such that redundant resources can be saved on to the greatest extent and the redundant resources are reserved for faults of a kernel-mode memory that have greater impact, thereby lowering the risk of system crashes.

The invention provides a memory fault processing method and device, and is applied to the technical field of computers. The method comprises the following steps: in a system operation stage, if error information exists in a mirror image memory, repairing a fault line corresponding to the error information by adopting a software repairing technology; if the repair of the fault line fails, marking the target memory page corresponding to the fault line as a decommissioning page, so that the target memory page is not subsequently allocated or used any more; and recording a repair request of adopting a hardware repair technology for the target memory page.

The invention discloses a running-state-oriented memory fault risk assessment and adaptive diagnosis method and system, and relates to the technical field of memory running management.The method comprises the steps that S1, running-state memory monitoring data are collected and preprocessed; s2, generating a cross-layer difference triple set, performing difference direction judgment on a cross-layer difference triple, and identifying cross-layer inconsistent fragments; s3, constructing a cross-layer risk index set, performing cross-layer fault risk quantitative analysis on each inconsistent fragment, performing risk grade division based on a quantitative analysis result, and generating a corresponding risk grade label; and S4, carrying out risk response operation on the inconsistent fragments, carrying out response stability evaluation, and generating a final risk response result set. The problem that in the prior art, cross-layer difference sources cannot be accurately recognized in a multi-layer memory access link, so that running state fault risk judgment is prone to being interfered by access jitter and affected by virtualization scheduling offset is solved.

Computer nodes associated with a cluster store a distributed database. The computer nodes are polled to retrieve their individual nodal query states. A coordinator node then merges the individual nodal query states to determine an overall query state associated with the distributed database. The coordinator node, though, has a memory capacity that can be overcome by some nodal query states. The coordinator node thus imposes a data size limit on the nodal query states to prevent memory failures. The coordinator node specifies the data size limit during any polling cycle, and the coordinator node receives compliant nodal query states that satisfy the data size limit. The coordinator node may adjust or revise the data size limit for subsequent polling cycles, based on a count of the nodal query states yet to be retrieved. The data size limit thus ensures that the memory capacity is not overcome during any polling cycle.

Described are systems and methods for memory failure analysis based on bitline threshold voltage distributions. An example method of implementing a failure type prediction model includes: receiving, by a processing device, a first failure-related dataset reflecting a first bitline threshold voltage distribution associated with a first memory device; determining, based on the first failure-related dataset, a first failure type distribution for the first memory device; creating a training dataset comprising the first failure-related dataset and the first failure type distribution; and training, using the training dataset, a failure type prediction model to determine, for a second memory device, a second failure type distribution based on a second failure-related dataset comprising second bitline threshold voltage data associated with a second memory device.

A system includes a processor and a memory. The processor locates a first memory chip that is faulty in a memory. After the first memory chip is isolated or replaced, the processor may reset the first memory chip when other memory chips in the memory are maintained to work normally. When a fault occurs in a memory chip in the memory, after the first memory chip that is faulty is isolated or replaced, the processor may independently reset the first memory chip without affecting the other memory chips in the memory. Resetting the first memory chip enables the first memory chip to restore to normal. A memory chip that can be normally used is used as a redundant memory chip or may continue to be used.

The invention discloses a memory fault prediction model training method, a memory fault processing method and electronic equipment, and the method comprises the steps: obtaining a first historical memory operation log corresponding to a first server, and a second historical memory operation log corresponding to a second server, obtaining corresponding segmented memory operation logs based on the first historical memory operation log and the second historical memory operation log, obtaining first space error report data and second space error report data corresponding to the segmented memory operation logs, and determining feature set data, and training a preset initial memory fault prediction model based on the feature set data to obtain a trained target memory fault prediction model. And performing fault prediction on the target server based on the trained target memory fault prediction model. Based on the method provided by the invention, the accuracy of server memory fault prediction can be improved.

This specification provides a server memory fault detection method, system, and electronic device, capable of early detection and warning of memory faults, ensuring the stability of server system operation. The method includes: monitoring a target server; when the target server triggers a system interrupt signal, collecting basic error information of the memory units corresponding to the system interrupt signal; parsing the basic error information to determine the corresponding memory unit attribute information stored in an internal database; querying and detecting the data content in the internal database to determine the information frequency of the memory unit attribute information corresponding to multiple memory units within a preset time period; determining whether a memory fault exists in the corresponding memory unit based on the information frequency; and when a memory fault is determined to exist in the memory unit, generating corresponding alarm information based on the memory unit attribute information and reporting it.