202 results about "Memory failure" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

A method for repairing a memory fault includes obtaining fault information of a memory, where the fault information includes a type of a fault; obtaining first repair resource information, where the first repair resource information includes a type of a first repair resource, and the first repair resource is capable of repairing the fault; determining first repair information based on the fault information and the first repair resource information, where the first repair information is used to indicate a BIOS to repair the fault by using a second repair resource, and the second repair resource is a repair resource with a smallest granularity in the first repair resource. The BIOS repairs the fault based on the first repair information.

The invention provides a memory fault processing method and device, electronic equipment and a readable storage medium, and in the method, the electronic equipment can determine a first storage unit with a fault and isolate the first storage unit. The electronic equipment can carry out pressure measurement on the first storage unit to obtain the fault level of the first storage unit, the electronic equipment executes corresponding operation on the first storage unit according to the fault level of the first storage unit, and when the fault level of the first storage unit indicates that the first storage unit is in a first risk level, the first storage unit is in a second risk level. The operations include de-isolating the first memory cell. According to the method and the device, after the faulted storage unit is isolated, the voltage of the storage unit can be measured, and the real fault level of the storage unit is obtained. Wherein when the fault level of the first storage unit is the first risk level, the electronic equipment can remove isolation of the first storage unit, the first storage unit can be continuously used, and the number of available storage units can be increased.

The invention relates to the technical field of electric digital data processing, and discloses a memory fault detection and hardware automatic replacement system and method, which comprises a memory fault detection module, a control module, an address mapping module and a hardware automatic replacement module, the memory fault detection module is used for scanning, detecting and positioning specific faults of the memory and recording detected fault information; the control module is used for receiving and analyzing damaged address information sent by the memory fault detection system. According to the invention, the number of the reserved address spaces is set through the memory, the reserved address spaces can be used as standby areas when the memory is greatly damaged, and continuous operation of the system can be ensured in emergency by presetting the reasonable number of the reserved address spaces; therefore, the equipment can be normally used when large-area fault damage exists in the equipment, and the service life of the system is prolonged.

The invention discloses a memory fault processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers.The method comprises the steps that when a memory line fault exists in a memory of a target system, an isolation operation is triggered for a target physical address, the target physical address at least comprises the physical address of the fault line with the memory line fault in the memory, the technical problem of system downtime caused by the fact that the memory line fault cannot be rapidly processed in the related technology is solved, the isolation process is started for the target physical address in time when the memory line fault is detected, and the system downtime is reduced. Performance reduction and data error accumulation caused by the fact that the fault line continues to participate in data reading and writing are avoided, and then the technical effect of reducing the risk of system downtime is achieved.

The disclosure herein describes training and using an uncorrectable error (UE) state prediction model based on telemetry error data. Sets of UE state labels and non-UE state labels are generated from a first set of collected telemetry data, wherein the UE state labels each reference a UE and telemetry data of an interval prior to the referenced UE. Statistical features are extracted from telemetry data of the sets of UE state labels and non-UE state labels, and the extracted statistical features are used to train a UE state prediction model. A second set of collected telemetry data is obtained, and a UE event is predicted based on the second set of collected telemetry data using the trained UE state prediction model. A preventative operation is performed on a memory page of the system based on the predicted UE event, whereby the predicted UE event is prevented from occurring.

Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

The invention discloses a memory fault prediction method and device, a chip, equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps that error position distribution of an error correction unit associated with a memory is obtained, the memory comprises at least one memory particle, the error correction unit comprises a plurality of data bits obtained from a plurality of storage units of the memory through continuous multiple burst reading, and each data bit corresponds to one storage unit in the memory; the error position distribution is used for indicating the position of an error data bit in a plurality of data bits, and the error position distribution causes the occurrence of CE in the memory; a memory fault model is obtained, the memory fault model comprises at least one reference position distribution, and the reference position distribution is associated with the UCE of the memory; according to the similarity between the error position distribution and the at least one reference position distribution, a prediction result is output, and the prediction result is used for indicating the probability that the UCE occurs in the memory. The method is beneficial to improving the timeliness of memory fault prediction.

The invention discloses a fault detection method for a persistent memory server, and relates to the technical field of fault detection and persistent memories, and the method comprises the following steps: collecting various historical index data from a persistent memory during the operation of a system, carrying out the preprocessing, and constructing an initial sample set; expanding the initial sample set by using a generative adversarial network to obtain an expanded sample set; a CNN-LSTM model is constructed, the expanded sample set is used for model training until network convergence, and a trained persistent memory fault prediction model is obtained; and monitoring the running state of the system in real time by using the trained persistent memory fault prediction model, predicting potential faults of the persistent memory, and determining whether to send out fault early warning or not by setting a threshold value. According to the method, the fault detection accuracy can be improved, memory faults can be found in time, measures are taken for repairing, and stable operation of the system is ensured.

This application discloses a memory fault processing method and apparatus, and a storage medium, to improve memory fault repair efficiency. An out-of-band controller obtains fault information of a memory. The out-of-band controller determines a fault severity of a target cache block based on the fault information and a target replacement cache block based on the fault severity of the target cache block. The target replacement cache block is used to replace the target cache block, the target replacement cache block is a cache block currently used to replace a historically faulty cache block. The out-of-band controller sends a repair request to a central processing unit (CPU), where the repair request is used to request the CPU to perform fault repair on the target cache block.

The invention discloses a memory fault management system and method, a server and electronic equipment, and relates to the technical field of computers, the memory fault management system comprises a processing circuit of a hardware memory, a hardware layer and a processor are arranged on the processing circuit, and the processor is further divided into a kernel layer, a user layer and an input and output layer. Through cooperative work of the hardware layer and each software layer, hierarchical detection, classified processing and automatic isolation of memory error data are realized, and server downtime caused by memory fault error data is effectively prevented. And meanwhile, through a linkage mechanism of a kernel mode and a user mode and in combination with visual display, the monitorability and maintainability of memory errors are enhanced, operation and maintenance personnel can quickly position and repair problems conveniently, and the operation and maintenance cost of the system is reduced.

A memory mapping method includes: obtaining a memory failed row address of a first memory; obtaining, by a matching and searching circuit, an address mapping table, where the address mapping table includes a mapping relationship between the memory failed row address and a memory remapping row address corresponding to the memory failed row address; and when an access target of the first memory is the memory failed row address, obtaining, based on the address mapping table, the memory remapping row address to which the memory failed row address is mapped, where a memory area indicated by the memory remapping row address is in reserved space of the first memory.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The embodiment of the invention provides a server fault processing method, a storage medium and electronic equipment, and the method comprises the steps: obtaining first time information, the first time information comprises at least one of a first moment and a second moment, the first moment is a moment when a first fault occurs, and the second moment is a moment when a second fault occurs; acquiring second time information, wherein the second time information is a third moment when the voltage regulator of the power management integrated chip is powered on; and generating a target control instruction set based on the first time information and the second time information, wherein the target control instruction set is used for controlling the server to execute a preset fault processing operation. According to the method and the device, the problems of temporary fault-free detection of the memory of the integrated PMIC chip and corresponding fault processing measures and methods in the prior art are solved.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

The present application provides a memory fault processing method, an apparatus, an electronic device and a readable storage medium. The method comprises: determining a faulty first storage unit (S801); isolating the first storage unit (S802); performing stress testing on the first storage unit, so as to obtain a fault level of the first storage unit (S803); and, according to the fault level of the first storage unit, executing a corresponding operation on the first storage unit, wherein when the fault level of the first storage unit indicates that the first storage unit is at a first risk level, the operation executed on the first storage unit comprises releasing the first storage unit from isolation (S804). In the present application, after the faulty storage unit is isolated, the storage unit may be further subjected to stress testing so as to obtain the actual fault level of the storage unit. When the fault level of the first storage unit is the first risk level, the electronic device may release the first storage unit from isolation, and the first storage unit may be continuously used; thus, the present application can increase the number of available storage units.

The file system comprises a plurality of first file systems, and the plurality of first file systems are mounted on different partitions of the same storage medium or mounted on different storage media; and the second file system is mounted on the plurality of first file systems and is used for carrying out fault-tolerant verification on the consistency data in the memory metadata of the plurality of first file systems among the plurality of first file systems. Thus, the second file system is overlaid on the original first file system, fault-tolerant verification can be carried out on the consistency data in the memory metadata of the first file system between the first file systems, redundant backup does not need to be carried out on the consistency data in the first file system, the memory overhead is reduced, and the memory efficiency is improved. The memory failure is covered with low memory overhead.

The invention discloses a test, device, system and equipment for a memory fault recovery function and a storage medium, and relates to the technical field of servers. In the whole test process, a user only needs to complete the test triggering operation, and does not need to acquire serial port information for many times for contrastive analysis, so that the operation steps are simple, and errors are not easy to occur; and in the whole test process, the operating system only needs to be restarted once, and finally, whether the memory fault repair function is normally operated or not is determined by obtaining the system event log in the substrate management controller, so that the test efficiency of the memory fault repair function is high.

The invention provides a memory fault prediction method and a related device, which can be applied to a memory fault prediction scene. The method comprises the steps that fault information is obtained firstly, the fault information comprises a physical address of a first correctable error CE occurring in a first memory bank in a memory module and a physical address of a first uncorrectable error UCE occurring in the memory module, and the physical address of the first CE comprises a row address, a column address and a bank address of the first CE in the memory module; the physical address of the first UCE comprises a row address, a column address and a bank address of the first UCE in the memory module. And training a model based on the physical address of the first CE and the physical address of the first UCE, wherein the model is used for predicting the physical address of the potential UCE based on the physical address of the CE. According to the method and the device, the model is trained by screening out the fault information of the bank granularity, so that bank-level prediction precision can be realized, namely, whether UCE can occur in a certain region on the bank can be predicted, and the prediction precision and accuracy are greatly improved.

The invention provides a non-associated grouped memory failure unit analysis method, which comprises the following steps of: firstly, obtaining position information of all memory failure units through a chip tester to form a fault bitmap; secondly, grouping all fault units in the fault bitmap based on a grouping principle according to position information characteristics in the fault bitmap to form a multi-fault group and a single-fault group; performing repair analysis on the fault unit in each group on the basis of a repair principle of the memory failure unit, and judging whether the failure unit of the memory chip can be repaired or not; and if the failure unit of the memory chip can be repaired, giving a repair solution. According to the non-association grouping type memory failure unit analysis method, all the failure units of the memory chip are divided into the multi-failure group and the single-failure group which are mutually independent, and then the redundancy repair scheme of each failure group is analyzed and searched independently, so that redundancy resources can be distributed more reasonably; and the repair efficiency of the memory failure unit is effectively improved.

The invention discloses a memory fault management method and device, a medium and a server, relates to the field of servers, and is used for solving the problems of system instability and reliability caused by memory faults. After the processor receives the fault alarm information of the target memory, the processor firstly analyzes the alarm information and verifies the validity of the alarm information, and if the fault information is valid, a target physical address and a target power supply corresponding to the target memory are determined according to the fault alarm information; and isolating the target memory according to the target physical address, and sending a power-off instruction to the target power supply so as to power off the target memory. The fault memory is allowed to be isolated and replaced when the server runs, the maintainability of the memory is improved, the service interruption caused by the memory fault can be reduced, the maintenance cost is reduced, and the downtime is shortened.

The embodiment of the invention provides a fault prediction method, a fault processing method and a fault processing system.The fault prediction method comprises the steps that a memory error event of a cloud server is obtained, and the memory error event has corresponding event information; based on the event information, extracting a first distribution feature of the memory error event in a basic storage unit of the cloud server memory; determining a second distribution feature of the memory error event in the instance according to the first distribution feature and an affiliation relationship between the basic storage unit and the instance; and on the basis of the second distribution feature, a fault prediction model is utilized to determine a predicted fault instance, and the fault prediction model is obtained based on sample distribution feature training of the sample memory fault event on the instance. By determining the distribution characteristics of the instance granularity, fault prediction of the instance granularity is realized based on the distribution characteristics of the instance granularity, and the refinement degree of fault prediction is improved.

Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

A Redundant Array of Independent Disks (RAID) scheme can be used to allow recovery from a memory failure. RAID 6 can be used to recover data from up to two catastrophic failures. Typically, a hardware encoder is used to generate parities of the RAID 6 protection scheme, and a separate hardware decoder is used in the data recovery process. In an example data storage device described herein, some of the components of the hardware encoder are used to perform the data recovery process, thereby eliminating the need for a separate, additional hardware component.

The invention discloses a dynamic real-time multi-memory fault collection method based on a server, and relates to the technical field of computer system monitoring and fault management, and the method comprises the following steps: after the server is powered on and started, collecting time required by communication; taking the shortest communication time as a first time threshold value; starting to monitor a memory error register in the ECC register; obtaining error data in the memory error register and data related to memory errors in the system log; determining a query timestamp according to the data related to the memory error in the system log, performing query from the query timestamp, gradually obtaining the data related to the memory error in the system log, and reporting the data to a system; and the system sets a second time threshold value, and after the time for the system to monitor the memory fault reaches the preset second time threshold value, monitoring is ended. According to the method, the memory state can be dynamically monitored, a response is made immediately when a problem occurs instead of depending on regular inspection, and the fault diagnosis and repair efficiency is improved.

The invention discloses a memory fault information processing method, a memory fault prediction method and electronic equipment, and relates to the field of information processing.The memory fault information processing method comprises the steps that a preset interrupt processing program based on UEFI is triggered, and fault information of a memory is obtained, the fault information represents at least one of recoverable faults and unrecoverable faults of the memory; generating target information according to the fault information; and uploading the target information to a target controller.

The invention discloses a memory leak detection method and device based on KNN and a medium, belongs to the technical field of intelligent operation and maintenance, and is used for solving the technical problems that an existing memory anomaly detection algorithm is mainly oriented to universal memory faults such as resource bottleneck and insufficient capacity and is not accurate enough in memory leak fault recognition and lagged in fault recognition. The method comprises the following steps: acquiring a memory monitoring index data set of a target system in a preset time period; determining whether any data point is an abnormal point or not based on the distance between any data point in the memory monitoring index data set and other data points; and if the number of the abnormal points in the memory monitoring index data set exceeds a preset number threshold, determining that the target system has a memory leak fault. By means of the method, targeted fault detection on specific fault scenes such as memory leakage is achieved, and when the target system has the memory leakage fault, the fault of memory leakage of the target system can be accurately and timely detected.

To accurately determine the presence or absence of a memory failure.SOLUTION: In a data processing apparatus 11, respective buffer memories BM of a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2 store therein data formed of a plurality of bits. A CPU 11A reads data from a buffer memory BM, inverts a plurality of bits to generate bit-inverted data resulting from inverting respective values of the plurality of bits, writes the bit-inverted data to the buffer memory BM at a first time, reads the bit-inverted data from the buffer memory BM at a second time later than the first time, and determines the presence or absence of a failure of the buffer memory BM by comparing first data being the bit-inverted data written in the buffer memory BM at the first time with second data being the bit-inverted data read from the buffer memory BM at the second time.SELECTED DRAWING: Figure 1