87 results about "Memory failure" patented technology

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

In some examples, a system monitors for a memory fault associated with execution of software. Based at least on receiving an indication of a possible memory fault, the system scans a first area of the memory based on a data structure that indicates that the first area of the memory stores a portion of parameters of the software that affect an accuracy of the software if there is a memory fault in the first area of the memory. Based at least on the scanning indicating that there is a memory fault in the first area of the memory, the system remaps the portion of parameters of the software from the first area to a second area of the memory that is determined to be free.

A Redundant Array of Independent Disks (RAID) scheme can be used to allow recovery from a memory failure. RAID 6 can be used to recover data from up to two catastrophic failures. Typically, a hardware encoder is used to generate parities of the RAID 6 protection scheme, and a separate hardware decoder is used in the data recovery process. In an example data storage device described herein, some of the components of the hardware encoder are used to perform the data recovery process, thereby eliminating the need for a separate, additional hardware component.

This application relates to a method, apparatus, and memory for detecting memory failures. The memory failure detection method performs error detection on read data from the memory array to identify failed cells. When repair triggering conditions are met, a repair operation is performed on the failed cell. The success of the repair is verified. If successful, the failed cell is marked as a normal memory cell and continues to be used. If not, redundant cells are used to replace the failed cell. Performing repair operations on failed cells can repair soft-failure cells, avoiding the replacement of a large number of normal cells by redundant cells, thus consuming redundant resources. This allows limited redundant cells to replace unrepairable hard-failure cells, improving the effective utilization rate of redundant cells and preventing redundant resources from being prematurely consumed by repairable soft-failure cells, thus delaying the depletion rate of redundant resources and extending the working life of the memory.

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

The application provides a memory fault area identification method and device, electronic equipment and storage medium. The method comprises the following steps: checking whether the current memory configuration of a system is changed compared with the memory configuration at the last operation; if the current memory configuration is not changed, obtaining a current suspicious memory area list of the system, wherein the current suspicious memory area list records the fault addresses of the current suspicious memory area; and performing shielding processing on the corresponding memory area according to the current suspicious memory area list. By shielding the fault memory area, the use of the fault memory area by the system is isolated, and the reliability of the system is effectively improved.

This invention belongs to the field of computer firmware technology, specifically relating to a method for recording server memory faults. The method of this invention, after a server memory is missing or a memory fault occurs, obtains the server memory fault status by checking logs, thereby quickly locating the problem of the server's inability to boot normally, while minimizing the consumption of BMC system resources.

A chip, a method of controlling memory failure repair, an electronic device, a non-transitory computer-readable storage medium, and a computer program product are provided. The chip comprises a power supply management unit, a repair management unit and a repair execution unit, wherein the power supply management unit is configured to provide a repair starting signal for a first power supply domain in a plurality of power supply domains through a power-on condition of the first power supply domain; the repair management unit is configured to determine first information at least according to a repair starting signal for the first power domain, and the first information comprises information indicating that a memory of the first power domain needs to be subjected to memory fault repair at present; sending a starting signal and first information to a repair execution unit; and the repair execution unit is configured to perform memory fault repair on the memory in the first power domain according to the starting signal and the first information.

The application provides a non-associated grouping memory failure unit analysis method, first, the position information of all memory failure units is obtained through a chip tester to form a fault bit map; then, based on the position information characteristics in the fault bit map, all the failure units in the fault bit map are grouped based on a grouping principle to form a multi-failure group and a single-failure group; then, based on the repair principle of the memory failure unit, the failure units in each group are analyzed for repair to determine whether the failure units of the memory chip can be repaired; if the failure units of the memory chip can be repaired, a repair solution is given. The application divides all the failure units of the memory chip into independent multi-failure groups and single-failure groups based on the non-associated grouping memory failure unit analysis method, and then analyzes and finds the redundancy repair solution of each failure group, which can more reasonably allocate the redundancy resources and effectively improve the repair efficiency of the memory failure units.

Methods and apparatus relating to a memory failure detection mechanism within a die architecture. In some examples, a die package includes decoder logic that receives a plurality of data words, and a first error correction code for each of the data words. The decoder logic generates, for each of the data words, a second error correction code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error state based on the first error correction code and the second error correction code corresponding to each of the data words. The die package also includes error generation logic that receives the error state for the data word from the decoder logic and generates error data based on a combination of the error states for the data word. The error generation logic may store the error data in a memory device.

The present disclosure provides a memory fault processing method, device and equipment and storage medium. The memory fault processing method comprises: obtaining interrupt information, the interrupt information being used to represent that an abnormality occurs in the running process of the terminal device; when the interrupt information is preset interrupt information, determining that the abnormality is a memory fault abnormality; and storing memory fault information into a pre-established abnormality information table. The present disclosure sets a preset interrupt information representing a memory fault abnormality, compares the interrupt information obtained when the terminal device has an abnormality with the preset interrupt information, to quickly determine whether the abnormality type of the terminal device is a memory fault abnormality, thereby saving the time cost of abnormality troubleshooting; and stores the memory fault information corresponding to the memory fault abnormality into the pre-established abnormality information table, so as to facilitate the user to quickly determine the position of the memory fault abnormality by reading the abnormality information table, thereby saving the analysis time cost, and facilitating the user to timely process the memory fault abnormality.

The invention provides a memory fault processing method and device, and is applied to the technical field of computers. The method comprises the following steps: in a system operation stage, if error information exists in a mirror image memory, repairing a fault line corresponding to the error information by adopting a software repairing technology; if the repair of the fault line fails, marking the target memory page corresponding to the fault line as a decommissioning page, so that the target memory page is not subsequently allocated or used any more; and recording a repair request of adopting a hardware repair technology for the target memory page.

The invention discloses a running-state-oriented memory fault risk assessment and adaptive diagnosis method and system, and relates to the technical field of memory running management.The method comprises the steps that S1, running-state memory monitoring data are collected and preprocessed; s2, generating a cross-layer difference triple set, performing difference direction judgment on a cross-layer difference triple, and identifying cross-layer inconsistent fragments; s3, constructing a cross-layer risk index set, performing cross-layer fault risk quantitative analysis on each inconsistent fragment, performing risk grade division based on a quantitative analysis result, and generating a corresponding risk grade label; and S4, carrying out risk response operation on the inconsistent fragments, carrying out response stability evaluation, and generating a final risk response result set. The problem that in the prior art, cross-layer difference sources cannot be accurately recognized in a multi-layer memory access link, so that running state fault risk judgment is prone to being interfered by access jitter and affected by virtualization scheduling offset is solved.

Described are systems and methods for memory failure analysis based on bitline threshold voltage distributions. An example method of implementing a failure type prediction model includes: receiving, by a processing device, a first failure-related dataset reflecting a first bitline threshold voltage distribution associated with a first memory device; determining, based on the first failure-related dataset, a first failure type distribution for the first memory device; creating a training dataset comprising the first failure-related dataset and the first failure type distribution; and training, using the training dataset, a failure type prediction model to determine, for a second memory device, a second failure type distribution based on a second failure-related dataset comprising second bitline threshold voltage data associated with a second memory device.

The invention discloses a memory fault prediction model training method, a memory fault processing method and electronic equipment, and the method comprises the steps: obtaining a first historical memory operation log corresponding to a first server, and a second historical memory operation log corresponding to a second server, obtaining corresponding segmented memory operation logs based on the first historical memory operation log and the second historical memory operation log, obtaining first space error report data and second space error report data corresponding to the segmented memory operation logs, and determining feature set data, and training a preset initial memory fault prediction model based on the feature set data to obtain a trained target memory fault prediction model. And performing fault prediction on the target server based on the trained target memory fault prediction model. Based on the method provided by the invention, the accuracy of server memory fault prediction can be improved.

This specification provides a server memory fault detection method, system, and electronic device, capable of early detection and warning of memory faults, ensuring the stability of server system operation. The method includes: monitoring a target server; when the target server triggers a system interrupt signal, collecting basic error information of the memory units corresponding to the system interrupt signal; parsing the basic error information to determine the corresponding memory unit attribute information stored in an internal database; querying and detecting the data content in the internal database to determine the information frequency of the memory unit attribute information corresponding to multiple memory units within a preset time period; determining whether a memory fault exists in the corresponding memory unit based on the information frequency; and when a memory fault is determined to exist in the memory unit, generating corresponding alarm information based on the memory unit attribute information and reporting it.

This invention discloses a method, apparatus, terminal, and storage medium for handling write-time memory faults, belonging to the field of memory. The method includes: when executing a memory unrepairable fault handling method, determining whether it is a memory synchronization fault; if it is a memory synchronization fault, obtaining the context register information of the interrupted process and obtaining the value of the program counter; determining the address of the interrupted instruction; based on the interrupted instruction address, reading the binary code corresponding to the interrupted instruction and parsing the opcode in the binary code; determining whether the currently interrupted process is in a write operation phase based on the opcode parsing result; if it is in a write operation phase, determining that a write-time memory fault has occurred; when using anonymous mapping, allocating a new physical page frame and replacing the original faulty physical page frame with the new physical page frame; identifying all page table entries involved in the original faulty physical page frame; and replacing the original information in all page table entries with the new physical page frame information.

The application provides a memory fault processing method and device, a storage medium and an electronic device, the method comprising: in response to a memory fault processing instruction, obtaining a heap memory dump file generated by a virtual machine corresponding to the memory fault processing instruction when a memory fault occurs; determining class information of each java class in the heap memory dump file; determining a target java class in each java class according to the class information of each java class; determining a target instance object occupying the most memory and an associated instance object referenced by the target instance object in all instance objects of the target java class; and analyzing the target instance object and the associated instance object to determine fault information having an association relationship with the memory fault. The method provided by the application can quickly and accurately determine factors causing the memory fault.

This application discloses a memory fault handling method and apparatus, relating to the field of computer technology, which solves the problem of system crashes caused by memory faults in the prior art. The specific solution is as follows: a management module obtains memory error information; based on the memory error information, the management module uses a machine learning algorithm to determine the memory fault characteristic pattern or the isolation repair technology used to repair the memory; based on the memory fault characteristic pattern or the isolation repair technology used to repair the memory, the management module determines whether to use at least one of hardware isolation or software isolation to repair the memory.

The embodiment of the application provides a memory fault processing method and computer equipment, and relates to the technical field of memory. In the method, after determining a plurality of fault events of the memory, the plurality of fault events are divided into at least two fault groups according to physical positions of the plurality of fault events, and the influence degree of the fault events in a target fault group on the memory is predicted. Since the influence degree of the target fault group is positively correlated with the repair value of the physical position where the target fault group is located, and the fault influence degree meets a preset condition, the repair value of the physical position where the target fault group is located is higher. Based on this, the physical position where the target fault group located and the influence degree meet the preset condition is determined as a to-be-repaired position, which can ensure that the necessity of repair is higher, and therefore, unnecessary repair operations and problems of wasting storage resources and fault repair resources of the memory can be avoided.

This application provides a server fault diagnosis method, apparatus, electronic device, and storage medium. The method is applied to a BMC (Block Controller). After receiving an interrupt signal from the CPU, the BMC selects a target MCA (Memory Access Control) register. The target MCA register indicates a fault in the CPU or memory and records the fault type and the addresses of the faulty CPU and memory. When a CPU fault is determined based on the data stored in the target MCA register, and the fault type is uncorrectable, the CPU slot information is reported to the monitoring terminal. When a memory fault is determined based on the data stored in the target MCA register, and the fault type is uncorrectable, the identification information of the faulty target memory is determined based on the address recorded in the target MCA register, and the identification information is reported to the monitoring terminal, accurately locating the faulty component. By using the BMC, out-of-band diagnosis and reporting of server faults are achieved, improving server maintainability.

The application discloses a memory bank fault detection device and method, relates to the field of memory fault detection of a computing device, and can timely determine the faulty memory bank when the memory is faulty, and improves the accuracy and timeliness of memory fault detection. The fault detection device comprises a memory management controller and a latch. An input end of the memory management controller is connected with the memory bank, and an output end of the memory management controller is connected with one input end of the latch. The memory management controller is used for detecting correctable errors (CE) of the memory bank and determining the number of the correctable errors (CE) of the memory bank. When the number of the correctable errors (CE) of the memory bank exceeds a preset threshold value, the memory management controller sends a latching signal to the latch.

The utility model relates to industrial automation technical field provides a kind of multifunctional automation monitoring industrial computer, the multifunctional automation monitoring industrial computer includes main controller CPU, FLASH data storage unit and RTC real-time clock unit, wherein, the main controller CPU is electrically connected with FLASH data storage unit and RTC real-time clock unit respectively, the FLASH data storage unit uses double NORFLASH data storage structure, for local double backup storage to acquisition data;The RTC real-time clock unit is used to provide time reference and timestamp record.The utility model has organic integration and electrical connection by main controller CPU and double NORFLASH data storage structure and RTC real-time clock unit, realizes the local synchronous double backup storage and accurate timestamp record of acquisition data, avoids the data loss risk caused by memory failure under single storage mode, and ensures the time traceability of monitoring data, improves the reliability and stability of data storage.

This invention belongs to the field of server testing technology, specifically providing a method, apparatus, and system for detecting server memory slot faults. The method includes the following steps: Powering on the server, configuring the BMC (Browser Control Center) to detect the GPIO status of the memory slots on the motherboard; when the GPIO status is high, determining a memory slot fault and configuring the BMC system event log to display the memory slot status information; during the boot process, configuring the BIOS to obtain memory slot status information from the BMC and, based on the obtained information, masking the faulty memory slots; during self-test, testing the memory in normal memory slots; after self-test completion, displaying the number of detected memory modules and the location information of the masked memory slots on the POST (Power-On Self-Test) interface. This method can accurately detect whether the fault is a memory module or a memory slot fault, enabling users to handle faults more accurately, improving user convenience and enhancing the user experience.

The embodiment of the invention provides a memory fault processing method and device and a substrate management controller, and relates to the field of storage, after an inspection instruction is received, the inspection instruction can be responded, and an identifier of a to-be-detected memory particle contained in the inspection instruction is positioned, so that a target address corresponding to the to-be-detected memory particle is obtained, and the memory fault processing method and device are obtained. The target inspection scene is determined through the target address corresponding to the to-be-detected memory particle, so that the corresponding inspection period is determined according to the target fault sensitivity corresponding to the target inspection scene, the fault is processed after the inspection period is ended, and the inspection period is dynamically set, so that the problem that the fault is damaged due to the fact that the memory does not have the interruption triggering capability can be avoided. The routing inspection period is fixed to detect the situation that the fault may not be processed in time, the fault screening efficiency is improved, and the efficiency of the memory fault processing process is improved.

The disclosure provides a fault processing method and device, electronic equipment and computer readable storage medium, relates to the technical field of data processing, and particularly relates to the technical field of cloud computing, virtual machines, computer hardware faults and the like. The specific implementation scheme is as follows: memory fault information reported by a memory hardware that has occurred a fault is acquired, the memory fault information comprises a fault host computer physical address of the memory hardware that has occurred a fault in a host computer; a user state process corresponding to the fault host computer physical address is determined through reverse mapping according to the fault host computer physical address; in the case that the user state process is a virtual machine simulator process, a fault host computer virtual address corresponding to the fault host computer physical address is acquired according to address information of a virtual memory region; and the fault host computer virtual address is sent to the user state process, so that the user state process instructs a fault virtual machine to run in the host computer according to the fault host computer virtual address.

This application discloses a memory fault management system, method, server, and electronic device, relating to the field of computer technology. It includes a hardware memory processing circuit with a hardware layer and a processor, the processor being further divided into a kernel layer, a user layer, and an input / output layer. Through the collaborative work of the hardware layer and various software layers, it achieves hierarchical detection, classification processing, and automatic isolation of memory error data, effectively preventing server downtime caused by memory fault data. Simultaneously, through the linkage mechanism between kernel mode and user mode, combined with visual display, it enhances the monitorability and maintainability of memory errors, facilitating rapid problem location and repair by maintenance personnel and reducing system maintenance costs.

Embodiments described herein relate to an IMD operating in a backup mode in a manner that mitigates against adverse effects of a memory failure. The IMD includes a NVM that stores backup mode firmware, a RAM that includes multiple separate RAM blocks, a processor, and a counter. The processor executes the backup mode firmware to operate the IMD in accordance with a backup mode in response to detection of a malfunction that when detected should cause the IMD to operate in accordance with the backup mode. While the processor operates the IMD in accordance with the backup mode the processor stores and accesses variables in one of the RAM blocks. The counter is selectively incremented and used to select which one of the RAM blocks the variables are stored within while the processor executes the backup mode firmware to operate the IMD in accordance with the backup mode.