3252results about "Static storage" patented technology

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention relates to the technical field of embedded data storage, and discloses a method and a system for prolonging the service life of a FLASH simulation EEPROM (Electrically Erasable Programmable Read-Only Memory) in a single chip microcomputer, and the method comprises the following steps: firstly, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when data is written, and writing the data into a database; the method comprises the following steps of: starting a backup area or a transaction log area, safely updating a mapping table by using a transaction mechanism, performing cyclic redundancy check when reading data, if the cyclic redundancy check fails, starting cascade recovery from the backup area or the transaction log area, and finally, updating a transaction log to record operation so as to form a closed-loop management process. According to the invention, through a set of dynamic wear leveling and data classification management mechanism, global and uniform distribution of the write load in the storage array is realized, the physical block with the least erasing times is selected during writing, the access frequency of the data can be identified, and cold data which is not changed frequently can be actively migrated.

The invention relates to the technical field of data storage, and discloses a solid state disk total write-in data volume testing method, which comprises the following steps of: initializing a testing environment and self-adaptive parameter configuration of a solid state disk; creating a plurality of parallel data acquisition threads, acquiring test data through the data acquisition threads, and storing the acquired test data into a database; establishing a preset health degree evaluation model, analyzing the collected test data in real time according to a preset health degree index system, dynamically adjusting a test load based on a dynamic acceleration stress model and according to the real-time state of the solid state disk, executing a corresponding test operation according to an adjustment result, and recording a test result; and analyzing the test result, and automatically generating a test report according to the analysis result. According to the method, the dynamic acceleration stress model is introduced, so that the test load is dynamically adjusted according to the real-time state of the SSD, and the test efficiency and accuracy are improved.

The invention discloses a high-density NAND storage medium self-adaptive repairing method which comprises the following steps: a main control chip separates a target feature vector representing the real aging trend of a storage unit from original read data containing random physical noise; the main control chip deduces the target feature vector by using a full-integer recursive prediction model to obtain a health state prediction result of the storage unit in a future preset time period; wherein the health state prediction result comprises an optimal read reference voltage offset and an estimated bit error rate growth curve; and the main control chip adjusts the charge distribution pattern and programming voltage parameters of the data on the storage unit in the data writing stage according to the health state prediction result. By means of the mode, the problems of firmware assembly line blocking and performance jitter caused by floating point operation and huge model parameter loading can be solved under the limited hardware environment that the main control chip only supports integer operation and on-chip cache is extremely small.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

The invention provides a decoder, a decoding method, a memory system, an operation method of the memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in a current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check matrix, the check formula and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to: determine a flipping threshold in a current iteration based on a change state of the checkout weight; and the bit flipping circuit is configured to output the to-be-decoded code word in the next round of iteration based on a comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value in the current iteration determined by the processor.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system, and the manufacturing method of a semiconductor structure comprises the steps: forming a first mask layer on a substrate, and forming a plurality of first openings in the first mask layer side by side; etching the substrate for the first time based on the plurality of first openings to form a plurality of first grooves arranged side by side; expanding the plurality of first openings, wherein the expanded plurality of first openings form a plurality of second openings; filling the plurality of first grooves and the plurality of second openings to form a plurality of filling structures arranged side by side; removing the first mask layer between the adjacent filling structures to form a third opening; and etching the substrate for the second time based on the third opening to form a second groove.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention provides a controller, method and device for verifying stored data and a storage medium. The controller obtains a data writing instruction and a verification writing instruction; in response to the data writing instruction, writing the to-be-written data block into the first memory; in response to the write verification instruction, obtaining a to-be-read data block based on the read address; calculating a read address and a to-be-read data block to obtain a write check code; the to-be-read data block is a part of the to-be-written data block; obtaining a read verification instruction; in response to the read verification instruction, obtaining a read data block from the first memory based on the read address; calculating a read address and a read data block to obtain a read check code; and comparing the write check code with the read check code to obtain a comparison result. According to the technical scheme, whether the read data block is abnormal or not can be checked by calculating the read data block and the read address corresponding to the read data block, and therefore safe operation and performance of the ADAS chip are guaranteed.

The invention discloses a multi-dimensional power consumption test method and device for a solid state disk and a storage medium, and the method comprises the steps: controlling a test environment parameter and the solid state disk to enter a preset initial state in response to a test start instruction; based on a test matrix which predefines a plurality of temperature and capacity occupation combinations, controlling a test device to apply a multi-dimensional dynamic working load to the solid state disk, and synchronously acquiring power consumption data, internal state data and performance data; performing time synchronization and data fusion on the collected multi-source data to form an associated data set; and performing intelligent analysis on the data set, extracting power consumption characteristics of the solid state disk, and generating a power consumption evaluation report based on the power consumption characteristics. According to the method, the problems of single test dimension, incomplete test condition coverage, failure in effective fusion of multi-source data and lack of intelligent analysis in the prior art are solved, and comprehensive, accurate and automatic evaluation of the power consumption of the solid state disk is realized.

The invention discloses a composite stress test method and device for a solid state disk, equipment and a medium, and the method comprises the steps: loading a test configuration parameter, and building communication connection with a to-be-tested solid state disk which is preset in a preset test environment; performing performance baseline calibration and preprocessing on the to-be-tested solid state disk; executing a composite stress performance test, and dynamically coupling at least two of temperature stress, capacity occupation stress, power interruption stress, garbage collection induced stress and mixed load stress; synchronously acquiring test data and constructing a time sequence data warehouse; and performing intelligent deep analysis based on the time sequence data warehouse, wherein the intelligent deep analysis comprises performance consistency deep analysis and health degree and risk prediction analysis. According to the method, a real complex environment is simulated through the composite stress test, the problem that a traditional test method is single in scene is solved, meanwhile, the problem that data analysis is shallow is solved through intelligent deep analysis, and the reliability of the solid state disk can be comprehensively and accurately evaluated.

The invention belongs to the technical field of semiconductor testing, and particularly relates to an HBM-DRAM grouping testing system and method, and the system comprises a main testing controller and a plurality of testing execution units configured in the system. And the main test controller is in communication connection with the plurality of test execution units through a preset test coordination bus. By physically segmenting the test interface into a plurality of independent, low-needle-count probe card modules, challenges of designing and manufacturing a single, huge, ultra-high-needle-count probe card are fundamentally avoided. Therefore, the manufacturing cost, the calibration difficulty and the maintenance cost of each probe card module are greatly reduced, and the overall yield and the service life of the probe card are remarkably improved.

An information handling system may include an information handling resource comprising a circuit board and an insert assembly mechanically coupled to the information handling resource and comprising a base mechanically attached via a press-fit mechanical coupling to an edge of the circuit board and a body mechanically coupled to the base.

The invention discloses an intelligent memory chip high and low temperature test device and a test tuning method, and relates to the technical field of memory chip testing, the device comprises a test unit used for constructing a cold and hot test environment for a to-be-tested memory chip; the power supply unit is used for providing direct current for each unit; the management unit is used for detecting environment data in real time and uploading the environment data to the data acquisition and analysis server, and regulating and controlling the environment data in a closed-loop manner by combining a test instruction; the excitation generator is used for generating and sending test excitation for the to-be-tested storage chip according to the test instruction, recording test data and feeding back the test data to the data acquisition and analysis server; and the data acquisition and analysis server is used for pre-judging faults of the to-be-tested storage chip based on an AI model according to the real-time environment data and the test data, optimizing test instruction parameters or storage chip FTL algorithm parameters, generating a dynamic regulation and control test instruction and issuing the dynamic regulation and control test instruction. According to the invention, accurate test and optimization of the memory chip in an extreme temperature environment can be realized.

The invention provides a power-down continuous test data consistency verification method and device, equipment and a medium. The method comprises the following steps: issuing a query instruction to obtain disk information of a currently connected SSD (Solid State Disk); according to the disk information, judging whether to issue a continuous test request; if a continuous test request is issued, returning a processing result according to the disk information and the continuous test request through a preset processing rule; selecting a continuous test request corresponding to a successful result as a verification request according to the processing result; and performing consistency verification on the disk information according to the verification request. By systematically executing the steps of disk information acquisition, continuous test request decision, request filtering and screening, final consistency comparison and the like, an automatic closed-loop test process is constructed, and the problem that the consistency of SSD power failure continuous test data cannot be verified by various IO tools at present is solved; and consistency verification can be carried out on the successfully written data before and after power failure.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

The invention discloses a high-reliability storage unit fault-tolerant control system, which relates to the technical field of storage unit fault-tolerant control and comprises a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate regulation and control module, a nonlinear charge turn-back channel module and a self-adaptive capacitance balance control module. And the dynamic charge mapping model module is used for constructing a dynamic charge mapping model, extracting a potential transition curve in a high-frequency read-write switching stage by taking a parasitic capacitance real-time response parameter of a parallel bit line in the storage unit as an input variable, and generating a dynamic coupling map for identifying a pseudo-synchronous charge accumulation region based on the potential transition curve. According to the invention, real-time suppression and energy balance of parasitic capacitance are realized through dynamic charge mapping and potential inversion, and potential stability of a bit line is maintained; and energy closed-loop control is realized through nonlinear charge turn-back and self-adaptive capacitance regulation and control, charge regeneration is prevented, so that the stability and the reliability of the storage unit are improved, and the service life of the storage unit is prolonged.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.

The invention discloses a test method and system for dynamic configuration and verification of a GPP of an eMMC memory, and relates to the technical field of embedded memorizers, and the method comprises the following steps: S1, the test system obtains a test parameter set through external input or from a predefined test case library, S2, after the input test set is processed through a dynamic parameterization engine DPCE, the test parameter set is stored in the test case library; the test system analyzes the configuration data to obtain analysis parameters, and to-be-written configuration data is formed; s3, before a configuration command is sent, dynamically constructing an eMMC partition layout model, and executing a conflict detection algorithm; s4, the test system writes the configuration data to be written after conflict detection into the eMMC; s5, adopting a triple persistence verification ring mechanism to form closed-loop verification with configuration taking effect; and S6, outputting a detailed test report by the test system based on the judgment node in the test process. According to the method, the test efficiency is remarkably improved, the test coverage rate and the product quality are enhanced, and more flexible and comprehensive test case design is supported.