5939results about "Static storage" patented technology

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

The invention discloses a disk array fault early warning method and related equipment, and relates to the technical field of computer storage, and the method comprises the steps: responding to a preset period triggering condition, and applying a preset mechanical excitation signal to a target disk array; collecting a vibration response frequency spectrum and an acoustic response waveform of the target disk array under the action of the mechanical excitation signal; performing fusion analysis on the vibration response frequency spectrum and the acoustic response waveform through a preset feature fusion model to obtain a fault probability prediction vector; and determining a real-time fault early warning instruction for the target disk array according to the fault probability prediction vector and a preset health reference vector. Through periodic mechanical excitation and multi-mode signal fusion analysis, high-precision, non-intrusive and real-time fault early warning of the disk array can be realized, the reliability of the disk array is improved, and the operation and maintenance cost is reduced.

The invention relates to the technical field of solid state disk performance evaluation. The solid state disk performance evaluation method comprises the steps of obtaining solid state disk operation information, conducting exception analysis on the solid state disk operation information through a deep learning model to obtain solid state disk exception information, conducting correction and interpolation on the solid state disk exception information, and obtaining the solid state disk performance evaluation result. Performing feature extraction on the corrected operation information to obtain a plurality of performance features of the solid state disk, screening the plurality of performance features based on a feature selection method to obtain a target feature set required by performance evaluation, and analyzing the target feature set required by performance evaluation through a time sequence prediction model. Obtaining performance change trend information under different loads, predicting the residual life and the performance degradation condition of the solid state disk according to the performance change trend information, and obtaining a performance evaluation result. The method has the effect of improving the performance evaluation accuracy of the solid state disk.

The invention discloses an SSD testing method, system, device and equipment and a storage medium, and relates to the technical field of solid state disk testing, and the method comprises the steps that firstly, a test request is responded, and a standardized test environment is constructed by deploying a test environment mirror image; and then an iterative testing process is executed on the SSD to be tested in the environment. The key of the iterative test process is that the real-time performance of the SSD to be tested in each round of test can be obtained, and the performance is compared with a preset performance standard. When a comparison result meets a specific condition, the system automatically adjusts and optimizes execution parameters used in the next round of test. According to the method and the device, the dynamic association between the performance indexes and the subsequent test parameters is established, so that the test process can be self-adjusted according to the actual performance of the SSD to be tested, and the limitation caused by the fact that the test parameters are fixed in the prior art is overcome.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The present invention relates to the technical field of hard disk life prediction, and in particular to a method and system for predicting the life of a solid-state hard disk based on big data. The method comprises the following steps: obtaining solid-state hard disk structure data; performing operation simulation based on the solid-state hard disk structure data, thereby generating solid-state hard disk operation simulation data; using the solid-state hard disk operation simulation data to collect power fluctuation data of flash memory units in the hard disk on the solid-state hard disk structure data, and obtaining power fluctuation data of flash memory units in key areas of the solid-state hard disk; classifying solid-state hard disk operations on the solid-state hard disk operation simulation data, and generating write operations and erase operations. The present invention improves the accuracy of life prediction for solid-state hard disks through multi-dimensional data collection and analysis, combined with factors such as hard disk operation, power fluctuation, electron migration effect, and material fatigue.

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and / or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and / or predefined patterns.

The invention discloses a server actual hard disk physical slot position and hard disk information mapping method and device, and relates to the technical field of hard disk testing, and the method comprises the steps: marking a unique number through a hard disk recognition tool and a visual recognition case slot position under an operating system, highlighting a hard disk in combination with a lighting mechanism, and carrying out the recognition of the unique number through the slot position association after lighting. According to the method and the device, the actual hard disk SN code is established, the mapping relation between the actual hard disk SN code and the visual physical slot position is established, and the unique mapping between the actual hard disk position and the hard disk information is established through the mapping relation between the SN and the actual physical slot position, so that the problems of low efficiency of a hard disk testing technology, easiness in mistaken formatting, mistaken unloading and mistaken plugging after disk letter disorder, and high reliability are solved. According to the technical scheme, the technical problems that a storage path cannot be found in time, and the accuracy and efficiency of hard disk management are seriously affected are solved, and the technical effects that decoupling of the storage path and physical hardware is ensured, the influence of system restart or hardware change on services is reduced, the fault hard disk can be directly positioned through slot position identification, and the fault recovery time is shortened are achieved.

The invention discloses a solid state disk performance fluctuation test method, device and equipment and a storage medium, and relates to the technical field of performance tests.A corresponding test action sequence is generated according to a performance test instruction, a plurality of test actions are organized into a standard test process capable of being repeatedly executed, and the performance fluctuation test efficiency is improved. The influence of the difference of manual test operation execution on the test result is eliminated, the performance fluctuation test result of the to-be-tested solid state disk is calculated based on the storage performance index of the to-be-tested solid state disk in the test action sequence execution process, and objective evaluation of the performance fluctuation of the solid state disk is realized on the basis of sufficient data support. The automation and standardization of the test are realized from the two aspects of the test process and the result evaluation, and the efficiency and accuracy of the test are improved.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

The invention provides a solid state disk testing method and device, equipment and a medium, and relates to the technical field of hard disk detection. The test method comprises the following steps: in a process of writing data into physical areas of a to-be-tested solid state disk according to a physical address in sequence, randomly selecting at least part of areas from the physical areas written with the data at a preset time interval to perform reset operation until the physical areas reach a target area state, the target area state comprises a target filling state and a target fragmentation state; executing a read-write test on the physical region in the target region state to obtain test data; and generating a test report based on the test data.

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

An apparatus for reliable fuse-based storage in an Integrated Circuit (IC) includes a plurality of electronic fuses and processing logic. The electronic fuses store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits. The processing logic receives a read command for reading given data bits from the electronic fuses, based on the read command retrieves access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits, using the access information reads the given data bits and the given parity bits from the given electronic fuses, applies the ECC scheme to the given data bits and the given parity bits, using the ECC module to generate corrected data bits, and outputs the corrected data bits.

This disclosure describes systems on a chip (SOCs) that prevent trim attempts. The SOCs include one-time programmable (OTP) memory and an engine configured to determine if the one-time programmable (OTP) memory has been trimmed; and if the one-time programmable (OTP) memory has been trimmed, to prevent trimming of the OTP memory.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a package substrate and a first processing integrated circuit (IC) chiplet disposed on the package substrate. A second processing IC chiplet is disposed on the package substrate. At least one first row multi-port memory chiplet is disposed on the package substrate and coupled between the first processing IC chiplet and the second IC processing chiplet. Data transfers between the first processing IC chiplet and a destination IC chiplet are routed through the at least one first row multi-port memory chiplet.

The embodiment of the invention provides a hot plug test board, a hot plug test system, a hot plug test method, hot plug test equipment and a medium, and relates to the field of internet big data. The hot plug test board comprises a logic module, a signal switch switching unit and a power supply detection unit, the logic module is connected with the signal switch switching unit and used for transmitting an NVME signal and controlling gating and cutting off of the signal switch switching unit so as to achieve hot removal or hot addition of the NVME hard disk, and the signal switch switching unit responds to control of the logic module and controls the power supply detection unit to detect the power supply of the NVME hard disk. And the NVME signal transmission to the NVME hard disk is gated or cut off, and the power supply detection unit is connected with the NVME hard disk and is used for detecting whether the NVME hard disk is normally powered off or powered on after hot plugging. Through the mode, the NVME hard disk hot plug test can be efficiently and conveniently carried out on the premise of not influencing the overall structure and the hardware and software logic of the original server.

The invention discloses a solid state disk management method and device, equipment, a medium and a product, which are applied to the technical field of storage and are used for solving the problem of data loss caused by difficult realization of timely and accurate solid state disk anomaly detection in the traditional technology, and the method is applied to a distributed storage system deployed with a service layer and a storage layer. The storage layer is deployed with a plurality of object storage devices, each object storage device is deployed with a plurality of solid state disks, and the method comprises the following steps: monitoring a service layer to determine whether the service layer is abnormal or not; if yes, determining an abnormal solid state disk and a solid state disk exception type in a storage layer; the exception type of the solid-state disk comprises exception of the disk and / or expiration of the service life of the disk; when the exception type of the solid state disk is the exception of the solid state disk, performing fault detection on the exceptional solid state disk by utilizing a preset fault detection strategy to obtain a fault detection result; and determining a target protection strategy by using the solid state disk exception type and the fault detection result so as to perform redundancy protection on the exceptional solid state disk.

The invention discloses a memory read-write consistency testing method and system, and relates to the technical field of memory testing. Comprising the steps of S1, performing crosstalk coupling modeling: constructing an interlayer crosstalk coupling transfer function according to a quantum tunneling current curve and a three-dimensional parasitic parameter matrix; s2, constructing a three-dimensional failure probability model: obtaining a plane coupling error distribution diagram, and generating an interlayer crosstalk coefficient matrix according to the interlayer crosstalk coupling transfer function; and S3, identifying electromagnetic coupling hot spot regions: determining a risk level of each region according to the three-dimensional failure probability, setting test parameters according to the risk levels, and performing read-write test on the to-be-tested memory through the test parameters. According to the method, three-dimensional quantitative modeling of cross-layer interference is realized, so that the detection range is expanded from a plane to a three-dimensional structure, and a blind area of interlayer electromagnetic coupling in a traditional method is solved.

The invention discloses a multichannel extended hard disk automatic test device and method. The multichannel extended hard disk automatic test device comprises a control server, a network switch, a test host and a test device, the control server is connected with at least one test host through a network switch, each test host is connected with a test device through a programmable power strip, and the test devices are connected with multiple paths of hard disk equipment; the control server can generate test parameters and issue the test parameters to the test host with the network wakeup function, and the test host can automatically call corresponding test scripts according to the received test parameters, execute test tasks on the hard disk, record the test process and result and upload the test process and result to the control server; the test device can realize automatic switching of a plurality of hard disks of the same test host interface according to the test parameters; and meanwhile, the power supply of the test host is controlled through the programmable power strip so as to generate abnormal power failure test excitation. According to the invention, a single test host can automatically and orderly test a plurality of hard disks in batches.

The invention relates to the technical field of embedded data storage, and discloses a method and a system for prolonging the service life of a FLASH simulation EEPROM (Electrically Erasable Programmable Read-Only Memory) in a single chip microcomputer, and the method comprises the following steps: firstly, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when data is written, and writing the data into a database; the method comprises the following steps of: starting a backup area or a transaction log area, safely updating a mapping table by using a transaction mechanism, performing cyclic redundancy check when reading data, if the cyclic redundancy check fails, starting cascade recovery from the backup area or the transaction log area, and finally, updating a transaction log to record operation so as to form a closed-loop management process. According to the invention, through a set of dynamic wear leveling and data classification management mechanism, global and uniform distribution of the write load in the storage array is realized, the physical block with the least erasing times is selected during writing, the access frequency of the data can be identified, and cold data which is not changed frequently can be actively migrated.

The invention relates to a built-in self-test circuit and a memory. The built-in self-test circuit comprises a storage array, a command / address generation module, a processing module and a repair module. After entering the self-test mode, the command / address generation module generates and sends an internal test command and an internal test address according to a preset test mode. The processing module writes preset data into a storage unit corresponding to the internal test address in the storage array according to the internal test command and a preset test mode, and reads storage data from the storage unit corresponding to the internal test address in the storage array; and generating and outputting a fault mark according to a comparison result of the storage data read each time and the corresponding written preset data. And the repairing module latches the internal test address corresponding to the currently read storage data as an error address according to the fault mark, and repairs the storage unit corresponding to the error address after the self-test mode exits. According to the invention, internal automatic detection and automatic repair can be realized.

The embodiment of the invention provides an early failure test method for flash memory particles, a controller and a storage medium, and the method comprises the steps: placing the flash memory particles in a test space, and adjusting the space temperature of the test space to a first test temperature; performing multiple rounds of testing on the flash memory particles according to different block states, target modes and target read-write behaviors at the first test temperature, and writing test data into a test result; reducing the space temperature from the first test temperature to a second test temperature; performing multiple rounds of testing on the flash memory particles according to different block states, target modes and target read-write behaviors at a second test temperature, and writing test data into a test result; and writing the test result into a bad block table, wherein the bad block table is used for recording the position information, the failure reason and the reliability level of the failure storage block. According to the embodiment of the invention, the blocks with poor performance are screened out by means of multiple rounds of experiments in different scenes, different modes and different read-write behaviors, so that the quality reliability of products is improved.

The invention relates to the technical field of integrated circuit repair, in particular to a storage repair system based on a polymorphic BISR chain, the system divides storage units in a chip into a plurality of repair modules, and a plurality of off-chip registers contained in each repair module form a plurality of first off-chip register chains; when the memory unit in the chip is repaired, the memory unit can be repaired at the same time through the plurality of first off-chip register chains, so that the repair duration of the memory unit of the chip is determined according to the maximum chain length of each first off-chip register chain; compared with the prior art that the repair duration of the chip storage unit is determined according to the sum of the chain lengths of all the off-chip registers, the storage repair time is greatly shortened, the storage repair efficiency is further improved, in the storage repair process, the storage unit can adopt a parallel repair mode or a serial repair mode, and the repair efficiency is improved. Storage repair can be compatible with memory cells of different repair types.

The present application relates to the field of storage technology, and in particular to a method, device, equipment and medium for locating bad data blocks, which are used to accurately and quickly locate damaged data blocks. The method includes: performing independent disk redundant array RAID check on the main storage array to determine the target stripe where the bad block exists; sending the first cyclic redundancy CRC check result of each data block in the target stripe to the second controller in the cluster, so that the second controller obtains the address information of the candidate bad block by comparing the second CRC check result and the first CRC check result of the corresponding data block in the secondary storage array; the secondary storage array is a copy obtained by synchronously writing data with the main storage array; and locating the bad data block in the main storage array according to the received address information.

The invention discloses a performance test method and device of a storage device, an electronic device and a storage medium, and relates to the technical field of data storage, and the performance test method comprises the steps of controlling the storage device to execute data operation in response to test input; wherein the data operation comprises read operation and / or write operation; in the process of executing the data operation by the storage device, obtaining performance data of the storage device through the performance test model; wherein the performance data comprises performance data of a data link of the storage device and performance data of the storage controller, the storage controller is electrically connected with the storage device through the data link, the data link is used for transmitting data between the storage controller and the storage device, and the performance test model comprises at least one performance monitoring tool. The at least one performance monitoring tool is used for performing performance monitoring on the data link and the storage controller; and generating a performance test report of the storage device according to the performance data. The technical effect of improving the performance test efficiency of the storage device can be achieved.

The invention relates to the technical field of storage, in particular to a hard disk testing method, device and equipment and a readable storage medium. The method comprises the steps that mapping information of a hard disk and an access node is acquired; wherein the access node is a node in a non-uniform memory access architecture; determining whether the number of hard disks distributed to the access node is balanced by using the mapping information; if not, adjusting the number of the hard disks allocated to the access node, and returning to obtain the mapping information of the hard disks and the access node again; and if yes, allocating the same number of processors to the hard disk in the access node, and then testing the hard disk based on the non-consistent memory access architecture. According to the invention, after resource balanced allocation is satisfied, hard disk testing is carried out on the non-consistent memory access architecture, so that efficient processing of read-write operation on a processor level can be ensured, detection of individual disks is prevented from being inconsistent with reality, and the accuracy of hard disk testing can be ensured.