8329results about "Static storage" patented technology

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

The invention relates to a state evaluation method and device of a solid state disk, a storage medium and a program product, and belongs to the technical field of storage, and the method comprises the following steps: obtaining related parameter information of the solid state disk, and preprocessing the related parameter information to obtain a first target data feature; according to a joint probability distribution value between the historical merged data features and the health degree, determining a correlation degree between the historical merged data features and the health degree, and according to the correlation degree, screening out a second target data feature from the first target data features; determining a health score corresponding to the second target data feature based on a health score calculation function; and determining a state evaluation result of the solid state disk according to the health score corresponding to the second target data feature, and visually displaying the state evaluation result. According to the method, the accuracy of state evaluation of the solid state disk is improved, and the risk of data loss or server downtime caused by solid state disk faults is effectively reduced.

The invention discloses a solid state disk testing method and system, a storage medium and a program product, and relates to the field of computer storage testing, and the method comprises the following steps: dividing a storage space of a solid state disk to be tested into a plurality of physical areas; determining the number of read-write tests of the to-be-tested solid state disk within a preset duration at a preset temperature; performing read-write test operation on the plurality of physical areas in sequence within a preset duration to obtain read-write error rates respectively corresponding to the plurality of physical areas, the number of read-write times of the read-write test operation being the number of read-write test times; if the read-write error rates corresponding to the physical areas exceeding the preset number are higher than a preset error rate threshold value, determining that the to-be-tested solid state disk is unqualified; and if the read-write error rates corresponding to the physical areas lower than the preset number are lower than a preset error rate threshold, determining that the to-be-tested solid state disk is qualified. By implementing the method, the specific problem area in the solid state disk can be positioned and diagnosed more accurately, so that the quality evaluation standard and the maintenance efficiency of the whole solid state disk are improved.

The invention discloses a disk array fault early warning method and related equipment, and relates to the technical field of computer storage, and the method comprises the steps: responding to a preset period triggering condition, and applying a preset mechanical excitation signal to a target disk array; collecting a vibration response frequency spectrum and an acoustic response waveform of the target disk array under the action of the mechanical excitation signal; performing fusion analysis on the vibration response frequency spectrum and the acoustic response waveform through a preset feature fusion model to obtain a fault probability prediction vector; and determining a real-time fault early warning instruction for the target disk array according to the fault probability prediction vector and a preset health reference vector. Through periodic mechanical excitation and multi-mode signal fusion analysis, high-precision, non-intrusive and real-time fault early warning of the disk array can be realized, the reliability of the disk array is improved, and the operation and maintenance cost is reduced.

The invention relates to the technical field of solid state disk performance evaluation. The solid state disk performance evaluation method comprises the steps of obtaining solid state disk operation information, conducting exception analysis on the solid state disk operation information through a deep learning model to obtain solid state disk exception information, conducting correction and interpolation on the solid state disk exception information, and obtaining the solid state disk performance evaluation result. Performing feature extraction on the corrected operation information to obtain a plurality of performance features of the solid state disk, screening the plurality of performance features based on a feature selection method to obtain a target feature set required by performance evaluation, and analyzing the target feature set required by performance evaluation through a time sequence prediction model. Obtaining performance change trend information under different loads, predicting the residual life and the performance degradation condition of the solid state disk according to the performance change trend information, and obtaining a performance evaluation result. The method has the effect of improving the performance evaluation accuracy of the solid state disk.

The invention discloses an SSD testing method, system, device and equipment and a storage medium, and relates to the technical field of solid state disk testing, and the method comprises the steps that firstly, a test request is responded, and a standardized test environment is constructed by deploying a test environment mirror image; and then an iterative testing process is executed on the SSD to be tested in the environment. The key of the iterative test process is that the real-time performance of the SSD to be tested in each round of test can be obtained, and the performance is compared with a preset performance standard. When a comparison result meets a specific condition, the system automatically adjusts and optimizes execution parameters used in the next round of test. According to the method and the device, the dynamic association between the performance indexes and the subsequent test parameters is established, so that the test process can be self-adjusted according to the actual performance of the SSD to be tested, and the limitation caused by the fact that the test parameters are fixed in the prior art is overcome.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The present invention relates to the technical field of hard disk life prediction, and in particular to a method and system for predicting the life of a solid-state hard disk based on big data. The method comprises the following steps: obtaining solid-state hard disk structure data; performing operation simulation based on the solid-state hard disk structure data, thereby generating solid-state hard disk operation simulation data; using the solid-state hard disk operation simulation data to collect power fluctuation data of flash memory units in the hard disk on the solid-state hard disk structure data, and obtaining power fluctuation data of flash memory units in key areas of the solid-state hard disk; classifying solid-state hard disk operations on the solid-state hard disk operation simulation data, and generating write operations and erase operations. The present invention improves the accuracy of life prediction for solid-state hard disks through multi-dimensional data collection and analysis, combined with factors such as hard disk operation, power fluctuation, electron migration effect, and material fatigue.

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and / or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and / or predefined patterns.

The embodiment of the invention discloses a flash memory testing method and device, a storage medium and computer equipment. The method comprises the following steps: acquiring error bit numbers corresponding to a plurality of flash memory particles and offset data of read voltage through a storage controller, acquiring a normalized value of the error bit number and a normalized value of the offset data of each flash memory particle through a processor, and acquiring weight values of the error bit numbers and the offset data, and obtaining an evaluation value of each flash memory particle according to the normalized value of the error bit number, the normalized value of the offset data and the weight value, and obtaining a test result of the plurality of flash memory particles according to the evaluation value of each flash memory particle. According to the scheme provided by the embodiment of the invention, the normalized weighted average can be carried out on the error bit number of the flash memory particles and the offset data of the read voltage, so that the corresponding evaluation value is calculated, classification is carried out based on the score, and the accuracy of flash memory particle division is improved.

The invention discloses a server actual hard disk physical slot position and hard disk information mapping method and device, and relates to the technical field of hard disk testing, and the method comprises the steps: marking a unique number through a hard disk recognition tool and a visual recognition case slot position under an operating system, highlighting a hard disk in combination with a lighting mechanism, and carrying out the recognition of the unique number through the slot position association after lighting. According to the method and the device, the actual hard disk SN code is established, the mapping relation between the actual hard disk SN code and the visual physical slot position is established, and the unique mapping between the actual hard disk position and the hard disk information is established through the mapping relation between the SN and the actual physical slot position, so that the problems of low efficiency of a hard disk testing technology, easiness in mistaken formatting, mistaken unloading and mistaken plugging after disk letter disorder, and high reliability are solved. According to the technical scheme, the technical problems that a storage path cannot be found in time, and the accuracy and efficiency of hard disk management are seriously affected are solved, and the technical effects that decoupling of the storage path and physical hardware is ensured, the influence of system restart or hardware change on services is reduced, the fault hard disk can be directly positioned through slot position identification, and the fault recovery time is shortened are achieved.

The invention relates to a power consumption and energy efficiency testing method for a solid state disk, a storage medium and a program product. The method comprises the steps that under the condition that the solid state disk meets a first test condition, aiming at each test state in multiple test states of the solid state disk, power consumption parameters of the solid state disk are collected at multiple collection moments, and power consumption test results of the solid state disk in the test states are obtained; for each energy efficiency index in a plurality of energy efficiency indexes of the solid state disk, under the condition that the solid state disk meets a test state corresponding to the energy efficiency index, values of the energy efficiency indexes are respectively collected at a plurality of sampling moments, and index values of the energy efficiency indexes at the plurality of sampling moments are integrated; obtaining an energy efficiency test result of the solid state disk under the energy efficiency index; and obtaining a power consumption and energy efficiency test result of the solid state disk based on the power consumption test result and the energy efficiency test result. By adopting the method, comprehensive and accurate testing of power consumption and energy efficiency of various types of solid state disks in a complex scene can be realized.

The invention discloses a solid state disk performance fluctuation test method, device and equipment and a storage medium, and relates to the technical field of performance tests.A corresponding test action sequence is generated according to a performance test instruction, a plurality of test actions are organized into a standard test process capable of being repeatedly executed, and the performance fluctuation test efficiency is improved. The influence of the difference of manual test operation execution on the test result is eliminated, the performance fluctuation test result of the to-be-tested solid state disk is calculated based on the storage performance index of the to-be-tested solid state disk in the test action sequence execution process, and objective evaluation of the performance fluctuation of the solid state disk is realized on the basis of sufficient data support. The automation and standardization of the test are realized from the two aspects of the test process and the result evaluation, and the efficiency and accuracy of the test are improved.

The embodiment of the invention discloses a phase adjustment circuit and method and a memory. The phase adjustment circuit includes: a multi-phase clock signal generator configured to generate an initial multi-phase clock signal, a phase error detector configured to detect a phase error of the initial multi-phase clock signal, and a phase error canceller configured to cancel a phase error of the initial multi-phase clock signal; the phase error detector is connected with the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signals to obtain error signals used for representing phase difference information among the initial multi-phase clock signals; the phase error eliminator is connected with the phase error detector and is configured to detect the error signal to obtain an error elimination code; and the multi-phase clock signal generator is also connected with the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

The invention provides a solid state disk testing method and device, equipment and a medium, and relates to the technical field of hard disk detection. The test method comprises the following steps: in a process of writing data into physical areas of a to-be-tested solid state disk according to a physical address in sequence, randomly selecting at least part of areas from the physical areas written with the data at a preset time interval to perform reset operation until the physical areas reach a target area state, the target area state comprises a target filling state and a target fragmentation state; executing a read-write test on the physical region in the target region state to obtain test data; and generating a test report based on the test data.

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

The invention relates to a processing method and device for a test data file and a readable storage medium, and the method comprises the steps: analyzing the test data file, and obtaining an analyzed file; determining whether the analysis file is complete or not; under the condition that the analysis file is incomplete, obtaining corresponding statistical information based on the test data record in the analysis file, and supplementing the statistical information into the analysis file to obtain a repair file; and outputting a test result corresponding to the test data record on the basis of the repair file, thereby solving the problem that the test data generated under the condition of abnormal chip test cannot be utilized in the prior art.

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

An apparatus for reliable fuse-based storage in an Integrated Circuit (IC) includes a plurality of electronic fuses and processing logic. The electronic fuses store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits. The processing logic receives a read command for reading given data bits from the electronic fuses, based on the read command retrieves access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits, using the access information reads the given data bits and the given parity bits from the given electronic fuses, applies the ECC scheme to the given data bits and the given parity bits, using the ECC module to generate corrected data bits, and outputs the corrected data bits.

The invention provides a memory fault processing method and device, electronic equipment and a readable storage medium, and in the method, the electronic equipment can determine a first storage unit with a fault and isolate the first storage unit. The electronic equipment can carry out pressure measurement on the first storage unit to obtain the fault level of the first storage unit, the electronic equipment executes corresponding operation on the first storage unit according to the fault level of the first storage unit, and when the fault level of the first storage unit indicates that the first storage unit is in a first risk level, the first storage unit is in a second risk level. The operations include de-isolating the first memory cell. According to the method and the device, after the faulted storage unit is isolated, the voltage of the storage unit can be measured, and the real fault level of the storage unit is obtained. Wherein when the fault level of the first storage unit is the first risk level, the electronic equipment can remove isolation of the first storage unit, the first storage unit can be continuously used, and the number of available storage units can be increased.

The invention discloses a storage chip energy consumption test method and device based on multi-objective optimization. The method comprises the following steps: S1, initializing a test environment; s2, setting a multi-objective optimization model and a fuzzy logic system; s3, constructing an initial test data set; s4, calculating the membership degree of each test target; s5, generating a group of initial optimization parameter combinations; s6, dynamically adjusting the test parameters on the basis of the initial optimization parameter combination; s7, generating an optimized test parameter combination; s8, repeating the steps S6 and S7 until a preset optimization convergence condition is reached, and generating a final test parameter combination; s9, obtaining final test result data; and S10, analyzing the final test result data, comprehensively evaluating the performance of each test target through a fuzzy logic system, and generating a multi-target optimization test report of the storage chip. According to the method, the problems of multi-target test balance, test process optimization and balance between efficiency and accuracy in the prior art are effectively solved.

This disclosure describes systems on a chip (SOCs) that prevent trim attempts. The SOCs include one-time programmable (OTP) memory and an engine configured to determine if the one-time programmable (OTP) memory has been trimmed; and if the one-time programmable (OTP) memory has been trimmed, to prevent trimming of the OTP memory.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a package substrate and a first processing integrated circuit (IC) chiplet disposed on the package substrate. A second processing IC chiplet is disposed on the package substrate. At least one first row multi-port memory chiplet is disposed on the package substrate and coupled between the first processing IC chiplet and the second IC processing chiplet. Data transfers between the first processing IC chiplet and a destination IC chiplet are routed through the at least one first row multi-port memory chiplet.