2410 results about "Probe card" patented technology

Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly thereto (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are "stacked up" so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed. The interposer has resilient contact structures extending from both the top and bottom surfaces thereof, and ensures that electrical connections are maintained between the space transformer and the probe card throughout the space transformer's range of adjustment, by virtue of the interposer's inherent compliance. Multiple die sites on a semiconductor wafer are readily probed using the disclosed techniques, and the probe elements can be arranged to optimize probing of an entire wafer. Composite interconnection elements having a relatively soft core overcoated by a relatively hard shell, as the resilient contact structures are described.

The present invention discloses a method and system compensating for thermally induced motion of probe cards used in testing die on a wafer. A probe card incorporating temperature control devices to maintain a uniform temperature throughout the thickness of the probe card is disclosed. A probe card incorporating bi-material stiffening elements which respond to changes in temperature in such a way as to counteract thermally induced motion of the probe card is disclosed including rolling elements, slots and lubrication. Various means for allowing radial expansion of a probe card to prevent thermally induced motion of the probe card are also disclosed. A method for detecting thermally induced movement of the probe card and moving the wafer to compensate is also disclosed.

In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Interconnection elements for electronic components, exhibiting desirable mechanical characteristic (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart to desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and / or solderability) may be applied to the composite interconnection element. The resulting interconnection elements may be mounted to a variety of electronic components, including directly to semiconductor dies and wafers (in which case the overcoat material anchors the composite interconnection element to a terminal (or the like) on the electronic component), may be mounted to support substrates for use as interposers and may be mounted to substrates for use as probe cards or probe card inserts. The shaping tool may be an anvil (622) and a die (624), and may nick or sever successive shaped portions of the elongate elements, and the elongate element may be of an inherently hard (springy) material. Methods of fabricating interconnection elements on sacrificial substrates are described. Methods of fabricating tip structures (258) and contact tips at the end of interconnection elements are also described.

The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

A probe card cooling assembly for use in a test system includes a package with one or more dies cooled by direct cooling. The cooled package includes one or more dies with active electronic components and at least one coolant port that allows a coolant to enter the high-density package and directly cool the active electronic components of the dies during a testing operation.

A needle fixture of a probe card and a needle fixing method in semiconductor inspection equipment include a needle fixture of a probe card in semiconductor inspection equipment including a printed circuit board; a needle fixture installed in the printed circuit board; a resin unit affixing a probe needle to the needle fixture using an adhesive; and a separation preventer for preventing separation of the resin unit from the needle fixture, wherein the separation preventer includes: a plurality of notches formed along a bottom surface of the needle fixture; and the adhesive filling the plurality of notches.

A probe card for testing semiconductor devices includes a main board member, an upper reinforcing plate, a lower reinforcing plate, an interface member, a sub board member, a needle guide member, a needle member, a side cover member, and a clamping member. The probe card achieves an interface between the circuit boards through elastic connection pins so as to cope with a connection shock with the connection terminals of a semiconductor device, thereby preventing damages on the boards, and has the component parts combined together simply by face contacts to facilitate assembly and disassembly of the component parts and thereby to provide a great economical advantage in the aspect of maintenance and repair.

A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads. The tester channel measures the voltage of its input signal so that the logic state of the signals produced at each of the N IC output pads can be determined from the measured voltage.

Disclosed is a probing method comprising steps of moving a main chuck to align an object of inspection on the main chuck with probes of a probe card located over the main chuck, moving the main chuck toward the probe card, thereby bringing electrodes of the object of inspection into contact with the probes, overdriving the main chuck toward the probe card while measuring a load applied to the object of inspection by contact with the probes and controlling the movement of the main chuck in accordance with the measured load, and inspecting the electrical properties of the object of inspection by means of the probes.

A zero-point detecting method of this invention is performed prior to testing the electrical characteristics of a wafer by bringing an object to be tested on a stage and probes of a probe card into contact with each other. The surface of a zero-point detection plate is made of a conductive material (e.g., copper). The zero-point detection plate is used to detect a zero point as a position where the surface of the object to be tested comes into contact with the probe pins.

Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and / or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a stiffening structure and a compliant carrier structure, such as a decal or screen, which is fixedly attached to the probe chip substrate.

A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs, even during the test process (2) to generate test vector signals to provide to the ICs, and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.

A method of testing a probe card includes the step of positioning the probe card in a prober over a verification wafer that is placed on a stage. The probe card is brought in contact with a contact region on the verification wafer. The verification wafer includes a shorting plane surrounding the contact region. A test signal is sent through the verification wafer to the probe card. A response signal from the probe card is received and analyzed.

The present invention relates to a probe stylus 1 for an inspection of semiconductor device in a state of wafer. When a large number of pad 5 are disposed in a semiconductor device, setting of the probe styluses 1 onto a probe card, on which a semiconductor to be inspected shall be mounted, is difficult. An objet of the present invention is to improve the form of the probe stylus to solve this problem.The object is attained by a probe stylus according to the present invention. The probe stylus 1 is comprised of a first electrically conductive member 2, a second electrically conductive member 3, and an insulating member 4 disposed between the first and second electrically conductive members 2,3, wherein the first and second electrically conductive members 2,3 have a form of a needle and they form a single needle. In an embodiment, the first and second electrically conductive members have a half round cross section. In another embodiment, each of the first and second electrically conductive members has a resilient portion at their tip portion. In another embodiment, the first electrically conductive member is covered with the insulating member, and the insulating member is covered with the second electrically conductive member. In further another embodiment, a slit is disposed between the first and second electrically conductive members.

An improved interconnection system is described, such as for electrical contactors and connectors, electronic device or module package assemblies, socket assemblies, and / or probe card assembly systems. An exemplary connector comprises a first connector structure comprising a contactor substrate having a contact surface and a bonding surface, and one or more electrically conductive micro-fabricated spring contacts extending from the probe surface, a second connector structure comprising at least one substrate and having a set of at least one electrically conductive contact pad located on a connector surface and corresponding to the set of spring contacts, and means for movably positioning and aligning the first connector structure and the second connector structure between at least a first position and a second position, such that in at least one position, at least one electrically conductive micro-fabricated spring contact is electrically connected to at least one electrically conductive contact pad.

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

In a probe card for testing a plurality of semiconductor integrated circuits formed on a semiconductor wafer in a lump, only a faulty probe can be repaired without removing all probes from a wiring board. The probe card comprises a plurality of probes to be connected to respective testing electrodes formed on the semiconductor wafer, and wiring means provided with pads to be jointed to the probes, wherein the pads is formed on the upper surface of the wiring board.

A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one or more peripheral edges where the conductor ends are disposed at a side surface of the dielectric material. Stacks of such semiconductor dice, wherein one of the dice is configured with discrete conductive elements projecting from the active surface, and the exposed ends of the dice in the stack are connected with vertical interconnects. A probe card is disclosed having bond wires extending from more central contacts between more peripheral contacts to the edge of the probe card. A probe card having an upper layer bearing contacts and at least one window therethrough, a lower layer bearing conductive traces with ends exposed through the at least one window, and conductors extending from at least some of the contacts to conductive trace ends is also provided. Methods of making the foregoing structures are disclosed.

A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC now with a known delay to connect to a device being tested.

A conventional probe card is very complex in a support structure of probe terminals and it has been difficult to change an array of the probe terminals correspondingly to various arrays of electrode pads of an object to be checked. A contactor (1) of the present invention simultaneously sets its probe terminals in contact with a plurality of electrode pads of an object to be checked and electrical checking of the object is made once or a plurality of times. It has a plurality of first electrodes (3) arranged on a first substrate (silicon substrate) (2) and probe terminals (4) respectively provided on these electrodes (3). The probe terminal (4) has a conductive support (7) provided on the first electrode, elastic support plate (8) whose one end is fixed to the upper end of the conductive support column (7), and probe terminal (bump) 9 fixed to the free end portion of the elastic support plate (8).

A needle assembly of probe card includes a plate and needles formed therein for enhancing an assembly characteristic and productivity and increasing an exact and reliable characteristic test. The plate is provided with holes that are formed with an insulating film on an inner side surface thereof. One side end surface of the needle adheres on an inner side surface of the hole, another side end surface thereof is spaced from an inner side surface of the hole, and a vertical thickness of the other side of the hole is formed thinner than the plate so as to have a space in which the other side can vertically move upwardly and downwardly. The plate and the needle are integrated.

A back-side imaging infrared microscope is integrated with a novel integrated-circuit probe station. The microscope is located below the silicon substrate of the integrated circuit, on the side opposite to the probe card. The electronic circuitry located on the top side of the substrate is imaged through the back side of the substrate and through a window sized to provide a view of a single integrated circuit and of the corresponding probe tips overlying the contact pads. Since the silicon substrate of integrated circuits is transparent to infrared wavelengths, the alignment between probe tips and contact pads is carried out with a clear view of both from the bottom of the substrate. Furthermore, emission images from the integrated circuit are taken during testing with the same microscope after electrical contact has been established.

Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.

A probe apparatus includes a mounting member on which an object to be inspected is mounted and a temperature thereof is being adjusted, a probe card arranged opposite to the mounting member, a driving mechanism which changes a relative positional relationship between the mounting member and the probe card, and a sensor which detects the distance between the sensor and the probe card. By way of detecting the height of the deformed probe card through the use of the sensor and revising the elevation distance of the mounting member, the electrode pads of the wafer W and the probe pins can electrically contact each other with a stable pin pressure, providing high inspection reliability and an increase in throughput.

A floating interface assembly provides signal paths between an integrated circuit (IC) test head and contact pads on a load board or probe card accessing an IC to be tested. Pogo pins or other contactors for contacting the contact pads are mounted on the interface assembly and linked to the test head by flexible conductors. The interface assembly is attached to the test head by springs to allow it the freedom to rotate to some extent about any axis. As the test head approaches the contact pads, alignment pins engage and orient the interface assembly so that its contactors will mate with the contact pads. As the contactors come into contact with the contact pads, the interface assembly adjusts the plane of the contactors so as to evenly distribute contact pressure over all contactor pads.