24 results about "Ic testing" patented technology

The invention discloses a simulation IC test method and system based on load transient response, and aims to improve the performance evaluation precision of a simulation IC under a complex load condition. The method comprises the following steps: firstly, acquiring transient response waveforms and response delay characteristics of an analog IC (Integrated Circuit) in various load jump modes, and constructing a mapping matrix between a load current step change rate and response delay time; in the real-time test, response delay time in a future preset time period is predicted according to the step change rate of the current load current. When the steady-state time window exists, a fixed sampling time sequence is set based on the window to generate a first test waveform; and if the steady-state window does not exist, correcting the transient waveform, and generating a compensated second test waveform. And then time sequence decomposition is carried out on the test waveform, and a load transient stability evaluation matrix is constructed, so that the dynamic performance of the simulation IC is accurately evaluated, and a detailed performance test report is output.

The utility model relates to the technical field of IC (integrated circuit) testing, and discloses a Burn in board Socket cleaning device, which is characterized in that a first ultrasonic cleaning pool, a second ultrasonic cleaning pool, a third ultrasonic cleaning pool and an oven are sequentially arranged, and a carrying arm is arranged to carry a Burn in board, so that the cleaning efficiency is high, manual participation is not needed, time and labor are saved, and the production efficiency is improved. And great convenience is brought to production and maintenance.

The present invention discloses an integrated sample rod processing device for superconducting wire Ic testing and its use method. The integrated processing device includes an operating table primarily constructed from a support frame and a panel. The panel is divided from left to right into a drying area, a storage area, and a welding area, according to the sample rod loading process. A drying actuator, a storage mechanism, a welding actuator, and a control mechanism are mounted on the operating table corresponding to each area. Through this integrated processing device, the present invention not only improves the efficiency of sample rod loading and the automation level of the sample rod drying, storage, and welding process during low-temperature superconducting wire testing, but also improves the working environment of each sample rod loading step, ensuring the health of test personnel. It also prevents sample rod contamination that could affect test precision and accuracy, thereby advancing the development of equipment for superconducting wire production.

The application discloses a wrong-leader-preventing distribution device and relates to the technical field of IC testing. The bundling table of the wrong-leader-preventing distribution device is provided with a bundling groove matched with the bundling magic tape profile, a plurality of first storage cavities are formed by being separated from a first storage cavity, each first opening corresponds to a first door plate, and the first door plate selectively closes the corresponding first opening. The bundling table with the bundling groove is additionally arranged on the workbench to avoid the risks of tray explosion, IC loss and IC crushing caused by bundling the tray loaded with IC products. In addition, the first door plate selectively closes the corresponding first opening, and the selective closing of the different first storage cavities avoids the risk of IC mixing caused by the human wrong taking of the corresponding bundling magic tape. Moreover, the opening control signal of the first door plate is suitable for being associated with the control of a handler tray signal, company ERP customer test information and the like, thereby facilitating the linkage with the above-mentioned external equipment, effectively improving the adaptability and production efficiency.

The invention discloses a test socket for integrated circuit (IC) wafer testing. The test socket comprises an insulating supporting structure with a plurality of through holes and a plurality of elastic conductive columns. The resilient conductive posts are partially embedded in the support structure and pass through the vias to accommodate variations due to IC package warpage and BGA solder ball dimensional tolerances. The insulation supporting structure further comprises a groove located near the through hole, and the elastic conductive column can be safely fixed. The elastic conductive column has an elastic structure, and the surface of the elastic conductive column is at least partially covered by an insulating material layer to prevent short circuit. The test socket is also provided with a hard support frame which can be made of polyimide, PCB (printed circuit board) materials or ceramics, and a soft support frame made of silica gel, so that the test socket is durable and flexible. The invention also relates to a method for manufacturing the test socket, and the method comprises a series of steps for manufacturing the insulating supporting structure, the elastic conductive columns and removing the sacrificial layer, so that the test socket for reliable IC testing is completed.

This invention relates to an automated integrated circuit (IC) system and apparatus for testing the entire IC. The automated IC system includes an acquisition unit for acquiring IC test data, and further includes: a central controller that communicates with the acquisition unit and receives IC test data sent by the acquisition unit through a receiving module therein; and a transmission module that communicates with the receiving module to transmit the IC test data to a comparison module and to a database for storage. Simultaneously, the comparison module retrieves pre-stored data from a memory and compares the IC test data with the pre-stored data. The comparison result is analyzed and judged by an analysis and judgment module. This testing system has high completeness, greatly improving the rigor of IC testing, effectively avoiding errors in the testing process, and ensuring testing effectiveness.

The invention provides an IC tray plane warping detection platform applied to IC detection equipment, which enables the detection to be efficient, is high in detection precision, and ensures that the quality control is stable and reliable. The machine table comprises a machine table large plate; the transmission mechanism comprises a front end detection conveying part, a rear end transfer conveying part and a lifting mechanism; a detection platform mechanism; and a blocking positioning mechanism. A front end detection conveying part of the transmission mechanism is arranged in a front cavity area of the machine table large plate, a pair of vertical stand columns B are arranged on the outer portions of the two sides, corresponding to the front end detection conveying part, of the machine table large plate, and the two ends, in the length direction, of a transverse connecting frame of the blocking and positioning mechanism are fixedly connected to the stand columns B respectively. An air cylinder adjusting plate is fixedly arranged on the transverse connecting frame, the air cylinder adjusting plate is arranged perpendicular to the transverse connecting frame, and the two ends of the air cylinder adjusting plate in the length direction are respectively provided with a material blocking assembly which is arranged downwards.

The present invention discloses a method and system for locating anomalies in analog IC tests based on parallel asynchronous testing, aiming to improve the efficiency and accuracy of locating abnormal channels during complex analog IC testing. This method first obtains data throughput information for the multi-channel analog-to-digital converter (ADC) of the analog IC during testing and, based on this information, formulates a parallel asynchronous testing plan. Subsequently, the transmission data of each ADC channel during testing is collected to construct a channel response characteristic matrix, and the timing drift parameters of each channel are calculated. A spectral clustering algorithm is used to cluster the timing drift parameters and identify clusters of abnormal drift channels. Finally, the clustering results are used to accurately locate the abnormal channels during testing. This method, with its high parallelism and adaptability, is suitable for rapid testing and anomaly analysis of large-scale analog ICs, offering significant advantages in improving test efficiency and reducing testing costs.

The utility model provides a test socket used for IC test. The test socket for IC testing includes: a housing; the device comprises a shell and two movable openings, the two movable openings are formed in the two sides of the shell, a butt joint base is installed at the bottom of the inner wall of the shell, a connector is installed on the back face of the butt joint base, sliding rods are fixedly connected to the positions, close to the four corners, of the bottom of the inner wall of the shell through supporting discs, and auxiliary springs are fixedly connected to the outer surfaces of the supporting discs. And movable rings are slidably connected to the outer surfaces of the sliding rods correspondingly, sliding blocks are installed at the tops of the four movable rings correspondingly, a movable plate is fixedly connected between the four sliding blocks, and supporting plates are fixedly connected to the two sides of the movable plate correspondingly. According to the test socket for the IC test provided by the utility model, the IC integrated circuit is clamped into the test socket through the design, so that the test socket is powered off, and the condition that the IC integrated circuit is damaged due to improper operation when the IC integrated circuit is clamped into the test socket in an electrified manner is avoided.

The present application relates to a control method for a test device and a chip test system. The method is applied to a second controller in a test resource board. The test resource board further includes a first controller and a third controller. The second controller and the third controller are connected to the test device. The method includes: receiving instruction data sent by the first controller; based on the instruction data, obtaining a corresponding operation type and a control mode, where the control mode includes any one of a direct control mode, a preloading mode, and a micro-instruction mode; based on the control mode, obtaining control information corresponding to the instruction data; sending the control information to a corresponding test device, or sending the control information to a corresponding test device through the third controller. The test device performs corresponding control actions based on the control information, solving the problem that the test device control method cannot meet the requirements of different test scenarios for IC testing.

The application belongs to the technical field of chip testing, and discloses an IC adjacent pin short circuit and gold finger contact detection system and method. The IC testing system is used for generating control instructions and measurement instructions, and the control instructions and the measurement instructions are respectively sent to a control module and a measurement module. The control module is used for receiving the control instructions generated by the IC testing system, and sending the control instructions to a to-be-tested IC chip through a control interface of a DUT board, so that the to-be-tested IC chip works according to the control instructions. The measurement module is used for receiving the measurement instructions generated by the IC testing system, and measuring the to-be-tested IC chip through a measurement interface of the DUT board to obtain measurement data, and feeding back the measurement data to the IC testing system to generate a test result. According to the control module and the measurement module, the test parameters can be accurately controlled, the measurement data of the chip can be accurately measured, and a more accurate test result can be obtained.

The utility model belongs to the technical field of IC carrying, and particularly discloses an IC carrying shuttle device. The IC carrier comprises the shell, the carrying assembly is arranged in the shell, the carrying assembly comprises the first IC carrier plate and the second IC carrier plate, the two motors are arranged on one side of the shell, the first IC carrier plate and the second IC carrier plate can be carried at the same time through the carrying assembly, the effect of carrying the double-layer IC carrier plates is achieved, it means that the number of ICs capable of being carried at the same time is doubled, and the carrying efficiency is improved. The carrying efficiency is greatly improved, the overall production cycle is effectively shortened, the high-efficiency requirement of large-scale integrated circuit production is met, the first IC carrier plate and the second IC carrier plate can accurately carry ICs to designated positions through stable movement and track limitation, the accuracy of subsequent IC testing, processing and other links is improved, and the production efficiency is improved. The defective rate caused by carrying errors is reduced, and the product quality and the production reliability are improved.

The invention discloses a simulation IC test abnormity positioning method and system based on parallel asynchronous test, and aims to improve the positioning efficiency and accuracy of an abnormal channel in a complex simulation IC test. The method comprises the following steps: firstly, acquiring data throughput capacity information of a multi-channel analog-to-digital converter (ADC) in a test process of an analog IC, and formulating a parallel asynchronous test scheme by combining the information; then, transmission data of each ADC channel in the test process is collected, a channel response characteristic matrix is constructed, and time sequence drift parameters of each channel are calculated; and clustering the time sequence drift parameters by using a spectral clustering algorithm, and identifying an abnormal drift channel cluster. And finally, accurately positioning an abnormal channel in the test according to a clustering result. The method has high parallelism and self-adaptive capability, is suitable for rapid test and anomaly analysis of a large-scale analog IC, and has remarkable advantages in the aspects of improving test efficiency and reducing test cost.

The invention discloses an automatic digital IC testing and performance evaluation method based on a digital testing platform, and relates to the technical field of IC testing, and the method comprises the steps: carrying out the instrumentation of a tested vehicle-mounted IC through a digital testing platform, simulating the real working condition of a vehicle, obtaining the reference performance, and connecting a load throwing simulator, a sensor network and the to-be-tested IC; acquiring vehicle-mounted voltage, temperature and CAN message load in real time, identifying a load throwing state, and monitoring a vehicle state in real time to obtain a vehicle state value; measuring IC execution delay, power consumption and error rate, and calculating a performance state value; setting a complexity regulation and control algorithm, and dynamically and adaptively adjusting the complexity step length of the algorithm according to the performance sensitivity and the vehicle state; fitting a trend surface, identifying critical complexity, and setting a complexity prediction model to output optimal test complexity. According to the method, the problems of low efficiency and high risk of fixed step length or manual parameter adjustment caused by relatively large influence of algorithm complexity on IC performance change in a vehicle IC test process are solved.

The invention discloses a test socket for integrated circuit (IC) testing. The test socket comprises an insulating support structure with a plurality of through holes and a plurality of elastic conductive columns, the conductive pillar portions are embedded in the support structure and pass through the vias to accommodate variations due to IC package warpage and BGA solder ball dimensional tolerances. The insulation supporting structure further comprises a groove located near the through hole, so that the compressibility and the heat dissipation capability of the test socket can be improved. The conductive post itself has an elastic structure, the surface of which is at least partially covered by an insulating material layer to prevent short circuit. The test socket also has a hard support frame, which may be made of polyimide, PCB material or ceramic, and a soft support frame made of silica gel, which is durable and flexible. The invention also relates to a method for manufacturing the test socket, and the method comprises a series of steps for manufacturing the insulating supporting structure, the conductive columns and removing the sacrificial layer, so that the test socket for reliable IC testing is completed.

The invention discloses a suction nozzle cleaning mechanism and IC test equipment. The suction nozzle cleaning mechanism is arranged in the moving range of the suction nozzle mechanism of the equipment and can clean an adsorption opening of the suction nozzle mechanism in time on the basis that the equipment performance and the carrying and adsorption performance of the suction nozzle mechanism are not affected, dust accumulation at the adsorption opening of the suction nozzle mechanism can be avoided, the carrying performance of the suction nozzle mechanism can be effectively guaranteed, and the service life of the suction nozzle mechanism is prolonged. The suction nozzle mechanism ensures that the IC to-be-carried part does not fall off in the carrying process, so that the IC to-be-carried part is prevented from being damaged due to falling off, the working efficiency can be ensured, equipment where the suction nozzle mechanism is located basically has zero interruption and zero abnormity during operation, and the productivity is improved. The suction nozzle cleaning mechanism is easy and convenient to install and flexible to use, and can be applied to various tool equipment with suction nozzle mechanisms, such as IC testing equipment. The suction nozzle cleaning mechanism is additionally arranged to clean an adsorption opening of the suction nozzle mechanism, and the service life of the suction nozzle mechanism is prolonged. The IC test equipment comprises the suction nozzle cleaning mechanism.

The invention discloses an IC test sorting machine which comprises a rack, a feeding and discharging arm, a transfer device, a plurality of IC test devices and a plurality of stock bin devices. The rack is provided with a feeding area, a first sorting area and a second sorting area, and the feeding area and the first sorting area are each provided with the stock bin device. The stock bin device is used for receiving and storing the trays and outputting the trays; the charging tray is used for storing ICs; the transfer device and the IC testing device are respectively arranged on the rack, and the transfer device is respectively adjacent to the feeding area and the IC testing device; the feeding and discharging arm is arranged above the rack and can transfer empty trays among the feeding area, the first sorting area and the second sorting area or transfer ICs among the trays, the transfer device and the IC testing device. According to the IC testing and sorting machine, full-automatic testing and sorting can be achieved, the labor intensity of workers is reduced, and the production efficiency is improved.

The utility model relates to the technical field of IC testing, in particular to a temperature control mechanism for IC testing, which comprises an IC testing machine, the IC testing machine is used for testing an IC, the top of the IC testing machine is provided with a homogenizing mechanism, and the homogenizing mechanism comprises a top hollow block, a main shaft, a driving motor, a belt and a stirring piece. By arranging the temperature control mechanism, when the temperature in the IC testing machine is too high, carbon dioxide gas in the thermal expansion cavity is heated to expand, and the carbon dioxide gas pushes the light transmission rod to move upwards, so that the light transmission rod moves to the position of the gas inlet pipe through the groove; according to the utility model, high-pressure air in the air inlet pipe enters the top hollow block through the groove and then enters the IC test machine through the through hole, so that high-temperature air in the IC test machine is replaced and rapidly cooled, the temperature in the IC test machine is reduced, the test environment is maintained in a safe range, and an IC is prevented from being damaged due to too high temperature.

The invention relates to the related technical field of IC testing, in particular to multi-station modular integrated turret type IC testing equipment and a testing method.The multi-station modular integrated turret type IC testing equipment comprises a testing cabinet and a turret arranged in the testing cabinet, and further comprises a bearing base used for placing an IC interface board to be tested, the plurality of bearing seats are arranged on the rotating tower at equal intervals along the circumference, and the rotating tower can drive the plurality of bearing seats to rotate circumferentially, so that the IC interface board to be tested reaches different test stations to form different radio-frequency signal transmitting / receiving units for transmitting and receiving different radio-frequency signals for testing; on the premise that various radio frequency functions of the to-be-tested IC interface board are tested, access positions of different radio frequency signals are concentrated at one position, and wiring at the side of the bearing seat is not needed, so that test wiring harnesses are convenient to arrange in a concentrated manner, the problem of disorder of the wiring harnesses is avoided, and the test is smoothly carried out.

The application discloses a kind of based on crosstalk simulation analog IC synchronous test optimization method and system.The method first obtains the position layout data in analog IC synchronous test process and the test signal data of each analog IC, determines electromagnetic crosstalk information in combination with test signal, and accordingly constructs crosstalk schematic diagram with position layout data;Spectral clustering algorithm is used to cluster the schematic diagram, and the crosstalk path in synchronous test is identified;Based on the schematic diagram and the crosstalk path, an electromagnetic crosstalk signal isolation barrier is designed and deployed in the test environment, the analog IC is simulated and evaluated by constructing and injecting crosstalk simulation signals for independent testing, and the isolation effect is judged;According to the evaluation result, the isolation barrier is optimized to obtain an optimization scheme.The method can effectively identify and isolate the electromagnetic crosstalk path in the synchronous test process, and improve the accuracy and reliability of analog IC testing.

An integral electrical contact pin for electrically connecting a test terminal of tester load board with an IC terminal of an IC device, adapted for short test height. The integral electrical contact pin comprises an upper cantilever arm and lower cantilever arm connected at a back portion. The upper cantilever arm is movable between a first default position to a second and third position, where the upper cantilever arm is in contact with the lower cantilever arm in the second position. A bracket arm is provided, extending in the opposite direction from the two cantilever arms for engagement with the corresponding socket housing.

A method for monitoring parameters of IC testing equipment includes the following steps: S100: configuring key parameters to be monitored in the IC testing equipment as a shareable data file; S200: reading and parsing the key parameters in the data file in real time using monitoring software; S300: comparing the parsed key parameters with preset work standard parameters; S400: triggering an anomaly determination when a deviation is detected between the key parameters and the work standard parameters; S500: sending an anomaly alarm message to a designated terminal via a message push system based on the anomaly determination result, and controlling the IC testing equipment to perform a shutdown operation or enter a pending state. This method uses automated monitoring software to set different judgment conditions according to different parameters, and uses the system push function to promptly detect problems and perform processing and optimization.

The present invention discloses a chip testing pipeline and a chip testing method. The pipeline sequentially includes an automatic loading machine, a material turnover device, an auxiliary loading machine, a testing machine, and an automatic unloading device, and each component is connected by a transmission line; the automatic loading machine grabs chips; the testing machine detects the chips; the automatic unloading device sorts the chips. The chip testing pipeline and the chip testing method of the present invention perform fully automated testing and have a modular structure that can be flexibly combined, enabling the entire testing line to always operate at the highest efficiency; it has the ability to quickly switch between high and low temperature broad temperature ranges and can replace traditional aging equipment for the aging process in the chip testing link; it makes full use of the advantage of the test module being replaceable and upgradable to achieve multi-task input, with the significant feature of flexible manufacturing; in view of the frequent replacement of IC testing, a modularized solution for the test structure body is adopted, providing continuous availability of the equipment for rapid product iteration.