169 results about "Ic testing" patented technology

Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.

A system and method are provided which provides more accurate temperature control of integrated circuits. A system for testing integrated circuit (IC) packages comprises a plurality of IC testing socket bases arranged on a testing board and configured to receive a plurality of IC packages. A plurality of IC testing socket lids are arranged to attach to the testing board. Each IC testing socket lid comprises a temperature sensor to thermally contact the IC package and measure a surface temperature of the IC package, a heater or cooler to directly contact the IC package, and an electronic controller to receive signals from the temperature sensor. The electronic controller is programmed to change the temperature of the heater or cooler responsive to the measured surface temperature of the IC package. A plurality of cooling devices individually removes heat generated by the plurality of IC packages. The electronic controller in each IC testing socket lid is further programmed to control a corresponding cooling device to maintain the surface temperature of the plurality of IC packages within a desired temperature range.

A system for testing both simulated and real versions of an integrated circuit (IC) includes an IC simulator, a simulator manager, an IC tester, and a tester manager. The IC simulator simulates response of the IC to a set of simulated IC input signals by producing a set of simulated IC output signals. The simulator manager, programmed by a user-supplied test bench file, provides the simulated IC input signals to the simulator during the simulation. During the simulation, the simulator manager also generates a set of waveform data sequences, each representing periodically sampled values of a corresponding one of the simulated IC input and output signals. The IC tester includes a separate channel corresponding to each real IC input and output signal. The tester manager converts the waveform data sequence corresponding to each simulated IC input and output signal to a separate set of instructions provided as input to a corresponding one of the IC tester channels. When testing the real IC, each IC tester channel corresponding to a real IC input signal responds to its input instructions by generating and supplying to the IC an input signal having the sequence of values indicted by the waveform data sequence representing the corresponding simulated IC input signal. Each IC tester channel corresponding to an IC output signal responds to its input instructions by periodically sampling the corresponding IC output signal to determine whether the IC output signal has the sequence of values indicated by the waveform data sequence representing the corresponding simulated IC output signal.

A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes a set of probes for contacting pads on a surface of an IC and having a plurality of tester channels. Each channel generates a TEST signal at a tip of a corresponding probe in response to a periodic CLOCK signal with a delay adjusted by drive calibration data supplied as input to the tester channel. The TEST signal produced by each channel includes edges occurring in a timing pattern controlled by programming data provided as input to each tester channel. To calibrate test signal timing of all channels, each channel is programmed to generate a test signal having the same repetitive edge timing pattern at the tester channel's corresponding probe tip. The test signal produced at each probe tip is then cross-correlated to a periodic reference signal having the same repetitive edge timing pattern. The drive calibration data of each channel is then iteratively adjusted to determine a value which maximizes the cross-correlation between its output test signal and the reference signal. To maximize the accuracy of the timing calibration, each repetition of the test and reference signal edge pattern provides pseudo-randomly distributed time intervals between successive signal edges.

For testing electrical properties of packaged IC devices, there is provided an apparatus which includes a test board which is located at a testing station and provided with a plural number of contacting sockets for connecting individual IC devices to an IC tester separately and independently of each other, a loader which is located at a loading station and adapted to feed untested IC devices toward the test board, an unloader which is located at an unloading station and adapted to discharge tested IC devices from the test board at the testing station, and a device transfer mechanism which is movable across the testing station to transfer untested IC devices from the loader to the test board and also to transfer tested IC devices from the test board to the unloader. Upon detecting completion of a test on one of IC devices in one socket of the test board, a fresh untested IC device is transferred to the testing station to replace the tested IC device. As soon as the fresh IC device is set in position in that socket, execution of a test program is started with respect to that socket on the test board.

A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.

The present invention is test bench configuration and measurement process for IC test. The test bench includes material stacking and feed buffering area for stacking ICs to be tested; empty IC tray dispatching mechanism for sucking empty tray for concentration in the empty IC tray area; double-IC conveying arm with double sucking heads to suck one pair of ICs; one pair of alternately conveyed temporary storing trays for conveying ICs to IC test area for continuous test; and tested IC setting area. In the test bench, all tested ICs are set based on their parameters. The present invention has high efficiency, small covered area and short processing path.

A temperature control system for IC tester, comprising: a test socket; a compressing device including a heat exchanger and a thermoelectric cooler (TEC); and a test head having a temperature sensor. The test head is configured at the front end of the compressing device such that, upon placing at least one device under test (DUT) onto the test socket, the test head coerces tightly one of the DUTs through downward pressure from the compressing device thereby allowing the temperature sensor to detect the surface temperature of the DUT to obtain a temperature signal, and then feed such a temperature signal back to a control processing unit for operations to generate a linear control signal thus that, through the control of the linear control signal, the heat absorption and heat discharge functions of the TEC are enabled to further control the temperature of the DUT within a determined range.

The invention discloses a memory IC testing and classifying device, comprising a feeding box, an empty box, at least one receiving box and a transfer device arranged at the front end of the machine platform, and at least one testing device, a second transfer device and a removal receiving box arranged at the rear end of the machine platform, as well as a first material-moving device and a second material-moving device arranged among the feeding box, the receiving box and the testing box; the feeding box and the receiving box are used to hold the memory ICs to be tested/tested respectively; the testing device is a test circuit board provided with a plurality of test sheath seats; the first material-moving device transfers more than one memory IC to be tested in the feeding box to the firsttransferring device; the first transferring device is capable to preheat the held memory ICs to be tested, and make displacement movement to ensure the testing device to take materials at different positions. The invention is capable to transfer and test a plurality of memory ICs simultaneously, thereby, the testing capability is largely enhanced and the service efficiency of each device is improved effectively.

An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) (such as an interposer or a 3D IC) formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels (such as probes). The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that electrical characteristics of the variety of TSVs can be tested all at once.

An test block includes a box-like body and four rails extending from side edges of the body. During thermal testing, the test block is mounted between a test head and a test socket such that the rails provide a thermal path between the test block body and contact pads formed on the test socket. In this manner the rails emulate the thermal path formed by the metal leads extending from a conventional Quad Flat Pack Integrated Circuit (QFP IC), thereby reliably duplicating the actual thermal path of the QFP IC. The test block is mounted on the test system and its temperature is measured before and after testing QFP IC devices. Confirming that the test block is within test temperature specifications before and after the QFP-IC test procedure provides a highly reliable verification that the QFP-IC's actual test temperature is within the test temperature specifications.

The invention discloses an IC (integrated circuit) testing device and method. The device comprises a controller, a socket, N testing modules, N relays, an analog switch group and a communication circuit, a second end of the analog switch group is connected with the socket, a control end of the analog switch group is connected with the controller, L-level multi-input analog switches are cascaded to form the analog switch group, the analog switch group is used for selecting corresponding pins of a chip to be tested to connect with corresponding testing modules according to control of the controller, a first end of the communication circuit is connected with the controller, the other end of the communication circuit is connected with the socket, and the communication circuit is used for establishing communication between the controller and the socket. According to the testing device, the analog switch group formed by cascade of the L-level multi-input analog switches is arranged between the N testing modules and the socket for placing chips to be tested, pins of the chips to be tested cannot be directly with the controller when the chips to be tested are tested, a plurality of controller are omitted, controller resources are greatly saved, cost of the testing device is reduced, and structures of the testing device are simplified.