2860results about "Fixed capacitor electrodes" patented technology

The invention belongs to the technical field of nickel electrode slurry preparation, discloses a preparation process of ultra-fine particle size roll-printed nickel electrode slurry for an ultra-high capacity MLCC, and aims to solve the problems that in the prior art, ultra-fine nickel powder is easy to oxidize, the cost of covering nickel nitride powder is high, a covering layer is easy to damage and agglomerate during dispersion, and the performance of the slurry is poor. The method comprises three steps of raw material pretreatment, synchronization of material dispersion and nitridation, post-treatment and nitrogen protection, wherein the pretreatment is used for removing impurities and preventing oxidation, dispersion and nitridation are carried out synergistically through a sand mill and an ultrahigh-pressure homogenizer in a graded regulation and control mode, the post-treatment comprises filtering, inspection and double-layer vacuum packaging, the raw materials are prepared according to a specific proportion, key parameters are precisely regulated and controlled, and finally the slurry is prepared. Roll printing adaptability and co-firing requirements are met, independent nitridation and reduction procedures are omitted, cost is reduced, slurry uniformity, dispersion stability and MLCC reliability are improved, and large-scale mass production can be achieved.

An apparatus includes a case capable of receiving a plurality of capacitive elements, each capacitor element having at least two capacitors, and each capacitor having a capacitive value. The apparatus also includes a cover assembly with a peripheral edge secured to the case. The cover assembly includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly generally at a central region of the cover assembly. Each cover terminal is connected to one of the at least two capacitors of the respective one of the plurality of capacitive elements. The cover assembly also includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly at a position spaced apart from the cover terminal generally at the central region of the cover assembly.

A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a plurality of capacitance formation portions including first dielectric layers and internal electrodes alternately arranged in a first direction. An intermediate layer disposed is between the adjacent capacitance formation portions and includes a second dielectric layer. An external electrode is disposed on the body and connected to the internal electrode. The first and second dielectric layers may include a plurality of grains and pores. An average grain size of the first dielectric layer may be smaller than an average grain size of the second dielectric layer. A porosity of the first dielectric layer may be lower than a porosity of the second dielectric layer.

The multilayer electronic component includes a laminate in which internal electrodes and dielectric layers are alternately laminated, a base electrode, and an external electrode. The internal electrodes include a first internal electrode and a second internal electrode. The base electrode includes a first base electrode and a second base electrode. The external electrode includes a first external electrode and a second external electrode. Each of the first base electrode and the second base electrode contains a plurality of sintered bodies made of dielectric particles. At least a part of the plurality of sintered bodies is located at the interface between each base electrode and the laminate.

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a triangular grid mode more reasonably and precisely, so that the capacitor can store more charges.

In a multilayer ceramic capacitor, a segregation amount of silicon and magnesium on an outer layer side of an outermost internal electrode layer is larger than a segregation amount of silicon and magnesium on an inner layer side of the outermost internal electrode layer, and when a region defined by an existence region of the outermost internal electrode layer and a segregation region of silicon and magnesium in contact with the outermost internal electrode layer is defined as a first region, a line edge roughness of an outer layer side of the first region is larger than a line edge roughness of an inner layer side of the first region.

A multilayer ceramic electronic component includes a first extension portion including a bent portion in a cross section. The multilayer body is divided into four regions by a straight line passing through a middle portion of the multilayer body in a lamination direction and a straight line passing through a middle portion of the multilayer body in a length direction, and a region adjacent to a first main surface and a first end surface among the divided four regions is defined as a first reference region, and a regression line derived based on values of x and y with respect to the bent portion in a reference region is defined as a virtual connection line, the virtual connection line intersects an effective layer portion.

A multilayer ceramic electronic device includes an element body including a dielectric layer and an electrode layer being laminated. The dielectric layer contains a main component represented by a formula ABO3. The dielectric layer contains 0.05 mol or more and 0.25 mol or less Mn oxide in terms of MnO; 1.00 mol or more and 2.50 mol or less Mg oxide in terms of MgO; 0.50 mol or more and 1.50 mol or less R oxide in terms of R2O3, where R includes at least one selected from the group consisting of Y, Dy, Ho, Yb, Lu, Gd, and Tb; and 0.05 mol or more and 0.45 mol or less Zr oxide in terms of ZrO2, with respect to 100 mol of the main component. The dielectric layer further contains V. The dielectric layer has a Zr / V ratio of 2.00 or more and 4.00 or less in atomic ratio.

The invention discloses a fixed vacuum capacitor with a short circuit function, which comprises a vacuum capacitor body, a movable conducting rod is arranged in the vacuum capacitor body, and the conducting rod is configured to connect two electrode groups of the vacuum capacitor body when the conducting rod deflects along a set direction so as to realize short circuit of the vacuum capacitor body. The movable conducting rod is arranged in the vacuum capacitor body, and when the conducting rod deflects, the two electrode groups can be connected to realize short circuit, so that the fixed vacuum capacitor has a short circuit function under the condition that the volume of the fixed vacuum capacitor is not changed; according to the design, the tedious problem that the circuit design of the radio frequency matcher needs to be changed by dismounting the fixed vacuum capacitor in specific scenes such as test and debugging of the radio frequency matcher and design of double-frequency and multi-frequency matchers is effectively solved, and the operation convenience is greatly improved; the specific requirements of a user for rapidly switching the working frequency and changing the circuit design of the radio frequency matcher are met, and the working efficiency is improved.

A multilayer ceramic capacitor includes a multilayer body and outer electrodes on two surfaces of the multilayer body. The multilayer body includes an inner-layer portion and two outer-layer portions. The inner-layer portion includes first dielectric layers laminated in the lamination direction and a first inner electrode between the first dielectric layers. Each outer-layer portion includes at least one second dielectric layer and a second inner electrode in contact with the at least one second dielectric layer. A length of the second inner electrode is less than a length of the first inner electrode, or a width of the second inner electrode is less than a width of the first inner electrode. When each outer-layer portion is divided into two equal regions, a porosity of a region near the inner-layer portion is less than a porosity of a region farther from the inner-layer portion.

Via array configurations for metal-insulator-metal (MIM) capacitor structures are disclosed herein. An exemplary MIM capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. A metal via array, which has a first metal via and a second metal via, is connected to the capacitor top metal layer and the capacitor bottom metal layer. A portion of the capacitor top metal layer covers an area of the second dielectric layer extending from the first metal via to the second metal via. From a top view, the portion of the capacitor top metal layer surrounds the first metal via and the second metal via.

A capacitance module may include a capacitance electrode on a first substrate, shielding material disposed on a second substrate where the second substrate is aligned with the first substrate, an antenna where the shielding material is between the antenna and the capacitance electrode, and a continuous opening defined in the shielding material. The continuous opening may include a branching shape, the branching shape having a stem and multiple branches extending from the stem; and the continuous opening may overlap with the antenna.

The utility model discloses a silicon capacitor electrode structure and a silicon capacitor, which can further improve the capacitance of a capacitor in a limited space by nesting, combining and arranging a plurality of groups of element arrays distributed in a quadrilateral grid mode more reasonably and precisely, so that the capacitor can store more charges.

The invention provides an implantable wireless passive blood pressure monitoring device, which relates to the technical field of blood pressure detection and comprises a blood pressure sensor and an in-vitro reading device, the blood pressure sensor comprises an outer inductance coil and an internal interdigital capacitor; the inductance coil is connected with the interdigital capacitor through a cross-layer line to form a capacitance-inductance LC loop; the inductance coil and the interdigital capacitor are packaged in the soft base material silicon rubber; the blood pressure sensor is used for being attached to the outer wall of an artery blood vessel, and the resonant frequency of the blood pressure sensor can change along with compression tensile deformation of the blood vessel; the in-vitro reading device is used for reading the resonant frequency of the blood pressure sensor; wherein the resonant frequency read by the in-vitro reading device is used for calculating a blood pressure value. The implantable wireless passive blood pressure monitoring device provided by the invention is used for providing a blood pressure monitoring mode with high measurement precision and small trauma so as to improve the accuracy and comfort of blood pressure monitoring.

The invention relates to an internal serial metallized film, a preparation method, a filter capacitor and a base film, the base film is made of a blending material of polyethylene glycol terephthalate and polyethylene naphthalate according to a mass ratio of 2: 3, and the thickness of the base film is 8-12 [mu] m; the multi-layer metallization layer is arranged on the base film and comprises a first metal layer, a buffer layer and a second metal layer, the buffer layer is located between the first metal layer and the second metal layer, the patterned structure forms a plurality of conductive units which are connected in series on the multi-layer metallization layer, each conductive unit is in a regular hexagon shape, and the first metal layer is arranged on the first metal layer. The side length of the conductive units is 3-6mm, and an isolation belt with the width of 0.3-0.8 mm is arranged between the adjacent conductive units. According to the invention, a plurality of key performance indexes such as high-frequency filtering performance, voltage endurance capability, oxidation resistance, structural stability, light transmission and the like are optimized and improved.

A system including a plurality of first wires and a plurality of second wires is disclosed. Each second wire overlaps over one or more first wires at a respective overlapping area of one or more first wires. A dielectric material is disposed in a vertical gap at each respective overlapping area forming a capacitance sensor including a first electrode corresponding to a first wire and a second electrode corresponding to a second wire. The first and second electrodes are connected to a positive bias and a negative bias of at least one voltage source, respectively. The system includes at least one processor configured to periodically measure change in respective electric field of each capacitance sensor of a subset of capacitance sensors of a plurality of capacitance sensors, and store data corresponding to periodically measured change in the respective electric field of each capacitance sensor of the subset of capacitance sensors.

An electronic device and a manufacturing method including a dielectric layer according to at least some embodiments are disclosed. The electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a first dielectric layer between the first electrode and the second electrode, a second dielectric layer having a rutile phase, a third dielectric layer between the first dielectric layer and the second electrode, and a third dielectric layer between the second dielectric layer and the second electrode and including a material having a higher energy bandgap than a material included in the second dielectric layer.

A multilayer ceramic electronic component includes a multilayer body and a pair of external electrodes at both end portions of the multilayer body. The external electrodes include a main surface-side external electrode. The main surface-side external electrode includes a main surface-side base electrode layer, a main surface-side conductive resin layer above the main surface-side base electrode layer, and a main surface-side plated layer above the main surface-side conductive resin layer. The main surface-side conductive resin layer includes a conductive resin layer recess recessed towards a side of the multilayer body at a boundary interface with the main surface-side plated layer, in a cross-sectional view along the lamination direction and the length direction.

A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrodes alternately laminated therein, and two end surfaces opposing each other in a length direction, and two side surfaces opposing each other in a width direction, and two external electrodes respectively on the two end surfaces of the multilayer body. At least one of two opposed main surfaces of the multilayer ceramic capacitor includes raised portions provided respectively on one side and another side with a middle portion of the main surface interposed therebetween. The raised portions are each raised to become thicker in the lamination direction from the middle portion toward an outer periphery of the main surface.

A multilayered capacitor according to present disclosure includes a dielectric layer including an aluminum nitride (AlN)-based compound, the aluminum nitride-based compound includes AlN, or a doped AlN compound in which AlN is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, and a crystal orientation of the aluminum nitride-based compound is a c-axis crystal orientation.

A multilayer ceramic electronic component includes a component body, a first external electrode provided on a first end surface of the component body, and a second external electrode provided on a second end surface of the component body. An absolute value of a difference between a surface roughness of a first side surface and a surface roughness of a second side surface of the component body is smaller than an absolute value of a difference between a surface roughness of a first main surface and a surface roughness of a second main surface.

A multilayer ceramic capacitor includes a multilayer body and external electrodes at both end portions of the multilayer body. The external electrodes include main surface-side external electrodes. In a cross-sectional view along a lamination direction and a length direction, main surface-side external electrodes include a recess recessed towards a side of the multilayer body, a first bulge on a central side of the multilayer body in the length direction, and a second bulge at an end portion side of the multilayer body in the length direction, between which the recess is interposed. A distance between a vertex of the first bulge and a vertex of the second bulge in the length direction is longer than a distance between an inner end portion of the main surface-side external electrode and the vertex of the first bulge in the length direction.

A multilayer electronic component includes a body including a capacitance formation portion including a dielectric layer and internal electrodes alternately arranged in a first direction and cover portions disposed on the capacitance formation portion in the first direction, first to sixth surfaces; external electrodes disposed on the third and fourth surfaces; side margin portions disposed on the fifth and sixth surfaces; and a first extension portion disposed to extend to portions of the first and second surfaces, and wherein at least a partial region of the first extension portion has a curvature, wherein when an average thickness of the side margin portion is WM0 and a radius of curvature of at least a portion of the first extension portion is R, WM0 and R may satisfy 1.1<R / WM0<2.

In a multilayer ceramic capacitor, a plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer. A coverage of the intermediate electrode layer is higher than a coverage of the first internal electrode layer and the second internal electrode layer.

The present disclosure provides a multilayer ceramic capacitor which can be manufactured even at a relatively low firing temperature and has excellent moisture resistance. The capacitor includes: a capacitor portion in which dielectric layers and internal electrode layers are alternately stacked; and a coating layer disposed on the outside in the stacking direction of the capacitor part, in which the coating layer contains a perovskite-type compound represented by general formula ABO3 and contains, in a metal state, one or more elements selected from Cu, Au, Ag, Al, Ir, and W, and the number of atoms of the elements is 0.002-0.15 with respect to the number of atoms of B-site elements of the general formula 100.

A multilayer ceramic electronic component includes a multilayer body including ceramic layers and internal conductive layers and a pair of external electrodes on both ends of the multilayer body in a length direction. The internal conductive layers include first internal conductive layers and second internal conductive layers. The pair of external electrodes include a first external electrode including a first base electrode layer connected to the first internal conductive layer, and a second external electrode including a second base electrode layer connected to the second internal conductive layer. The first and second base electrode layers each include a metal portion and non-metal portions in the metal portion. In a cross-sectional view perpendicular or substantially perpendicular to a width direction, an average area of non-metal portions in a first population of non-metal portions each with a circularity about 0.4 or less is about 12 μm2 or less.

In a multilayer electronic component according to an embodiment of the present disclosure, a step of the multilayer electronic component may be alleviated by adjusting the shape of the reinforcing pattern included in the reinforcing portion disposed on at least one of one surface and the other surface of the capacitance formation portion in the first direction, and the occurrence of bending cracks may be suppressed.

To provide a laminate type electronic component that relieves a problem of deterioration in moisture resistance reliability of the laminate type electronic component that occurs due to the decrease in a moisture resistance permeation path.SOLUTION: A laminate type electronic component includes: a dielectric layer 111; internal electrodes 121 and 122 disposed alternately with the dielectric layer in a first direction; a lamination part 110 having a first surface and a second surface which face each other in the first direction, a third surface and a fourth surface which face each other in a second direction that is perpendicular to the first direction and is coupled to at least a part of the internal electrodes, and a fifth surface and a sixth surface which face each other in a third direction that is perpendicular to the first direction and the second direction; a protection part 120 disposed on the third surface and the fourth surface; and external electrodes 131 and 132 disposed on the lamination part and the protection part and coupled to the internal electrodes. The dielectric layer includes a first dielectric crystal grain and the protection part includes a second dielectric crystal grain. An average size of the second dielectric crystal grains may be smaller than an average size of the first dielectric crystal grains.SELECTED DRAWING: Figure 3

A multilayer electronic component includes a body including a dielectric layer, and internal electrode layers disposed alternately in a first direction with the dielectric layer, and; first and second external electrodes disposed on the third and fourth surfaces, respectively, wherein internal electrode layer includes a main portion and an internal electrode extending from the main portion and connected to the external electrode through the lead portion, and a dummy electrode spaced apart from the internal electrode and connected to the external electrode, and a width of the lead portion may be smaller than a width of the main portion, at least a portion of the dummy electrode overlap the internal electrode in a length direction, and the dummy electrode may not overlap the internal electrode of another layer in a laminate direction.

To provide a multilayer ceramic electronic component that maintains good temperature characteristics while suppressing the occurrence of thermal cracks.SOLUTION: A multilayer ceramic electronic component is formed by laminating dielectric layers and internal electrode layers. The internal electrode layer located outermost in the lamination direction among the internal electrode layers is designated as the first internal electrode layer. The Mn concentration in the first internal electrode layer is higher than the Mn concentrations in the other internal electrode layers.SELECTED DRAWING: Figure 4