24 results about "Deep reactive-ion etching" patented technology

The invention discloses a CoWoS packaging technology for a GPU chip, and the technology comprises the following steps: S1, forming a glass substrate with a glass wafer as a temporary carrier, and coating a temporary bonding glue layer; s2, using a deep reactive ion etching technology to form a copper through silicon via, depositing an insulating layer and a barrier layer, patterning a metal wiring layer, and using a Cu Pin process to optimize TSV manufacturing to form a copper column interconnection structure; s3, forming a first EMC layer by using an epoxy molding compound; s4, the first EMC layer is thinned and flattened, the upper end face of the copper column is exposed, and the composition is defined as an intermediate layer; s5, making micro-bumps on the front surface of the interposer, and forming an insulating layer on the surface; and S6-S13, sequentially completing chip stacking, plastic packaging, glass substrate removal, C4 bump manufacturing, film pasting, cutting, butt joint and BGA ball implantation. According to the process, the TSV process is simplified through the CuPin process, the equipment investment is reduced by 40%, the productivity is improved by 30%, the process is compatible with the existing CoWoS-S process, and core equipment does not need to be transformed.

The invention discloses a flexible micro-nano cross-scale integrated metasurface single-cell sensor and a preparation method thereof, and relates to the field of biosensing. The sensor comprises a PDMS flexible substrate layer, a micro-nano cross-scale structure layer and a gold metal film layer, the micro-nano cross-scale structure layer adopts a nesting design of a micron-scale single cell capture unit and a nano-scale plasmon structure, so that single cell precise limiting and local electromagnetic field multi-stage enhancement are realized, and the problems of poor adaptability and low sensitivity of a traditional rigid sensor are solved. According to the preparation method, a silicon-based template-replication forming-magnetron sputtering process is adopted, a silicon template is prepared through deep ultraviolet lithography and deep reactive ion etching, a gold film is deposited after a flexible micro-nano structure is copied by PDMS, and large-scale mass production of the sensor is realized. The sensor has excellent flexibility, biocompatibility and high detection sensitivity, can realize single cell level accurate and in-situ detection, is suitable for the scenes of early disease screening, cell biological analysis, personalized medical treatment and the like, and is simple in process and low in cost.

The invention provides an MEMS differential capacitive z-axis accelerometer without cross-axis interference and a preparation method thereof, and relates to the technical field of sensors, the accelerometer adopts two (111) crystal orientation silicon wafers to be bonded to form a sandwich structure, the accelerometer comprises a first silicon wafer provided with a first fixed electrode and a first cavity, and a second silicon wafer provided with a second fixed electrode and a second cavity, and a movable mass block, an elastic beam, a second cavity, a movable electrode and a second fixed electrode are integrated in the second silicon wafer. The areas of the upper fixed electrode and the lower fixed electrode are both larger than the area of the middle movable electrode, so that the effective sensing area is constant, and cross axis interference is eliminated from the structure source. The preparation method combines key processes of deep reactive ion etching, TMAH anisotropic wet etching and gold-gold thermocompression bonding. The method has the advantages of high sensitivity, excellent linearity and strong common-mode rejection capability, and is suitable for the field of inertial measurement with strict requirements on precision and stability.

The invention discloses a preparation method of a near-infrared achromatic super lens based on a nanoimprint technology, and relates to the technical field of micro-nano manufacturing. The preparation method comprises the following steps: 1, designing a target super lens by using finite element simulation software based on a time domain finite difference method, a particle swarm algorithm and a scalar diffraction algorithm; 2, preparing a silicon female die corresponding to the super lens according to the designed target super lens parameters by using electron beam lithography and deep reactive ion etching; 3, carrying out surface fluorination treatment on the silicon female die; and 4, preparing a corresponding sub-mold according to the silicon female mold, carrying out imprinting by using a nano imprinting technology and the sub-mold, and finally, etching the a-Si layer on the surface of the substrate through deep reactive ion etching by taking imprinting glue as an etching mask to obtain the super lens. According to the invention, the nanoimprint technology can be used for manufacturing the near-infrared achromatic superlens, so that the near-infrared achromatic superlens gets rid of dependence on a high-precision photoetching machine.

The application relates to the technical field of resonators, and discloses a MEMS resonator and a preparation method thereof. The preparation method of the MEMS resonator comprises the following steps: forming a first wafer, wherein the first wafer at least comprises a first monocrystalline silicon layer; forming a second wafer, wherein the second wafer at least comprises a second monocrystalline silicon layer and a piezoelectric material layer located on the second monocrystalline silicon layer; bonding the first wafer and the second wafer to form a laminated structure comprising the first monocrystalline silicon layer, the piezoelectric material layer and the second monocrystalline silicon layer, and performing high-doping treatment on the first monocrystalline silicon layer and the second monocrystalline silicon layer before or after bonding; and performing deep reactive ion etching on the laminated structure to form a resonator body, a connecting beam and an anchor, wherein the resonator body is arranged in a suspended mode, and the resonator body is connected with the anchor through the connecting beam. The application improves the electromechanical coupling efficiency and the quality factor of the MEMS resonator, and guarantees the temperature stability of the MEMS resonator.

The invention discloses a method for processing a special-shaped cavity structure in a silicon-based terahertz circuit, which comprises the following steps of: firstly, determining the shape and parameters of an upper-layer cavity of the special-shaped cavity structure in the silicon-based terahertz circuit, and processing the upper-layer cavity and a lower-layer structure of the special-shaped cavity structure in the silicon-based terahertz circuit; and finally, bonding the processed upper-layer cavity structure with the lower-layer structure to complete the processing of the special-shaped cavity structure in the silicon-based terahertz circuit. According to the scheme, the hard mask silicon oxide is patterned twice according to different depths of the cavities in the processing process of the upper-layer cavity, finally, the deep reaction plasma etching equipment is utilized to complete etching of two steps with different depths in one step, the process steps are reduced by adopting an All-In-One mode, the process efficiency is improved, and the process cost is reduced. And the situation of side wall damage caused by multiple times of etching of multiple steps is also avoided.

The invention provides a measuring method of an ocean optical fiber temperature sensing unit with a cover-type silicon-based structure. The unit comprises a single-mode optical fiber core, a single-mode optical fiber cladding, the cover-type silicon-based structure and polydimethylsiloxane. According to the method for measuring the ocean optical fiber temperature sensing unit of the silicon-based structure, the silicon substrate is etched through deep reactive ion etching, it is guaranteed that the surface of the silicon substrate is smooth, polydimethylsiloxane sensitive to the temperature is injected into the hollow-core cover-type silicon-based structure, optical path difference estimation is achieved through Buneman frequency estimation, and the optical path difference is accurately measured. The demodulation resolution of temperature sensing is improved, and the demodulation operand is reduced. According to the invention, a complex sensing probe and a demodulation algorithm are not needed, a mapping relation between the ocean temperature signal and the optical fiber sensor is established, and rapid and high-precision detection of the ocean temperature signal is realized.

The application provides an infrared thermoelectric array and a preparation method thereof. The method comprises the following steps: providing a substrate with infrared thermocouples arranged in an array on the front surface; forming a patterned dielectric layer and a release groove etching window on the back surface of the substrate, wherein the dielectric layer comprises an outer dielectric layer and an inner dielectric layer; forming a photoresist layer on the outer dielectric layer; etching the substrate to a first preset depth by deep reactive ion etching through the release groove etching window; removing the inner dielectric layer; and etching the substrate exposed on the inner part of the outer dielectric layer by deep reactive ion etching to form a plurality of bosses arranged in an array. The infrared thermoelectric array prepared by the method has reduced thermal conductivity and reduced risk of film rupture. In addition, the bosses can quickly conduct heat, so that the temperature of the cold junction area is consistent with the ambient temperature. When the bosses are etched, only the side etching of the remaining substrate needs to be considered, which greatly reduces the influence of side etching on the bosses, thereby greatly reducing the size of the bosses and improving the array integration.

The teachings of the present disclosure enable rosette strain gages that can be cost-effectively produced in high volume with substantially uniform performance. Rosette strain gages in accordance with the present disclosure comprise a plurality of semiconductor strain gages that are sculpted from a device layer of a semiconductor-on-insulator wafer using deep reactive ion etching, yielding very good control over their electrical properties and physical dimensions. The strain gages are provided to an automated assembly system while attached to a frame via one or more sprues that are configured to ease their removal by the automated assembly system. The strain gages are mounted on a rosette substrate having an arrangement of contact pads and traces for connecting pairs of contact pads to different gages. The materials of the rosette substrate and strain gages are selected to efficiently transfer strain from an object under test to the strain gages.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

This invention discloses a method for fabricating a conical microporous semi-transparent crystalline silicon photovoltaic cell, relating to the field of photovoltaic cells. The method includes the following steps: silicon wafer cleaning and preparation, photolithography to define the micropore pattern, deep reactive ion etching to prepare vertical micropores, micropore tapering treatment, diffusion doping to form a PN junction, alumina passivation layer deposition, post-annealing treatment, silicon nitride antireflection layer deposition, double-sided microgrid electrode fabrication, Low-E film deposition, and module encapsulation. This invention also discloses a conical microporous semi-transparent crystalline silicon photovoltaic cell fabricated using the above method. Through the synergistic design of the conical micropore structure and the selective Low-E film, this invention significantly expands the effective light transmission angle range of incident light without sacrificing the light absorption area, enabling the module to maintain stable light uniformity under different solar illumination angles. This significantly improves the utilization rate of the near-infrared band, reduces the air conditioning cooling load, and achieves a balance between power generation performance and building insulation function.

This invention provides a polyimide thin-film passive optical filter device and its fabrication method. The fabrication method includes: providing a semiconductor substrate, and sequentially forming a dielectric layer and a polyimide thin film layer on the front side of the semiconductor substrate; forming a barrier layer on the polyimide thin film layer; forming a first patterned photoresist layer on the barrier layer to obtain a photolithographic pattern of the outer contour of the thin film; sequentially etching the barrier layer, the polyimide thin film layer, and the dielectric layer based on the first patterned photoresist layer; forming a second patterned photoresist layer on the back side of the semiconductor substrate to obtain a photolithographic pattern of the inner contour of the thin film; etching the semiconductor substrate using a deep reactive ion etching process based on the second patterned photoresist layer to form an etching window; and removing the dielectric layer using a dry etching process based on the etching window to obtain the polyimide thin-film passive optical filter device. This fabrication method can effectively improve the performance of the polyimide thin film.

A method of fabricating a patterned mask on a silicon wafer includes grind-polishing a pre-cut silicon wafer; ion beam figuring the grind-polished silicon wafer, transferring a coronagraphic pattern to a surface of the ion beam figured silicon wafer; and in a cryogenic deep reactive ion etching process, applying black silicon to exposed silicon regions of the ion beam figured silicon wafer. The cryogenic etching process is used to fabricate black silicon to achieve a high aspect ratio structure with higher etch rate than conventional reactive ion etching.

An apparatus for delivering an agent to a target recipient includes a planar substrate having a first surface and a second surface, a reservoir defined in the first surface of the planar substrate, and a plurality of microstructures projecting from the second surface of the planar substrate. Each of the plurality of microstructures includes a delivery channel that extends from the reservoir to a channel opening defined in an exterior surface of the microstructure. In some embodiments, a needle with microchannels can be fabricated using a silicon wafer. A primary channel is etched into the wafer, and then a second silicon wafer can be bonded on top of the initial wafer. Microchannels can be formed from the primary channel to a surface of the wafer using deep reactive ion etching. The diameter of the microchannels may be chosen for drug delivery. The illustrative diameter of the microchannels is 4 micrometers.

The invention relates to a preparation method of an MEMS test chip, and the method comprises the steps: S1, obtaining an MEMS device which comprises a substrate and a device structure which are stacked; s2, performing transverse etching on the substrate to form a side cavity; and S3, etching a region corresponding to the side cavity on the device structure to form a U-shaped cavity with an upward opening, and etching the substrate downwards from the bottom of the U-shaped cavity to communicate the U-shaped cavity with the side cavity to form a cantilever beam. According to the method, expensive and complex deep reactive ion etching is avoided, the used wafer is a common Si wafer, and a relatively expensive SOI wafer is not needed. The used RIE etching is a common low-cost technological means in a laboratory, and the equipment threshold and the manufacturing cost are greatly reduced.

The application discloses a processing method of micro-silicon spherical cavities, which comprises the following steps: sequentially performing deposition etching mask, photolithography, removing part of the etching mask, removing glue and deep reactive ion etching on the side of a silicon wafer to be patterned; obtaining the micro-silicon spherical cavities through wet etching; and inputting the real-time collected images into an etching circle detection module and a roughness prediction model and an etching depth prediction model which are pre-established and trained, to obtain the top view, sectional view images of the micro-silicon spherical cavities under the current etching state and the etching related prediction values; comparing the etching related prediction values with the expected indicators, if the expected indicators are not reached, adjusting the wet etching related process parameters and continuing the wet etching; if the expected indicators are met, stopping the etching to obtain the micro-silicon spherical cavities meeting the expected indicators; the etching circle detection module is based on a Hough circle detection algorithm, the roughness prediction model adopts a BP neural network, and the etching depth prediction model adopts a convolutional neural network.

The invention relates to a preparation method of an on-chip magnetic core power inductor. The preparation method comprises the following steps: etching a silicon groove of an inductor end winding and a silicon groove of an inductor middle winding on the upper surface of a wafer by utilizing photoetching and deep reactive ion etching; forming an insulating film layer, a titanium barrier layer and a copper seed crystal layer on the groove walls of the inductor end winding silicon groove and the inductor middle winding silicon groove in sequence; copper is fully plated in the inductor end winding silicon groove and the inductor middle winding silicon groove through electroplating; carrying out photoetching and deep reactive ion etching on bulk silicon at the peripheries of the upper ends of the inductor end winding silicon groove and the inductor middle winding silicon groove on the upper surface of the wafer, and coating a fluid magnetic material formed by fusing soft magnetic powder and epoxy resin to form a part of magnetic core; polishing the lower surface of the wafer by adopting a CMP (Chemical Mechanical Polishing) process until the lower end of the inductor end winding is exposed, and forming a welding spot at the exposed part of the lower end of the inductor end winding; carrying out photoetching and deep reactive ion etching on bulk silicon at the peripheries of the lower ends of the inductor end winding silicon groove and the inductor middle winding silicon groove on the lower surface of the wafer, and coating a fluid magnetic material formed by fusing soft magnetic powder and epoxy resin to form the other part of magnetic core; and polishing the lower surface of the magnetic core by adopting a CMP (Chemical Mechanical Polishing) process to expose welding spots of the end winding of the inductor to obtain the prepared on-chip magnetic core power inductor. The problems that a traditional inductor is large in size, high in material cost and incompatible with the CMOS technology, and a chip-level fully-integrated power supply product with high integrated packaging efficiency cannot be achieved are solved.

The invention discloses a silicon capacitor and a preparation method thereof, and relates to the technical field of power electronic components. The preparation method of the silicon capacitor comprises the steps that a conductive substrate is provided, the upper surface of the conductive substrate is etched to form a plurality of stand columns and side walls surrounding the stand columns, communicated grooves are formed among the stand columns, and deep reactive ion etching of the Bosch technology is adopted to enable the side walls of the stand columns to be wavy faces in the vertical direction; forming a dielectric structure on the conductive substrate, wherein the dielectric structure covers the side wall and the bottom wall of the groove and the upper surface of the stand column; depositing an upper electrode on the dielectric structure; etching the upper electrode to enable the upper electrode to form an electrode block corresponding to each column, and forming a capacitor assembly by the electrode block, the dielectric structure overlapped with the projection of the electrode block and the conductive substrate; forming a passivation layer on the electrode block; and etching the passivation layer and preparing an extraction electrode, and connecting the extraction electrode with the plurality of electrode blocks respectively to form the silicon capacitor. According to the silicon capacitor and the preparation method thereof, the capacitance density of the silicon capacitor can be improved.

The invention relates to a component (1) intended to be in frictional contact with another component, said component (1) being coated with an integral electrically conductive layer (4) at least partially covering each surface of said component (1), on at least one of which a friction occurs, this surface being referred to as a functional surface (2), said functional surface (2) being surrounded by a plurality of side surfaces (3), according to the invention, the component (1) has, on its functional surface (2), a texture formed by successive grooves (2a) coated with the electrically conductive layer (4), said grooves (2a) each extending between two side surfaces such that the electrically conductive layer (4) remains entirely on the component (1) despite wear caused by friction on the functional surface (2). The invention also relates to a method for manufacturing a component (1) by a deep reactive ion etching (DRIE) process, wherein surface defects on the sides machined by the DRIE process are used to form said recesses (2a).

The invention discloses a manufacturing method of a semiconductor strain gauge. The manufacturing method comprises the following steps: S1, epitaxially growing a boron-doped silicon epitaxial layer on a (110)-oriented P-type monocrystalline silicon substrate; s2, depositing a passivation layer on the surface of the epitaxial layer in the step S1; s3, exposing the position where metal deposition needs to be carried out through a first photoetching step; s4, depositing an aluminum metal layer on the surface of the epitaxial layer exposed in the step S3 to form a metal short circuit part and a lead bonding pad; s5, patterning the passivation layer through a third photoetching step to form a hard mask pattern for deep silicon etching; and S6, performing deep reactive ion etching to form a strain gauge wire grid. The strain gauge is simple in structure, can be reduced in size, and is suitable for the fields of force sensors, pressure sensors, miniature force measurement assemblies and the like.

A method for manufacturing a batch of silicon balance springs from SOI (Silicon On Insulator) plates, designed to keep the value of the resilient torque of the balance springs within a given range. This method includes, in order, the following steps:a—Photolithography and deep reactive ion etching (DRIE) of at least one SOI plate, on which there is at least one balance spring structure and a measurement structure,b—Measuring a parameter of the measurement structure, the value of the measurement parameter being correlated to the value of the resilient torque of the balance spring in a manner known per se,c—Precision adjusting the photolithography and DRIE parameters based on the value of said measurement parameterd—Iterating steps a, b and c so as to continuously control the dissipation of the resilient torque of the balance springs.

[Problem] To provide a method for manufacturing with remarkable speed a silicon substrate having a thick silicon oxide film with a thickness of at least 2 μm and excellent film properties, e.g. hardness, refractive index, and optical transmittance, with low internal stress resulting in reduced warpage and deformation. [Solution] The method includes: a first step of patterning an etching mask for deep trenches on a surface of a silicon substrate; a second step of forming deep trenches in the silicon substrate by using deep reactive ion etching (D-RIE); and a third step of forming a thick silicon oxide film by oxidizing the surface of the silicon substrate in which the deep trenches are formed by a thermal oxidation method, oxidizing all silicon of ridges defined by the deep trenches, and filling the deep trenches with volume-expanding silicon oxide.

The application relates to a method for improving wafer edge damage, and belongs to the technical field of semiconductor manufacturing processes, which solves the problem of silicon needle or silicon spike damage caused by wafer edge silicon substrate exposure during deep reactive ion etching in the preparation of high-voltage element processors. The method for improving wafer edge damage provided by the application comprises the following steps: providing a semiconductor substrate; sequentially forming a stop layer and a first hard mask layer from bottom to top above the substrate, and coating photoresist above the first hard mask layer; removing the photoresist in the edge region and the first hard mask layer directly below the edge region, exposing the stop layer in the edge region, and forming a blank area above the edge stop layer; removing the photoresist reserved above the first hard mask layer, exposing the top surface of the reserved first hard mask layer; and forming a second hard mask layer in the area surrounded by the exposed stop layer in the edge region and the side surface of the first hard mask layer. During deep reactive ion etching, the wafer edge is prevented from being damaged by silicon needles or silicon spikes.

The application discloses a preparation method of a silicon-based adapter plate heterogeneous integrated fan-out SiP packaging module, first, a silicon-based TSV functional adapter plate of a thin film resistor and a thin film capacitor is prepared, passive devices and the silicon-based adapter plate are integrated by oxidation, deep reactive ion etching, insulation layer deposition, seed layer sputtering, copper filling, CMP planarization, double-sided RDL and Ni / Au pad preparation; then, the heterogeneous bare chip PAD is pretreated by electroless nickel plating, ball planting and FC flip to complete the integration of the bare chip and the adapter plate; subsequently, epoxy resin is used for fan-out injection molding and plastic packaging, and then a BGA solder ball lead-out end is made at the bottom of the plastic package body to obtain a finished product. The application integrates passive resistance and capacitance devices in the silicon-based adapter plate, saves an additional device assembly process, improves the connection reliability of the heterogeneous bare chip, realizes shell-free, lead-free and high-density fan-out packaging as a whole, effectively reduces the packaging cost, and can be widely applied to multi-chip system-level integration scenes.