5 results about "Deep reactive-ion etching" patented technology

The application provides an infrared thermoelectric array and a preparation method thereof. The method comprises the following steps: providing a substrate with infrared thermocouples arranged in an array on the front surface; forming a patterned dielectric layer and a release groove etching window on the back surface of the substrate, wherein the dielectric layer comprises an outer dielectric layer and an inner dielectric layer; forming a photoresist layer on the outer dielectric layer; etching the substrate to a first preset depth by deep reactive ion etching through the release groove etching window; removing the inner dielectric layer; and etching the substrate exposed on the inner part of the outer dielectric layer by deep reactive ion etching to form a plurality of bosses arranged in an array. The infrared thermoelectric array prepared by the method has reduced thermal conductivity and reduced risk of film rupture. In addition, the bosses can quickly conduct heat, so that the temperature of the cold junction area is consistent with the ambient temperature. When the bosses are etched, only the side etching of the remaining substrate needs to be considered, which greatly reduces the influence of side etching on the bosses, thereby greatly reducing the size of the bosses and improving the array integration.

This invention discloses a method for fabricating a conical microporous semi-transparent crystalline silicon photovoltaic cell, relating to the field of photovoltaic cells. The method includes the following steps: silicon wafer cleaning and preparation, photolithography to define the micropore pattern, deep reactive ion etching to prepare vertical micropores, micropore tapering treatment, diffusion doping to form a PN junction, alumina passivation layer deposition, post-annealing treatment, silicon nitride antireflection layer deposition, double-sided microgrid electrode fabrication, Low-E film deposition, and module encapsulation. This invention also discloses a conical microporous semi-transparent crystalline silicon photovoltaic cell fabricated using the above method. Through the synergistic design of the conical micropore structure and the selective Low-E film, this invention significantly expands the effective light transmission angle range of incident light without sacrificing the light absorption area, enabling the module to maintain stable light uniformity under different solar illumination angles. This significantly improves the utilization rate of the near-infrared band, reduces the air conditioning cooling load, and achieves a balance between power generation performance and building insulation function.

[Problem] To provide a method for manufacturing with remarkable speed a silicon substrate having a thick silicon oxide film with a thickness of at least 2 μm and excellent film properties, e.g. hardness, refractive index, and optical transmittance, with low internal stress resulting in reduced warpage and deformation. [Solution] The method includes: a first step of patterning an etching mask for deep trenches on a surface of a silicon substrate; a second step of forming deep trenches in the silicon substrate by using deep reactive ion etching (D-RIE); and a third step of forming a thick silicon oxide film by oxidizing the surface of the silicon substrate in which the deep trenches are formed by a thermal oxidation method, oxidizing all silicon of ridges defined by the deep trenches, and filling the deep trenches with volume-expanding silicon oxide.

The application relates to a method for improving wafer edge damage, and belongs to the technical field of semiconductor manufacturing processes, which solves the problem of silicon needle or silicon spike damage caused by wafer edge silicon substrate exposure during deep reactive ion etching in the preparation of high-voltage element processors. The method for improving wafer edge damage provided by the application comprises the following steps: providing a semiconductor substrate; sequentially forming a stop layer and a first hard mask layer from bottom to top above the substrate, and coating photoresist above the first hard mask layer; removing the photoresist in the edge region and the first hard mask layer directly below the edge region, exposing the stop layer in the edge region, and forming a blank area above the edge stop layer; removing the photoresist reserved above the first hard mask layer, exposing the top surface of the reserved first hard mask layer; and forming a second hard mask layer in the area surrounded by the exposed stop layer in the edge region and the side surface of the first hard mask layer. During deep reactive ion etching, the wafer edge is prevented from being damaged by silicon needles or silicon spikes.