7792 results about "Process conditions" patented technology

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V / III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.

A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.

This invention relates to flexible, transparent and conductive coatings and films formed using single wall carbon nanotubes and polymer binders. Preferably, coatings and films are formed from carbon nanotubes (CNT) applied to transparent substrates forming one or multiple conductive layers at nanometer level of thickness. Polymer binders are applied to the CNT network coating having an open structure to provide protection through infiltration. This provides for the enhancement of properties such as moisture resistance, thermal resistance, abrasion resistance and interfacial adhesion. Polymers may be thermoplastics or thermosets, or any combination of both. Polymers may also be insulative or inherently electrical conductive, or any combination of both. Polymers may comprise single or multiple layers as a basecoat underneath a CNT coating, or a topcoat above a CNT coating, or combination of the basecoat and the topcoat forming a sandwich structure. Binder coating thickness can be adjusted by changing binder concentration, coating speed and / or other process conditions. Resulting films and articles can be used as transparent conductors for flat panel display, touch screen and other electronic devices.

Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2 / H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

This invention relates to flexible, transparent and conductive coatings and films formed using carbon nanotubes (CNT) and, in particular, single wall carbon nanotubes, with polymer binders. Preferably, coatings and films are formed from carbon nanotubes applied to transparent substrates forming one or multiple conductive layers at nanometer level of thickness. Polymer binders are applied to the CNT network coating having an open structure to provide protection through infiltration. This provides for enhancement of properties such as moisture resistance, thermal resistance, abrasion resistance and interfacial adhesion. Polymers may be thermoplastics or thermosets, or a combination thereof. Polymers may also be insulative or inherently electrical conductive, or any combination of both. Polymers may comprise single or multiple layers as a basecoat underneath a CNT coating, or a topcoat above a CNT coating, or combination of the basecoat and the topcoat forming a sandwich structure. A fluoropolymer containing binder, which is a solution of one fluoropolymer or a blend of fluoropolymers, which may be formulated with additives, is applied onto a carbon nanotube-based transparent conductive coating at nanometer level of thickness on a clear substrate such as PET and glass. The fluoropolymers or blend can be either semi-crystalline (with low level of crystallinity) or amorphous, preferably to be amorphous with low refraction index. Binder coating thickness can be adjusted by changing binder concentration, coating speed and / or other process conditions. This binder coating significantly improves optical transparency, and also maintain or increases conductivity of the CNT-based coating. With other benefits such as abrasion, thermal and moisture resistance, this binder coating and the resulting products is used for display and electronic applications.

Microfluidic devices with multiple fluid process regions for subjecting similar samples to different process conditions in parallel are provided. One or more common fluid inputs may be provided to minimize the number of external fluid supply components. Solid materials such as chromatographic separation media or catalyst media is preferably provided in each fluid process region. Solid materials may be supplied to the devices in the form of slurry, with particles retained by porous elements or frits. Different fluid process regions may having different effective lengths, different solid material types or amounts, or may receive different ratios of common fluids supplied to the device. The flow resistances of dissimilar fluid process regions may be balanced passively with the addition of impedance elements in series with each fluid process region.

A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

Provided are memory cells including resistive switching layers having silicon, oxygen, and nitrogen as well as embedded resistor layers having a metal, silicon, and nitrogen. In some embodiments, silicon may be partially or completely replaced with aluminum. The embedded resistor may also have oxygen. A resistive switching layer directly interfaces an embedded resistor layer of the same cell. A portion of each layer forming this interface may be formed substantially of silicon nitride and may be formed in the same deposition chamber without breaking vacuum. For example, these portions may be formed by sequential atomic layer deposition cycles. However, silicon concentrations in these portions may be different. Specifically, the silicon concentration of the embedded resistor portion may be less than the silicon concentration of the resistive switching layer portion. This variation may be achieved by varying one or more process conditions during fabrication of the memory cell.

The present invention provides an upper electrode used in an etching apparatus and the etching apparatus including the upper electrode, both of which can properly reduce intensity of electric field of plasma around a central portion of a substrate to be processed, thus enhancing in-plane uniformity of a plasma process. In this apparatus, a recess, serving as a space for allowing a dielectric to be injected therein, is provided around a central portion of the upper electrode. A dielectric supply passage configured for supplying the dielectric into the space and a dielectric discharge passage configured for discharging the dielectric from the space are connected with the space, respectively. With such configuration, the dielectric can be controllably supplied into the recess, such that in-plane distribution of the intensity of the electric field can be uniformed, corresponding to in-plane distribution of the intensity of the electric field of the plasma generated under various process conditions, such as a kind of each wafer that will be etched, each processing gas that will be used, and the like.

Thermally-stable polycrystalline diamond materials of this invention comprise a first phase including a plurality of bonded together diamond crystals, and a second phase including a reaction product formed between a binder / catalyst material and a material reactive with the binder / catalyst material. The reaction product is disposed within interstitial regions of the polycrystalline diamond material that exists between the bonded diamond crystals. The first and second phases are formed during a single high pressure / high temperature process condition. The reaction product has a coefficient of thermal expansion that is relatively closer to that of the bonded together diamond crystals than that of the binder / catalyst material, thereby providing an improved degree of thermal stability to the polycrystalline diamond material.

Disclosed are interfacially modified particulate and polymer composite material for use in injection molding processes, such as metal injection molding and additive process such as 3D printing. The composite material is uniquely adapted for powder metallurgy processes. Improved products are provided under process conditions through surface modified powders that are produced by extrusion, injection molding, additive processes such as 3D printing, Press and Sinter, or rapid prototyping.

Thermally-stable polycrystalline diamond materials of this invention comprise a first phase including a plurality of bonded together diamond crystals, and a second phase including a reaction product formed between a binder / catalyst material and a material reactive with the binder / catalyst material. The reaction product is disposed within interstitial regions of the polycrystalline diamond material that exists between the bonded diamond crystals. The first and second phases are formed during a single high pressure / high temperature process condition. The reaction product has a coefficient of thermal expansion that is relatively closer to that of the bonded together diamond crystals than that of the binder / catalyst material, thereby providing an improved degree of thermal stability to the polycrystalline diamond material.

A method and processing tool are provided for trimming a gate electrode structure containing a gate electrode layer with a first dimension. A reaction layer is formed through reaction with the gate electrode structure. The reaction layer is the selectively removed from the unreacted portion of the gate electrode structure by chemical etching, thereby forming a trimmed gate electrode structure with a second dimension that is smaller than the first dimension. The trimming process can be carried out under process conditions where formation of the reaction layer is substantially self-limiting. The trimming process can be repeated to further reduce the dimension of the gate electrode structure.

The present invention relates to a selectively soluble polymer capable of binding to a desired biomolecules in a mixture containing various biological materials and the methods of using such a polymer to purify a biomolecule from such a mixture. The polymer is soluble in the mixture under a certain set of process conditions such as pH or temperature and / or salt concentration and is rendered insoluble and precipitates out of solution upon a change in the process conditions. The polymer is capable of binding to the desired biomolecule (protein, polypeptide, etc) and remains capable of binding to that biomolecule even after the polymer is precipitated out of solution. The precipitate can then be filtered out from the remainder of the stream and the desired biomolecule is recovered such as by elution and further processed.

A process for drawing essentially diluent-free gel-spun polyethylene multi-filament yarns in a forced convection air oven and the drawn yarns produced thereby, The process conditions of draw ratio, stretch rate, residence time, oven length and feed speed are selected in specific relation to one another so as to achieve enhanced efficiency and productivity. The drawn yarns are useful in armor, composites, fishing line, ropes, sutures, fabrics and other applications.

Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V / III ratio in a range of from about 1 to about 10<5>, nitrogen source material partial pressure in a range of from about 1 to about 10<3 >torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10<2 >microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

A method and apparatus for catalytic production of carbon nanotubes. Catalytic particles are exposed to different process conditions at successive stages wherein the catalytic particles do not come in contact with reactive (catalytic) gases until preferred process conditions have been attained, thereby controlling the quantity and form of carbon nanotubes produced. The method also contemplates methods and apparatus which recycle and reuse the gases and catalytic particulate materials, thereby maximizing cost efficiency, reducing wastes, reducing the need for additional raw materials, and producing the carbon nanotubes, especially SWNTs, in greater quantities and for lower costs.

The invention relates to a modified molecular sieve capable of improving coking performance. The modified molecular sieve is prepared from a NaY type molecular sieve by the twice-crosslinking twice-roasting preparation method. According to the weight ratio, in the modified molecular sieve, the content of RE2O3 is 0.05 to 4 percent, the content of P is 0.05 to 5.0 percent; and the crystal cell of the modified molecular sieve is 2.430 to 2.440nm, and the crystallinity is between 35 and 55 percent. The modified molecular sieve has bigger hole volume of medium-and-large-sized holes and good stability; under the same condition of preparation process for catalyst, compared with the comparison molecular sieve, the modified molecular sieve has the advantages of reducing coke yield of the catalyst, simultaneously further improving the heavy oil cracking capability, further improving total liquid yield, and particularly facilitating the improvement of the yield of light oil.

Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

Embodiments of the present invention overcome the well-known recalcitrance of lignocellulosic biomass in an economically viable manner. A process and system are provided for the efficient fractionation of lignocellulosic biomass into cellulose, hemicellulose sugars, lignin, and acetic acid. The cellulose thus obtained is highly amorphous and can be readily converted into glucose using known methods. Fermentable hemicellulose sugars, low-molecular—weight lignin, and purified acetic acid are also major products of the process and system. The modest process conditions and low solvent / solid ratios of some embodiments of the invention imply relatively low capital and processing costs.

The invention is a sterilizing apparatus that reads information from an information recording section provided in an endoscope, sets a sterilizing process condition for sterilizing the endoscope on the basis of the read information, and controls a sterilizing process in accordance with the sterilizing process condition that is set.

A process control method to monitor ion implantation process conditions by measuring the optical properties of a masking material is provided. A patterned masking material may protect underlying regions of a semiconductor substrate from undergoing a chemical or physical change during an ion implantation process. The patterned masking material, however, may also undergo a chemical or physical change during processing. The chemical or physical changes to the masking material during such processing may also cause the optical properties of the material to change. The optical properties of the masking material may be used to determine the concentration of ions implanted into the semiconductor substrate.

A method of selecting a sensor in a semiconductor manufacturing process is provided. The method includes measuring responses of a plurality of sensors when a first of a plurality of process conditions is varied, identifying one or more of the sensors having a steady state response after the first of the process conditions is varied, and selecting a sensor having a highest value within a response range from among the sensors having the steady state response for the first process condition that is varied. This methodology may be performed for multiple different process conditions. Thus, when process conditions in multiple processes of manufacturing a semiconductor device are varied, sensors having a steady state response can be selected from among multiple sensors for detecting abnormalities in the processes.

The invention relates to a method for modifying a USY (Ultra-Stable Y) molecular sieve. The method is characterized in that organic acid and an inorganic salt dealuminizing reagent are simultaneously added in a modifying process for organic acid-inorganic salt combined modification, and optimum process conditions, namely optimum concentration, volume ratio, reaction time, reaction temperature and the like, of an organic acid and an inorganic salt solution are determined by virtue of an orthogonal test. Compared with an industrial USY molecular sieve, the USY molecular sieve obtained by adopting the method disclosed by the invention is obviously increased in secondary pore content, can be kept at higher crystallinity and is enhanced in silica-alumina ratio, reduced in lattice constant and suitable for high-medium oil type hydrocracking catalyst carriers.

Novel iron and cobalt complexes of certain novel tricyclic ligands containing a “pyridine” ring and substituted with two imino groups are polymerization and / or oligomerization catalysts for olefins, especially ethylene. Depending on the exact structure of the ligand, and polymerization process conditions, products ranging from α-olefins to high polymers may be produced. The polymers, especially polyethylenes, are useful for films and as molding resins.

The invention relates to a selective hydrogenation method of high unsaturated hydrocarbons in C4 fractions, which is characterized in that salvage stores which are rich in acetylene hydrocarbon and prepared by extracting butadiene are used as the material, and a fixed bed reactor is adopted to obtain 1, 3-budiene by selective hydrogenation under the existence of a catalyst. The adopted process conditions are as follows: the reaction temperature is between 30 DEG C and 90 DEG C, the reaction pressure is between 1.0 MPa and 4.0 MPa and the liquid space velocity is 7 to 20h<-1>. The catalyst is preferably a palladium system catalyst with alumina as a carrier, the specific surface is 50 to 150m<2> / g and the specific pore volume is 0.25 to 1.0ml / g. The method has remarkable good effects on reducing waste of resources and improving economic benefits by effectively utilizing the salvage stores rich in acetylene hydrocarbon and prepared by extracting butadiene.