213 results about "Resistive switching" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention relates to the technical field of electronic devices, in particular to a synaptic memristive device with a vertical structure and a preparation method and application of the synaptic memristive device. The invention provides a synaptic memristor with a vertical structure. The synaptic memristor structurally comprises a substrate, a bottom electrode, an active layer, an electrolyte layer and a top electrode which are stacked in sequence. Wherein the active layer is a vanadium pentoxide film which is excellent in electrical property and optical response, and the sensitivity and plasticity of the device can be improved; the electrolyte layer adopts polyethylene oxide ionic glue, so that the resistance change characteristic of the active layer can be adjusted, the reaction between the active layer and the top electrode can be prevented, and the service life of the device is prolonged; the bottom electrode is an indium tin oxide thin film, has good compatibility with an active layer interface, can promote oxygen vacancy migration, and optimizes the resistance switching performance. Through mutual coordination of the materials, the device can generate microampere-level current under millivolt-level stimulation, shows high-sensitivity synaptic plasticity, and is suitable for a high-performance neuromorphic computing system.

An adaptive IGBT active drive circuit is divided into two parts: a gate drive circuit, and a feedback circuit. The gate drive circuit includes a totem pole unit, and multi-level resistance switching is achieved by using a totem pole parallel structure. The feedback circuit includes a comparison unit, and a logic unit. The comparison unit includes divided resistors, sampling resistors, and a comparator. Internal currents, after passing through the sampling resistor, are compared with current comparison thresholds of complementary transistors to output a digital signal to participate in control of the totem pole. The logic unit is responsible for logically combining a PWM signal and a signal output by the comparison unit to obtain a driving signal of the totem pole.

The invention relates to the field of semiconductor device preparation, and provides a method for preparing a resistive layer of a variable resistance type memory based on laser pulse, which comprises the following steps: depositing a buffer layer on a bottom electrode layer of a pre-prepared variable resistance type memory, the material of the buffer layer comprising any one or more of tungsten, tantalum, nitrogen and boron; depositing a seed layer on the buffer layer; a target material is shot based on laser pulse shock, the target material is deposited on the seed layer to form a resistive layer, and the target material comprises any one or more of scandium, titanium, strontium, yttrium, lanthanum and barium and aluminum nitride. The method and the device are used for solving the defect of low read-write speed of the variable resistance type memory in the related technology, and the read-write speed of the variable resistance type memory can be improved based on preparation of the resistive layer by using aluminum nitride.

The utility model discloses a novel IGBT (Insulated Gate Bipolar Translator) driving circuit, which comprises a driving signal control module, a grid voltage monitoring and logic processing module and a triode driving and resistance switching module, the grid voltage monitoring and logic processing module comprises a grid voltage, a first signal comparator and a second signal comparator which are connected with the grid voltage, a turn-on threshold voltage connected with the first signal comparator, a Miller platform voltage connected with the second signal comparator, and a gate voltage monitoring and logic processing module connected with the turn-on threshold voltage and the Miller platform voltage. The logic gate circuit is connected with the first signal comparator and the second signal comparator; the triode driving and resistor switching module comprises a turn-on triode group, a turn-on resistor assembly connected with the turn-on triode group, a turn-off triode group, and a turn-off resistor assembly connected with the turn-off triode group. The IGBT is quickly turned on and reliably turned off, and the dead time is reduced.

The invention provides an insulation resistance testing method, which comprises the following steps of: when detecting that each switch in all resistance switching structures is switched off, acquiring initial sampling voltages at two ends of a negative electrode ground insulation resistor RN and a positive electrode ground insulation resistor RP; if the initial sampling voltage of the RP is greater than or equal to the initial sampling voltage of the RN, determining a first switching sequence corresponding to each switch in a resistor switching structure connected to the two ends of the RP in parallel after resistors connected with the switches are arranged from large to small according to resistance values; sequentially performing closing operation on the corresponding switches and detecting the sampling voltage at the two ends of the RN after the operation until the sampling voltage at the two ends of the RN is greater than the offset voltage threshold value; and the resistors correspondingly connected in parallel at the two ends of the RP and the resistance values of the resistors are obtained, and the sizes of the RP and the RN are calculated by combining the voltage of the power supply UBAT, the initial sampling voltages of the RP and the RN, the last sampling voltage of the RN and the resistance values of the sampling resistors R3-R5. According to the invention, the resistance detection result can be improved.

The invention discloses a power device driving circuit of a motor controller, a control method and a vehicle. The power device driving circuit comprises a gate resistance control module which selectively switches gate resistors of a power device according to a control signal, and switching speeds of the power device are different when the gate resistors are switched to different gate resistors; the detection processing circuit collects the phase current of the motor controller, generates a control signal according to the phase current and a preset voltage reference signal, and sends the control signal to the gate resistance control module; and the isolation driving module is used for sending a driving signal to the power device so as to drive the power device to be switched on and switched off at the corresponding switching speed. According to the invention, the method can effectively improve the efficiency of small current output, can effectively protect the peak and oscillation of a power device during large current output, achieves the real-time switching, is higher in response speed, enables the switching operation to be decomposed into each current period, and is more effective for reducing the loss and protecting the device.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

The invention provides a circuit for automatically adjusting magnification times and realizing synchronous sampling, and belongs to the technical field of power electronics. The circuit comprises an amplifying circuit, a resistance switching circuit, a phase locking circuit and an acquisition circuit, the amplifying circuit is used for receiving and processing an original signal, obtaining a voltage signal and analyzing an amplification factor required by the voltage signal, and an amplifier is correspondingly connected to a resistor in the resistance switching circuit according to the required amplification factor and is used for acquiring the voltage signal. And amplifying the voltage signal according to the amplification factor, receiving the amplified voltage signal by the phase-locked loop, analyzing the amplified voltage signal to obtain an average voltage, and adjusting the output frequency of the phase-locked loop according to the average voltage to lock the phase. And the acquisition circuit is used for synchronously sampling the amplified voltage signal according to the locked phase. In an electric power system data acquisition application, the amplification factor can be automatically adjusted, phase synchronization can be realized, and signal acquisition and data analysis of different capacitive devices of a power grid can be satisfied.

The invention relates to a memristor and a preparation method thereof. The preparation method comprises the following steps: providing an insulating substrate with a bottom electrode formed on the surface; depositing an aluminum oxide thin film on the bottom electrode by adopting electron beam evaporation under a room temperature condition to form a resistive function layer, and not performing high-temperature annealing treatment after deposition is completed, so that a primary oxygen vacancy defect is reserved in the thin film; and then depositing a top electrode on the resistive function layer through thermal evaporation or electron beam evaporation to obtain the memristor. The resistive function layer is an aluminum oxide film which is not densified through annealing, and internal defects of the resistive function layer provide a channel for metal ion migration, so that the reversible resistive characteristic is achieved. The memristor device is simple in structure and suitable for normal-temperature process preparation, the stable resistance switching behavior can be achieved, excessive densification of a film layer and thermal damage of an ITO electrode interface caused by high-temperature annealing are avoided, and the memristor has high cycle durability and nonvolatile data retention capacity and has the stable bipolar resistance change characteristic.

The invention discloses new energy automobile charging safety inspection metering calibration equipment and a control method thereof. The equipment comprises a direct current charging metering calibration module, an insulation resistance calibration module and a potential equalization calibration module, the DC charging metering calibration module comprises a DC charging gun base, a BMS simulator, a high-precision ammeter and a high-precision voltmeter. The insulation resistance calibration module comprises a main control unit, a high-precision resistor, a high-voltage switching unit and an alternating-current charging gun base, the potential equalization calibration module comprises a high-precision galvanometer, a high-precision voltage source and a low-voltage switching unit, and the low-voltage switching unit comprises a low-voltage relay set, a first banana head interface and a second banana head interface. The AC charging gun base is connected to the calibration circuit through the low-voltage relay group. By integrating the high-precision measurement module, the resistance switching unit and the BMS simulator, one-key calibration of direct-current charging, insulation resistance and potential equalization is realized, and the problems of contact resistance interference and multi-instrument collaboration are solved.

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first bottom electrode with a first feature size and a second bottom electrode with a second feature size, and the first feature size is greater than the second feature size; a first resistive switching layer and a second resistive switching layer; a first top electrode with a third feature size and a second top electrode with a fourth feature size, and the third feature size is greater than the fourth feature size; wherein a vertical projection of the first bottom electrode and a vertical projection of the first top electrode at least partially overlap to form a first overlapping area, and the first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping area constitute an erasable memristor; a vertical projection of the second bottom electrode and a vertical projection of the second top electrode at least partially overlap to form a second overlapping area, and the second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping area constitute a non-erasable memristor.

A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

The present application belongs to the technical field of nanoelectronic devices, and provides an integrated gas sensing-computing synaptic device and a preparation method therefor. The device comprises: a first functional layer, a barrier layer, a second functional layer, a first metal electrode, and a second metal electrode; the first functional layer is heavily doped silicon; the second functional layer uses CuOx material, such that defect energy levels are formed by interstitial oxygen and copper vacancies; the barrier layer increases contact area between the second functional layer and a test gas; a direct current voltage scan is applied between the first metal electrode and the second metal electrode, to simulate resistive switching behavior of a memristor; the second functional layer reacts with the test gas, to implement a gas sensing function; a constant voltage signal is applied between the first metal electrode and the second metal electrode, and in a gas pulse environment, a current response state exhibits a synaptic response. The present application can implement in-situ sensing and processing of gas information, improving information processing efficiency, and the gas information inference method of the integrated gas sensing-computing device is simpler.

A method for manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a resistive switching film in the substrate; forming a first electrode and a second electrode on opposite sides of the resistive switching film.

The invention discloses a switched capacitor resistance improvement method, and belongs to the field of analog integrated circuits. When the conduction is reduced, the NMOS tube is used as a switch, and the gate end voltage of the switch is reduced from the power supply voltage VDD until the gate end voltage is close to the threshold voltage or even lower than the threshold voltage; when a PMOS (P-channel Metal Oxide Semiconductor) tube is used as a switch, the gate end voltage of the switch is increased from the ground GND until the gate end voltage is close to the threshold voltage or even higher than the threshold voltage. According to the invention, the low conduction voltage is adopted to carry out switch resistance switching, the generated channel charge is reduced, and the charge accumulated to the input / output end is correspondingly reduced. The threshold value of the switch MOS tube is correspondingly changed due to the conversion of the process corner and the temperature, and if the MOS tube is used as a switch, the MOS tube with the same size can be used for forming a diode connection method to form the switch voltage.

A method includes forming a transistor over a substrate; and forming a resistive element over the transistor, in which forming the resistive element includes forming a bottom electrode electrically connected to a source / drain region of the transistor; forming a resistive switching layer over the bottom electrode, in which the resistive switching layer is made of metal halide; and forming a top electrode over the resistive switching layer.

A memory device with hard mask insulator and its manufacturing methods are provided. In some embodiments, the memory device includes a memory cell stack disposed over a substrate. The memory cell stack includes a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is disposed over the top electrode layer, and a first metal hard masking layer disposed over the first insulating layer.

The invention discloses a synaptic memory cell for neuromorphic calculation, a preparation method and a synaptic array, the synaptic memory cell comprises two gating transistors and two resistance change memristors, and the gating transistors and the resistance change memristors are in one-to-one correspondence connection; the gate transistor comprises a grid electrode, a dielectric layer and a channel layer which are sequentially arranged from bottom to top, and a source electrode and a drain electrode which are arranged on the surface of the channel layer, and a first passivation layer is arranged between the source electrode and the drain electrode; the channel layer is made of hydrogenated amorphous silicon; the resistance change memristor comprises a bottom electrode, a resistance change layer and a top electrode which are sequentially arranged on the drain electrode, and a second passivation layer which is arranged on the surface of the drain electrode and the surface of the first passivation layer; the resistive layer is a hexagonal boron nitride film; and the two resistive memristors are connected with each other through a metal layer arranged on the surface of the top electrode. According to the invention, low-temperature process compatibility is realized, so that three-dimensional stacking integration is facilitated, and the conductivity fluctuation coefficient is remarkably reduced.

The application belongs to the technical field of microelectronic devices, and particularly relates to a nonvolatile FeOOH / TiO2 heterojunction memristor and a preparation and multi-value storage control method thereof. The nonvolatile FeOOH / TiO2 heterojunction memristor comprises a bottom electrode, a TiO2 resistive switching layer and a FeOOH resistive switching layer which are epitaxially grown on the bottom electrode in sequence, and an upper electrode deposited on the surface of the FeOOH resistive switching layer. The preparation method comprises the following steps: placing a bottom electrode substrate with a conductive surface downward in a water heating reaction kettle inner container, adding a reaction solution prepared by tetrabutyl titanate, keeping part of the bottom electrode substrate higher than the reaction solution surface, sealing, and placing in a muffle furnace for water heating reaction; obtaining a TiO2 / bottom electrode sample; placing an epitaxial growth surface downward in the water heating reaction kettle inner container, adding a reaction solution of FeCl3.6H2O, sealing, and placing in a muffle furnace for water heating reaction to obtain a required FeOOH / TiO2 / bottom electrode heterojunction sample; and depositing an upper electrode with a certain thickness and morphology on the surface. The application provides a low-cost and high-density nonvolatile FeOOH / TiO2 heterojunction memristor.

The random-access resistive storage device comprises a first ILD layer on a substrate; a first interconnect structure within the first ILD layer; a capping layer on the first interconnect structure and the first ILD layer; a dielectric intermediate layer on the capping layer; a conductive via in the capping layer and the dielectric intermediate layer; and a resistive switching element on the conductive via. The resistive switching element comprises a bottom electrode layer, a top electrode layer, and a resistive switching material layer located between the top electrode layer and the bottom electrode layer. A hard mask layer is placed on the resistive switching element. A second interconnect structure is placed on the hard mask layer and the resistive switching element.The second interconnect structure comprises a flange section that is in direct contact with an upper side wall of the top electrode layer of the resistive switching element.

The application discloses a water-soluble polymer-based proton-type memristor and a preparation method thereof. The memristor has a sandwich structure and is sequentially composed of a top electrode, an inorganic resistive switching functional layer, an organic resistive switching functional layer and a bottom electrode. The top electrode is a metal active electrode, the bottom electrode is indium tin oxide (ITO), the inorganic resistive switching functional layer is a metal oxide film, and the organic resistive switching functional layer is a doping system composed of a water-soluble polymer and a doping material. The preparation process of the proton-type memristor is reliable and stable. The obtained memristor has the characteristics of high biocompatibility and green environmental protection. The device performance consistency and environmental dependence are improved, and the simulation of bionic synaptic plasticity is greatly improved. The device can be controlled by using a low voltage, has low power consumption, and has a good bidirectional current modulation effect, so that the device provides a possibility for further enriching synaptic functions and designing flexible wearable devices.

The application discloses a preparation method of a multifunctional self-selecting memristor based on a composite structure and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The self-selecting memristor prepared by adopting the method has both volatile and nonvolatile resistive switching performances, and can realize the conversion from volatility to nonvolatility by changing electrical operation conditions. When the self-selecting memristor works in a volatile region, the self-selecting characteristic and short-range plasticity ability with high consistency are maintained; and when the self-selecting memristor works in a nonvolatile region, the self-selecting memristor has the advantages of low power consumption and a relatively large adjustable interval, and can maintain a storage state. The application has wide application potential in data storage and online learning scenes, and can realize efficient weight update and improve storage performance.

The present invention discloses a true random number generator based on a photoelectrically controlled memristor and a preparation method. The true random number generator comprises: a photoelectrically controlled memristor, an illumination control module, a pulse generation module, and a monitoring module. The illumination control module is configured to provide illumination to the photoelectrically controlled memristor under the control of the monitoring module. The pulse generation module is configured to provide a preset pulse signal to the photoelectrically controlled memristor. When illumination is present or illumination meets preset conditions, the photoelectrically controlled memristor generates random numbers based on the preset pulse signal, using the on / off state of the conductive channel in the resistive switching layer as a random entropy source. When illumination is absent or illumination does not meet the preset conditions, random number generation ceases. The monitoring module monitors the random numbers output by the photoelectrically controlled memristor and, if the same random number is output multiple times in a row, sends a control signal to the illumination control module to cause it to turn off illumination or provide illumination that does not meet the preset conditions. The present invention can implement self-testing and on / off control of the true random number generator.

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer between the first and second conductive layers; a switching layer between the first and third conductive layers; and a resistive switching layer between the third and second conductive layers. The switching layer comprises an oxide, nitride, or oxynitride of a first element selected from the group consisting of Al, Si, Ge, Zr, Y, Ta, La, Ce, Ti, Hf, and Mg; a second element, different from the first element, selected from the group consisting of Al, Zn, Sn, Ga, and In; and a third element selected from the group consisting of Te, S, Se, and Sb. The switching layer includes a first region and a second region, wherein the sum of the atomic concentrations of the second element and the third element in the first region is greater than the sum of the atomic concentrations of the second element and the third element in the second region.

A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

To reduce writing time while suppressing element destruction of a resistance change element upon performing writing operation which changes a resistance state of the resistance change element.SOLUTION: In a write current path 30, a resistance change element R0 and a write transistor M0 are connected in series between a write voltage Vw and a ground voltage VSS, and a write current Iw for performing write operation flows. In a replica current path 20, a drain terminal of a replica write transistor MR0 with substantially the same properties as those of the write transistor M0 is connected to a current source 12, a source terminal of the replica write transistor MR0 is connected to the ground voltage VSS, and a replica current Iwr set based on a current value of the write current Iw flows. In a differential amplifier 11, the write voltage Vw is connected to an inverted input terminal, a voltage of an output terminal of the current source 12 is connected to a non-inverted input terminal, and a control voltage Vb from the output terminal is supplied to each of gate terminals of the write transistor M0 and the replica write transistor MR0.SELECTED DRAWING: Figure 5

Methods for manufacturing a memory cell, comprising: Forming a memory cell stack (204) over a substrate (102), wherein the memory cell stack (204) has a lower electrode layer (1002), a resistive switching dielectric layer (1004) over the lower electrode layer (1002) and an upper electrode layer (1006) over the resistive switching dielectric layer (1004); Forming a first insulating layer (1108) over the upper electrode layer (1006); Forming a first metal hard mask layer (1110) over the first insulating layer (1108); and Performing an etching series to structure the first metal hard mask layer (1110), the first insulating layer (1108), the upper electrode layer (1006) and the resistance switching dielectric layer (1004) to form a first metal hard mask (1110), a hard mask insulator (120), an upper electrode (118) and a resistance switching dielectric (116); Furthermore, comprehensively, before carrying out the etching series: Forming a second insulating layer (1112) over the first metal hard mask layer (1110); and Forming a second metal hard mask layer (1114) over the second insulating layer (1112).

The present invention discloses a resistive random access memory (RRAM) with adjustable operating voltage and a preparation method thereof, which includes a substrate, a bottom electrode, a resistive switching layer, and a top electrode arranged in sequence from bottom to top. The resistive switching layer is a Ta2O5 thin film doped with W, with a thickness of 40 - 120 nm. The top electrode and the bottom electrode are made of metal W and Pt respectively, and the substrate material is Ti / SiO2 / Si. In the present invention, the Ta2O5 is doped with W element, and the formation energy and diffusion barrier energy of oxygen vacancies in Ta2O5 are changed by doping, so as to change the diffusion activation energy of oxygen vacancies, realize the regulation of the diffusion activation energy of oxygen vacancies, and further regulate the operating voltage of the device, so as to achieve the purpose of controlling the operating voltage of the RRAM device.

The invention provides a non-linear self-rectification resistive random access memory. The non-linear self-rectification resistive random access memory comprises a first electrode layer, a first resistive random layer, a second resistive random layer and a second electrode layer, specifically, a first potential barrier is formed on the contact surface of the first electrode layer and the first resistive layer, and a second potential barrier different from the first potential barrier is formed on the contact surface of the second electrode layer and the second resistive layer. Wherein the first potential barrier and the second potential barrier are used for forming an operation current between the first electrode layer and the second electrode layer under the condition that an operation voltage applied through the first electrode layer and the second electrode layer is at a first voltage; when the operating voltage is in the second voltage range, the operating current is rectified to hinder transmission of the operating current between the first electrode layer and the second electrode layer. The invention also provides a manufacturing method of the resistive random access memory.