106 results about "Resistive switching" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention relates to a memristor and a preparation method thereof. The preparation method comprises the following steps: providing an insulating substrate with a bottom electrode formed on the surface; depositing an aluminum oxide thin film on the bottom electrode by adopting electron beam evaporation under a room temperature condition to form a resistive function layer, and not performing high-temperature annealing treatment after deposition is completed, so that a primary oxygen vacancy defect is reserved in the thin film; and then depositing a top electrode on the resistive function layer through thermal evaporation or electron beam evaporation to obtain the memristor. The resistive function layer is an aluminum oxide film which is not densified through annealing, and internal defects of the resistive function layer provide a channel for metal ion migration, so that the reversible resistive characteristic is achieved. The memristor device is simple in structure and suitable for normal-temperature process preparation, the stable resistance switching behavior can be achieved, excessive densification of a film layer and thermal damage of an ITO electrode interface caused by high-temperature annealing are avoided, and the memristor has high cycle durability and nonvolatile data retention capacity and has the stable bipolar resistance change characteristic.

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first bottom electrode with a first feature size and a second bottom electrode with a second feature size, and the first feature size is greater than the second feature size; a first resistive switching layer and a second resistive switching layer; a first top electrode with a third feature size and a second top electrode with a fourth feature size, and the third feature size is greater than the fourth feature size; wherein a vertical projection of the first bottom electrode and a vertical projection of the first top electrode at least partially overlap to form a first overlapping area, and the first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping area constitute an erasable memristor; a vertical projection of the second bottom electrode and a vertical projection of the second top electrode at least partially overlap to form a second overlapping area, and the second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping area constitute a non-erasable memristor.

A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

The present application belongs to the technical field of nanoelectronic devices, and provides an integrated gas sensing-computing synaptic device and a preparation method therefor. The device comprises: a first functional layer, a barrier layer, a second functional layer, a first metal electrode, and a second metal electrode; the first functional layer is heavily doped silicon; the second functional layer uses CuOx material, such that defect energy levels are formed by interstitial oxygen and copper vacancies; the barrier layer increases contact area between the second functional layer and a test gas; a direct current voltage scan is applied between the first metal electrode and the second metal electrode, to simulate resistive switching behavior of a memristor; the second functional layer reacts with the test gas, to implement a gas sensing function; a constant voltage signal is applied between the first metal electrode and the second metal electrode, and in a gas pulse environment, a current response state exhibits a synaptic response. The present application can implement in-situ sensing and processing of gas information, improving information processing efficiency, and the gas information inference method of the integrated gas sensing-computing device is simpler.

A method for manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a resistive switching film in the substrate; forming a first electrode and a second electrode on opposite sides of the resistive switching film.

A method includes forming a transistor over a substrate; and forming a resistive element over the transistor, in which forming the resistive element includes forming a bottom electrode electrically connected to a source / drain region of the transistor; forming a resistive switching layer over the bottom electrode, in which the resistive switching layer is made of metal halide; and forming a top electrode over the resistive switching layer.

The invention discloses a synaptic memory cell for neuromorphic calculation, a preparation method and a synaptic array, the synaptic memory cell comprises two gating transistors and two resistance change memristors, and the gating transistors and the resistance change memristors are in one-to-one correspondence connection; the gate transistor comprises a grid electrode, a dielectric layer and a channel layer which are sequentially arranged from bottom to top, and a source electrode and a drain electrode which are arranged on the surface of the channel layer, and a first passivation layer is arranged between the source electrode and the drain electrode; the channel layer is made of hydrogenated amorphous silicon; the resistance change memristor comprises a bottom electrode, a resistance change layer and a top electrode which are sequentially arranged on the drain electrode, and a second passivation layer which is arranged on the surface of the drain electrode and the surface of the first passivation layer; the resistive layer is a hexagonal boron nitride film; and the two resistive memristors are connected with each other through a metal layer arranged on the surface of the top electrode. According to the invention, low-temperature process compatibility is realized, so that three-dimensional stacking integration is facilitated, and the conductivity fluctuation coefficient is remarkably reduced.

The application belongs to the technical field of microelectronic devices, and particularly relates to a nonvolatile FeOOH / TiO2 heterojunction memristor and a preparation and multi-value storage control method thereof. The nonvolatile FeOOH / TiO2 heterojunction memristor comprises a bottom electrode, a TiO2 resistive switching layer and a FeOOH resistive switching layer which are epitaxially grown on the bottom electrode in sequence, and an upper electrode deposited on the surface of the FeOOH resistive switching layer. The preparation method comprises the following steps: placing a bottom electrode substrate with a conductive surface downward in a water heating reaction kettle inner container, adding a reaction solution prepared by tetrabutyl titanate, keeping part of the bottom electrode substrate higher than the reaction solution surface, sealing, and placing in a muffle furnace for water heating reaction; obtaining a TiO2 / bottom electrode sample; placing an epitaxial growth surface downward in the water heating reaction kettle inner container, adding a reaction solution of FeCl3.6H2O, sealing, and placing in a muffle furnace for water heating reaction to obtain a required FeOOH / TiO2 / bottom electrode heterojunction sample; and depositing an upper electrode with a certain thickness and morphology on the surface. The application provides a low-cost and high-density nonvolatile FeOOH / TiO2 heterojunction memristor.

The application discloses a water-soluble polymer-based proton-type memristor and a preparation method thereof. The memristor has a sandwich structure and is sequentially composed of a top electrode, an inorganic resistive switching functional layer, an organic resistive switching functional layer and a bottom electrode. The top electrode is a metal active electrode, the bottom electrode is indium tin oxide (ITO), the inorganic resistive switching functional layer is a metal oxide film, and the organic resistive switching functional layer is a doping system composed of a water-soluble polymer and a doping material. The preparation process of the proton-type memristor is reliable and stable. The obtained memristor has the characteristics of high biocompatibility and green environmental protection. The device performance consistency and environmental dependence are improved, and the simulation of bionic synaptic plasticity is greatly improved. The device can be controlled by using a low voltage, has low power consumption, and has a good bidirectional current modulation effect, so that the device provides a possibility for further enriching synaptic functions and designing flexible wearable devices.

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer between the first and second conductive layers; a switching layer between the first and third conductive layers; and a resistive switching layer between the third and second conductive layers. The switching layer comprises an oxide, nitride, or oxynitride of a first element selected from the group consisting of Al, Si, Ge, Zr, Y, Ta, La, Ce, Ti, Hf, and Mg; a second element, different from the first element, selected from the group consisting of Al, Zn, Sn, Ga, and In; and a third element selected from the group consisting of Te, S, Se, and Sb. The switching layer includes a first region and a second region, wherein the sum of the atomic concentrations of the second element and the third element in the first region is greater than the sum of the atomic concentrations of the second element and the third element in the second region.

A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

To reduce writing time while suppressing element destruction of a resistance change element upon performing writing operation which changes a resistance state of the resistance change element.SOLUTION: In a write current path 30, a resistance change element R0 and a write transistor M0 are connected in series between a write voltage Vw and a ground voltage VSS, and a write current Iw for performing write operation flows. In a replica current path 20, a drain terminal of a replica write transistor MR0 with substantially the same properties as those of the write transistor M0 is connected to a current source 12, a source terminal of the replica write transistor MR0 is connected to the ground voltage VSS, and a replica current Iwr set based on a current value of the write current Iw flows. In a differential amplifier 11, the write voltage Vw is connected to an inverted input terminal, a voltage of an output terminal of the current source 12 is connected to a non-inverted input terminal, and a control voltage Vb from the output terminal is supplied to each of gate terminals of the write transistor M0 and the replica write transistor MR0.SELECTED DRAWING: Figure 5

The present disclosure relates to a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a substrate; a first conductive structure disposed on the substrate; a memory cell disposed on a side of the first conductive structure away from the substrate, the memory cell including a first electrode layer, a first functional layer, a second functional layer, and a second electrode layer sequentially stacked in a direction away from the substrate, the memory cell forming a second hole above the first conductive structure, an opening direction of the second hole facing away from the substrate, and one of the first functional layer and the second functional layer being a selector layer, and the other being a resistive switching layer.

The problem of reducing the formation voltage for an RRAM cell is solved with a resistance switching structure having at least two different layers. The thickness and composition of the layers are selected such that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing durability is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the low oxygen affinity layer. The lower oxygen affinity layer may have a laminated structure in which dopant metals are disposed in different levels. The embodiment of the invention also relates to an integrated chip and a manufacturing method thereof.

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the second electrode, an upper surface of the resistive switching film and an upper surface of the first metal layer are coplanar.

The problem of reducing the formation voltage in an RRAM cell is solved by a resistance switching structure having different layers of at least two different metal oxides. The thickness and composition of the layers are selected such that a difference in oxygen affinity between the layers produces intrinsic oxygen vacancies in one of the layers. The problem of increasing durability is solved by adding a dopant metal to the lower oxygen affinity layer. The dopant metal has a higher oxygen affinity than the bulk metal of the low oxygen affinity layer. The lower oxygen affinity layer may have a laminated structure in which dopant metals are disposed in different levels. The dopant metal may have a concentration gradient within the lower oxygen affinity layer. Reducing the dopant metal concentration in the direction of the higher oxygen affinity layer can further reduce the formation voltage. The embodiment of the invention also relates to an integrated chip and a manufacturing method thereof.

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer. The switching layer comprises an oxide, nitride, or oxynitride of a first element which is at least one element selected from the group consisting of Zr, Y, Ta, La, Ce, Ti, Hf, Zn, Si, and Al; a compound of a second element which is at least one element selected from the group consisting of Be, Mg, and Ca; and a third element which is at least one element selected from the group consisting of S, Se, and Te.

A non-volatile memory device includes: a resistive switching layer; a gate on the resistive switching layer; a gate oxide layer between the resistive switching layer and the gate; and a source and a drain on the resistive switching layer and spaced apart from each other. The resistance value of the resistive switching layer changes based on the illuminance of light illuminating the resistive switching layer and remains at the changed resistance value.

A device and method for high speed metamagnetic resistive switching provides a metamagnetic phase transitioning (MPT) portion formed on a substrate between terminals. The MPT portion is tuned for temperature-responsive transitions between magnetic phases through a transition phase. The phases are delineated by phase boundaries each traversed at different critical temperatures depending on direction of traversal. The critical temperatures of each phase boundary are mutually offset by a hysteretic shift. The MPT portion is boosted across one phase boundary responsive to thermal actuation pulsed in a first direction to reach or exceed both critical temperatures of that phase boundary in the first direction, and boosted across the other phase boundary responsive to thermal actuation pulsed in a second direction to reach or exceed both critical temperatures of that phase boundary in the second direction. The electrical conduction path is thereby adjusted in resistivity for switching between ON and OFF states.

Provided is a gating transistor manufacturing method, comprising: preparing a substrate, and depositing a dielectric layer (2) on an upper side of the substrate (1); depositing a lower electrode layer (3) on an upper side of the dielectric layer, and depositing a first metal layer (4) on an upper side of the lower electrode layer; depositing a resistive switching layer (5) on an upper side of the first metal layer, and depositing a second metal layer (6) on the resistive switching layer; depositing an upper electrode layer (7) on the second metal layer, so as to form a wafer; flipping the wafer, such that the substrate faces upward and the upper electrode layer faces downward; driving the wafer to rotate, and spraying an etching solution onto the substrate, such that the edge of the wafer is impregnated with the etching solution; and at the same time, performing wet etching on the edges of the second metal layer, the resistive switching layer, the first metal layer and the lower electrode layer. Thus, wet etching is performed on the edges of the second metal layer, the resistive switching layer, the first metal layer and the lower electrode layer, and wet etching is more efficient at etching the second metal layer and the first metal layer, with all by-products being soluble, such that the problems of metal exposure and contamination at the edge of the wafer can be solved.

According to the stacked single device based on the RRAM and the method for achieving the 2-bit vector product, a back gate and a back gate dielectric layer of the device are the bottommost layer, the back gate dielectric layer is connected with a bottom electrode, a resistive layer is arranged among the bottom electrode, a middle electrode and a top electrode, and the middle electrode is divided into a left middle electrode and a right middle electrode. The top electrode, the middle electrode, the bottom electrode and the resistive random access layer are stacked to form a first RRAM, a second RRAM, a third RRAM and a fourth RRAM, and the third RRAM is formed by connecting the left middle electrode with the bottom electrode and the top electrode through a through hole. And the other three RRAMs are set to be corresponding low / high impedance states according to weights, and then different 2-bit signals of 11, 10, 01 and 00 are input to obtain corresponding current magnitudes, so that a 2-bit vector product is realized. According to the method, the signal capacity is improved, the requirement for device normalization is lowered, the calculation speed is increased, the area efficiency is improved, 2-bit storage and vector product are achieved, and the method is suitable for neural network learning.

The task of reducing the forming voltage for an RRAM cell is solved with a resistive switching structure comprising at least two distinct layers. The thicknesses and compositions of the layers are selected such that a difference in oxygen affinity between the layers creates intrinsic oxygen vacancies in one of the layers. The task of increasing endurance is achieved by adding a dopant metal to the layer with the lower oxygen affinity. This dopant metal has a higher oxygen affinity than a primary metal in the layer with the lower oxygen affinity. The layer with the lower oxygen affinity can have a laminate structure in which the dopant metal is arranged in different layers.

This invention discloses a semiconductor memory device and a method for fabricating the same, wherein the semiconductor memory device includes a substrate; a first dielectric layer located on the substrate; a bottom electrode located on the first dielectric layer; a second dielectric layer located on the first dielectric layer; a top electrode located in the second dielectric layer, the top electrode including a lower portion and a tapered upper portion, the lower portion being located around the bottom electrode; a third dielectric layer located above the bottom electrode and around the tapered upper portion of the top electrode; a resistor switching layer located between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode, and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode; and an air gap located in the third dielectric layer.

The utility model discloses a resistance value switching circuit, which comprises a resistance switching unit comprising a plurality of parallel resistance channels and a chip U4, and the chip U4 is respectively connected with a controller in an optical fiber temperature measurement circuit and the plurality of parallel resistance channels and is used for outputting different resistance values; the power supply unit is connected with the resistance switching unit and used for supplying power to the resistance switching unit, the effect of outputting different resistance values according to instructions can be achieved, and therefore compatibility between optical fiber temperature measurement and a thermistor interface is achieved.

The application provides a nonvolatile alpha-Fe2O3 / TiO2 heterojunction memristor and a preparation and multi-value storage control method thereof, comprising a bottom electrode, an epitaxial TiO2 heterojunction resistive switching layer and an alpha-Fe2O3 heterojunction resistive switching layer are sequentially grown on the bottom electrode, and an upper electrode is deposited on the surface of the alpha-Fe2O3 heterojunction resistive switching layer. The application is a low-cost, high-density nonvolatile alpha-Fe2O3 / TiO2 heterojunction memristor, which has high stability, high reliability, high resistive switching ratio, and bipolar resistive switching storage characteristics. A simple, inexpensive and efficient hydrothermal preparation method is adopted, the controllable design of the alpha-Fe2O3 / TiO2 heterojunction is realized, and a simple and efficient implementation process is provided for the development and application of related materials.

An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

An RRAM string includes a substrate and numerous RRAM cells disposed on the substrate in a memory region. The RRAM cells include at least two last RRAM cells and one middle RRAM cell. Each RRAM cell includes a bottom electrode, a resistive switching layer, a top electrode, and a cap layer stacked from bottom to top. A first spacer contacts a first sidewall of the bottom electrode and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and a third sidewall of the top electrode. Furthermore, a dielectric layer covers the second spacer in the memory region. The dielectric layer at an outer side of the last RRAM cells includes a slope. An end of the slope contacts the second spacer located on a surface of the substrate.

The utility model discloses a resistive memory element and a memory device, and the resistive memory element comprises a lower electrode structure, and a resistive layer and an upper electrode structure which are sequentially stacked above the lower electrode structure. A first side wall and a second side wall are sequentially arranged in the side wall direction, opposite to the resistive storage element, of the upper electrode structure and the resistive layer; the first side wall covers the upper electrode structure and the side wall of the resistive layer; the second side wall covers the surface of the first side wall; the first side wall and the second side wall are made of different materials. By utilizing the scheme of the invention, the backwash problem of the resistive random access memory in the preparation process can be solved, and the stability of the memory element is improved. The first side wall can resist heat and pressure and can be tightly combined with the upper electrode structure and the resistive layer, and the second side wall can be tightly combined with the first side wall and a dielectric material deposited in the subsequent contact hole preparation process.