1577 results about "Low leakage" patented technology

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A method is described for a plasma treatment of a TiCl₄ based CVD deposited TiN layer that reduces stress, lowers resistivity, and improves film stability. Resistivity is stable in an air ambient for up to 48 hours after the plasma treatment. A TiN layer is treated with a N-containing plasma that includes N₂, NH₃, or N₂H₄ at a temperature between 500° C. and 700° C. Optionally, H₂ may be added to N₂ in the plasma step which removes chloride impurities and densifies the TiN layer. The TiN layer may serve as a barrier layer, an ARC layer, or as a bottom electrode in a MIM capacitor. An improved resistance of the treated TiN layer to oxidation during formation of an oxide based insulator layer and a lower leakage current in the MIM capacitor is also achieved.

It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.

An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.

Gallium nitride material structures, including devices, and methods associated with the same are provided. In some embodiments, the structures include one or more isolation regions which electrically isolate adjacent devices. One aspect of the invention is the discovery that the isolation regions also can significantly reduce the leakage current of devices (e.g., transistors) made from the structures, particularly devices that also include a passivating layer formed on a surface of the gallium nitride material. Lower leakage currents can result in increased power densities and operating voltages, amongst other advantages.

A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

A gates-line driving circuit of a display device includes a plurality of stages that are serially connected to each other, where each stage includes a plurality of transistors and a plurality of capacitors and receives a scanning start signal, a plurality of clock signals, and first and second gate-off voltages Voff1 and Voff2 of different magnitudes, where some of the transistors are turned off with the first gate-off voltage, and others of the transistors are turned off with the second gate-off voltage.

Electrolyte solutions for electrochromic devices such as rear view mirrors and displays with low leakage currents are prepared using inexpensive, low conductivity conductors. Preferred electrolytes include bifunctional redox dyes and molten salt solvents with enhanced stability toward ultraviolet radiation. The solvents include lithium or quaternary ammonium cations, and perfluorinated sulfonylimide anions selected from trifluoromethylsulfonate (CF₃SO₃⁻), bis(trifluoromethylsulfonyl)imide ((CF₃SO₂)₂N⁻), bis(perfluoroethylsulfonyl)imide ((CF₃CF₂SO₂)₂N⁻) and tris(trifluoromethylsulfonyl)methide ((CF₃SO₂)₃C⁻). Electroluminescent, electrochromic and photoelectrochromic devices with nanostructured electrodes include ionic liquids with bifunctional redox dyes. Some of the electrolyte solutions color to red when devices employing the solutions are powered, leading to red or neutral electrooptic devices.

A solid electrolytic capacitor that comprises an anode that contains a valve-action metal (e.g., tantalum, niobium, and the like) and a dielectric film overlying the anode is provided. The capacitor also comprises a protective coating overlying the dielectric film, wherein the protective coating contains a relatively insulative, resinous material. For example, in one embodiment, the resinous material can be a drying oil, such as olive oil, linseed oil, tung oil, castor oil, soybean oil, shellac, and derivatives thereof. The capacitor also comprises a conductive polymer coating overlying the protective coating. As a result of the present invention, it has been discovered that a capacitor can be formed that can have a relatively low leakage current, dissipation factor, and equivalents series resistance.

The invention provides an array substrate row driving circuit. The driving circuit comprises multiple array substrate row driving units, wherein an n-level array substrate row driving unit of the array substrate row driving circuit comprises an n-2 level signal input end (21), an n+2 level signal input end (22), a clock signal first input end (23), a clock signal second input end (24), a first low electric level input end (25), a second low electric level input end (26), a first output end (27), a second output end (28), a pull-up driving unit (32), a pull-up unit (34) and first to third pull-down units (36, 37 and 38). As a second low electric level signal is added, and the second low electric level is utilized to lower a voltage difference Vgs between a gate and a source of the first output end thin-film transistor, relatively low leakage current of the thin-film transistor is obtained, and precise control is achieved.