134 results about "Low leakage" patented technology

A video encoder and video decoder may include a video syntax processing (VSP) engine configured to process the video data at a syntax element level, and a video pixel processing (VPP) engine configured to process the video data at a pixel level. The video encoder and video decoder may further include a controller configured to control a power of the VSP engine based on the VSP engine being idle.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A circuit includes: a low-pass filter that includes a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a reference node. The circuit further includes: a first transistor, where a drain terminal of the first transistor is coupled to the second node, and a source terminal of the first transistor is coupled to the first node; and a second transistor, where a drain terminal of the second transistor is coupled to the first node, and a source terminal of the second transistor is coupled to the reference node, where a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control node.

FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-κ) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-K material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-κ material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-κ material.

This invention relates to the field of chip technology, specifically to a high-voltage GPP chip with composite trenches and its fabrication method, comprising: N layers arranged sequentially from bottom to top. + Substrate, N-layer, P-layer + Layer, the N + The substrate layer and the N layer form an N-N + Substrate, the P + Layer P and N layers constitute P + -N junction; trenches in the chip edge region, with the inner walls of the trenches covered by a composite passivation layer, the composite passivation layer comprising an inner boron-doped silicon glass layer and an outer phosphorus-doped silicon glass layer; an isolation ring on the inner side of the trench; covering P + Layer surface and N + The metal layer on the lower surface of the substrate serves as the electrode lead-out layer of the chip. The optimized fabrication process of this invention is highly compatible with each structure, achieving a comprehensive improvement in the overall performance of the chip. The matching of each fabrication step with the structural design allows the functions of each component of the chip to be fully utilized, synergistically achieving a comprehensive effect of high breakdown voltage, low leakage current, low forward voltage drop, and excellent high-temperature stability.

Fast low leakage SRAM cells, e.g., for digital display systems, are disclosed herein. In one embodiment, a bit memory circuit includes a latch coupled between a supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.

The present invention provides a method for forming a high-k metal oxide. By using a small amount of a precursor mainly composed of trisilyl amine (TSA, chemical formula: N(SiH3)3) to generate silicon dioxide (SiO2), and incorporating it into a high-k metal oxide with an organometallic compound as its precursor, a high-performance high-k metal oxide with a good interface layer to the substrate is formed. This approach effectively prevents leakage in a metal-insulator-semiconductor (MIS) structure and achieves a transistor gate oxide layer with high dielectric constant, low leakage current, high breakdown voltage, and high reliability, while also lowering production costs.

The invention provides sealing glass as well as a preparation method and application thereof. The preparation method comprises the following steps: preparing materials according to a sealing glass formula, uniformly mixing, and carrying out first ball milling; the raw materials are subjected to high-temperature melting, clarification, leakage forming and annealing, and lead glass is obtained; crushing lead glass, performing secondary ball milling, sieving, preparing the obtained glass powder into slurry, coating the surface of the to-be-passivated area with the slurry, and performing heat treatment to form a glass passivation layer; and immersing the glass passivation layer into molten toughening molten salt, and carrying out chemical toughening treatment at a designed temperature to synchronously remove sodium ions, so as to obtain the high-strength low-leakage-current sealing glass. The technical problem to be solved is how to prepare the sealing glass which has higher strength and chemical stability on the basis of meeting the performance that low-melting-point glass can be used for electronic device packaging in the prior art, the strength of the sealing glass can reach 300 MPa or above, the expansion coefficient is 35 * 10 <-6 >-50 * 10 <-6 > / DEG C, and the sealing glass is excellent in insulating property and can be applied to electronic device packaging. And the requirements of development in the fields of semiconductor surface passivation and the like on a sealing glass material can be met.

The invention provides a static random access memory, which comprises at least a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPD). The gate structures of the first pull-down transistor (PD1), the second pull-down transistor (PD2), the first access transistor (PG1) and the second access transistor (PG2) each include a P type work function metal layer, and an N type work function metal layer is located on the P type work function metal layer. The invention provides a static random access memory with low leakage current.

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

The application discloses a temperature and pressure sensor, and relates to the technical field of sensors.The temperature and pressure sensor comprises a shell, an electrical connector, a ceramic core, a temperature sensing element and a flexible circuit board.The shell forms a containing cavity with an opening.The electrical connector covers the opening at one end of the shell.The ceramic core is located in the containing cavity and jointly seals the containing cavity with the electrical connector.The ceramic core comprises a ceramic core substrate and a ceramic core pressure sensing sheet which are integrally connected, and a pin for connection.The temperature sensing element is located in the containing cavity and is welded with the pin of the ceramic core.The flexible circuit board is located in the containing cavity and is connected with the electrical connector and the ceramic core respectively.The temperature and pressure sensor provided by the application has simple structure, is convenient to assemble, has good sealing performance and low leakage risk.

The utility model aims at providing a kind of high energy efficiency, with weak energy collection and high integration, small size's low leakage rectifier unit.The utility model includes field effect tube and operational amplifier, the drain electrode of field effect tube is connected with power input terminal, the source of field effect tube is connected with output terminal, the output terminal of operational amplifier is connected with the grid of field effect tube, the opposite input terminal of operational amplifier is connected with power input terminal by feedback resistance, the same phase input terminal of operational amplifier is connected with the source of field effect tube, the source of field effect tube is also connected with output energy storage capacitor.The utility model is applied to the technical field of circuit structure.

The invention relates to the technical field of high polymer materials, and discloses a super junction MOSFET device structure and a manufacturing method thereof, and the method comprises the steps: forming a catalyst nano dot matrix on a semiconductor substrate; and then, in a single and continuous epitaxial growth process, N-type pulses and P-type pulses are alternately executed at high frequency, so that catalyst-guided growth of the N-type semiconductor columns and selective epitaxial filling growth of the P-type semiconductor columns are realized, and a self-aligned super junction structure is formed. According to the method, an in-situ real-time optical monitoring system is utilized, and according to different thicknesses of an epitaxial layer in the initial growth stage, the middle growth stage and the final growth stage, the duration time of pulses is adjusted in a self-adaptive mode, and surface topology is compensated. The prepared super junction structure is an integral single crystal structure without a physical interface, so that an atomic-scale steep doped junction is realized, the process is simplified, interface defects are eliminated, and charge balance can be accurately controlled, thereby obtaining a device with low leakage current, high breakdown voltage uniformity and high surface flatness.

Circuits and methods are disclosed that include a boost rail having a first voltage and an electrostatic discharge (ESD) rail having a second voltage that is less than the first voltage. An ESD protection circuit may include a trigger circuit configured to determine an ESD event on the boost rail and to selectively activate a clamp circuit to shunt current from the ESD rail to a power supply terminal in response to the ESD event. The circuit may include a first voltage drop circuit having a first configuration and coupled between a first power supply terminal and the boost rail to provide the first voltage and a second voltage drop circuit having a second configuration and coupled between the ESD rail and one of the boost rail or the first power supply terminal.

A multiplexer circuit includes a plurality of switch circuits coupled between respective input nodes and an output node. The switch circuits include first and second switch elements coupled in series, at an intermediate node, between the respective input node and the output node. A third switch element is coupled between an output of a buffer and the intermediate node. The buffer is configured to generate a buffered voltage based on the output voltage. When a particular switch circuit is selected, its respective first and second switch elements are active while its third switch element is inactive, resulting in a path between its input node and the output node. When the particular switch circuit is not selected, its third switch element is active while its first and second switch elements are inactive. The buffered voltage is driven to the intermediate node via the active third switch element.

The present application discloses a method for improving the defects of ultra-low leakage device after chemical mechanical polishing, the ultra-low leakage device adopts tungsten gate, and the thickness of tungsten layer deposited before chemical mechanical polishing is less than 2000 angstroms. The present application adopts tungsten metal gate instead of traditional aluminum metal gate, which can greatly reduce the resistance, and at the same time, provides positive pressure for the gate, which can effectively improve the performance of NMOS device. Meanwhile, the present application adjusts and controls the thickness of tungsten deposition of tungsten metal gate, which can significantly reduce the total number of defects of tungsten metal gate after chemical mechanical polishing, so that the tungsten residue is within the process allowable range, which effectively expands the window of chemical mechanical polishing defects of tungsten metal gate.

The embodiment of the invention provides a frequency determination method and device, electronic equipment and a storage medium. According to the scheme, the method comprises the following steps: obtaining a first corresponding relation between coupler frequencies and leakage rates according to operation of at least one resonance type double-quantum logic gate on a first quantum bit and a second quantum bit in a target system under different coupler frequencies; based on the first corresponding relation, the coupler frequency corresponding to the lowest leakage rate is selected as the target frequency, and the target frequency is the frequency of a control signal applied to the adjustable coupler when the first quantum bit and the second quantum bit execute the resonance type double-quantum logic gate operation. Through the technical scheme provided by the embodiment of the invention, the frequency of the control signal applied to the adjustable coupler during the execution period of the resonance type double-quantum logic gate can be determined, so that an observer error is effectively inhibited, and the fidelity of quantum calculation is improved.

The invention relates to the technical field of diode preparation, and particularly discloses a low-leakage Schottky diode and a preparation method thereof. The first N type GaN layer is arranged on the substrate; the first N-type GaN layer comprises a plane layer and a boss structure arranged on the plane layer; the N-type buried layer is arranged on the first N-type GaN layer; the second N-type GaN layer is arranged on the boss structure; the JTE region is arranged on the partial upper surface of the second N-type GaN layer, the side wall of the second N-type GaN layer, the side wall of the boss structure and the partial upper surface of the plane layer; the JTE region is a P-type GaN layer, is formed by Mg ion injection activation, and is not in contact with the Schottky electrode, the front ohmic electrode and the back ohmic electrode. The Mg-JTE terminal is adopted, a metal P-type terminal layer is not used, and the shielding effect, electric field reflection and distortion and high-frequency stray capacitance interference or inductance interference of metal under high frequency are eliminated from the source.

The invention relates to the technical field of planar transformers, in particular to a PCB (printed circuit board) high-power planar transformer, which adopts the technical scheme that the PCB high-power planar transformer comprises a plurality of layers of PCB substrates and a magnetic core penetrating through the plurality of layers of PCB substrates, the plurality of layers of PCB substrates at least comprise a first PCB layer and a second PCB layer, a primary winding is arranged on the first PCB layer, a secondary winding is arranged on the second PCB layer, and the magnetic core is arranged between the first PCB layer and the second PCB layer. The primary windings and the secondary windings are electrically connected between layers through metalized through holes, and the primary windings and the secondary windings are arranged in adjacent PCB layers in a staggered mode. The winding type transformer has the advantages of low leakage inductance and high power density, and solves the problems of large leakage inductance and large size of a traditional winding type transformer in high-frequency and high-voltage application.

This invention relates to the field of water hinge technology, specifically a dual-channel water hinge, comprising a rotating ring with a rotating structure on its exterior, and a docking structure for connecting water channels connected to the rotating ring; an overflow structure connected within the rotating ring; the rotating structure is sealed using a third sealing structure, and the rotating ring and the rotating structure are sealed using a first sealing structure and a second sealing structure. The embedded dual-channel design saves on the number of parts and installation space, reduces weight, and improves the power-to-weight ratio; effectively reducing processing costs. The sealing assembly uses dynamic and static ring mechanical seals, which have advantages such as reliable performance, low leakage, long service life, automatic compensation, and no frequent maintenance, and can meet the sealing requirements of harsh working conditions such as high temperature, low temperature, high pressure, high vibration, and highly corrosive media.

The application relates to the technical field of integrated circuit design, and particularly discloses a pre-charging low-leakage control circuit and method, which comprises the following: an MOS switch, the source electrode of which is electrically connected with the input end of a pre-charging buffer, and the drain electrode of which is electrically connected with the output end of the pre-charging buffer; the MOS switch is an NMOS switch, a PMOS switch or a CMOS switch; a control switch network, which comprises a plurality of control switches, one end of one of the control switches being electrically connected with the input end of a switch capacitor circuit; and the control switch network is used for connecting the back gate of the MOS switch to different working nodes according to the working phase of the control circuit. According to the application, the back gate of the MOS switch can be connected to different working nodes according to the working phase of the control circuit, so that when the MOS switch is turned on, the back gate always maintains the same potential as the input end of the pre-charging buffer, thereby reducing or eliminating the influence of the back gate effect on the control circuit.

An electrode structure and preparation methods thereof, the electrode structure includes a substrate and a sintered body, wherein the sintered body is formed on the surface of the substrate, and the sintered body is provided with cracks that are formed after the hydration treatment of the sintered body. The continuity of cracks of the electrode structure was good, and the preparation method is suitable for industrial production. The electrode structure with cracks can effectively increase the bending strength and reduce the stress during the winding process of the electrode structure, thereby reducing the risk of fracture during the application process. It can also improve the flexural strength of the electrode structure while maintaining the original high electrostatic capacity and lower leakage current value of the electrode structure, without negatively affecting the performance of the electrode structure.

The invention provides a method for forming a high-dielectric metal oxide, which comprises the following steps of: preparing silicon dioxide by doping a small amount of a precursor mainly comprising silane amine (Trisilylamine, TSA and N (SiH3) 3), and doping the silicon dioxide into a high-dielectric metal oxide which takes an organic metal compound as a precursor, so as to form a high-efficiency high-dielectric metal oxide with a good interface layer with a base material; according to the present invention, the electric leakage phenomenon of the metal-high dielectric metal oxide-silicon (MIS) structure can be effectively avoided, the high dielectric constant, the low leakage current, the high breakdown voltage, the high reliability and the like of the transistor gate electrode oxide layer can be achieved, and the production cost can be reduced.

The invention provides a display device and an electronic terminal. The display device includes an oxide semiconductor thin film transistor including an oxide semiconductor layer disposed on a gate insulating layer. The oxide semiconductor layer is doped with rare earth elements, the doping concentration of the rare earth elements at a first position in the oxide semiconductor layer is greater than that at a second position, and the first position is farther from the gate insulating layer than the second position. Through gradient doping, the position far away from the gate insulating layer has high carrier mobility, and the position close to the gate insulating layer has low leakage current, so that the leakage current of the thin film transistor is effectively reduced while a high switching ratio is maintained, the problem of flickering of a displayed picture under a low-frequency driving condition is solved, and the display efficiency is improved. And the display quality and stability are improved.

The application discloses a method for winding of a flyback transformer with extremely low leakage inductance, wherein the primary winding is wired on the same layer and the same side, and the secondary winding is wired on the same side but different layers, so that the loop area of the wired end is greatly reduced, the coil loop is more complete, the coupling degree of the primary winding and the secondary winding is enhanced, the leakage inductance of the transformer can be reduced to an extremely low value, the primary winding and the secondary winding are wound on the magnetic core in an interlaced and stacked manner, the leakage inductance of the transformer is reduced, the magnetic loss is reduced, and meanwhile, the copper loss and the parasitic capacitance between turns are not increased.

Disclosed is an electrolysis apparatus stack comprising two base plates clamped between a stack of elements having electrolysis cells, and at least one intermediate plate (30) clamped within the stack of elements. The intermediate plate (30) has a thickness comprising at least one electrolyte supply duct, a first duct for releasing a first electrolysis product, and a second duct (33) for releasing a second electrolysis product, each of which is individually integrated into a supply network, a first discharge network, and a second discharge network. Each of the ducts (33) within the intermediate plate (30) has a length exceeding the thickness of the intermediate plate (30) and includes a folded section (34) connecting inlet and outlet ports to each other.

A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

The application discloses a kind of six fluorine sulfur filled electrical equipment leakage management devices, including basic unit, sealing unit and clamping unit, wherein basic unit, including sealing body, connecting piece is connected to the one end of the sealing body.This six fluorine sulfur filled electrical equipment leakage management device, by sealing assembly is clamped between connecting piece and sealing body, by using manual wheel, let first clamping assembly clamp sealing shell and reduce gap, while, liquid guide assembly also carries out liquid guide, and the gap between sealing body and connecting piece is blocked by plugging glue, then, drainage is carried out using drainage device, to reduce the pressure of six fluorine sulfur gas on plugging glue, improve plugging success rate, after solidification, it can be covered with end, around leakage point using drainage device forms a closed space, reduces the pressure of leakage gas, improves the bonding quality of plugging glue, simultaneously, through drainage end, the sealing of closed space is realized, finally, through reinforcing glue, overall sealing is realized, to achieve the purpose of plugging.

The invention discloses a non-isolated high-gain three-port converter with a low leakage current characteristic and a control method thereof. The non-isolated high-gain three-port converter comprises a direct-current port I, a direct-current port II and an alternating-current port, the positive electrode of the first direct current port and the positive electrode of the second direct current port are electrically connected with the drain electrode of the first switching device. The negative electrode of the first direct-current port is electrically connected with the source electrode of the third switching device and one end of the third energy storage inductor. The negative electrode of the second direct-current port is electrically connected with one end of the first energy storage inductor. Stable alternating current output under the condition of wide-range photovoltaic voltage fluctuation can be achieved, leakage current is restrained, the size of the converter is reduced through the three-port structure and the single-stage topology, power density is high, efficiency is high, voltage stress of a switching device is low, cost is low, and the converter can be widely applied to various occasions needing direct current / direct current / alternating current conversion.