303 results about "Low leakage" patented technology

In one implementation, an apparatus, such as an ESD protection circuit, is disclosed. The apparatus can include a filter coupled between a local supply voltage rail to a supply voltage rail. A switch circuit can be connected in parallel with the filter. The apparatus can include a clamp configured to 1) provide a first ESD shunt path from an input line to the local supply voltage rail and 2) provide a second ESD shunt path from the input line to a lower voltage rail. A second clamp can be configured to provide a third ESD shunt path from the local supply voltage rail to the lower voltage rail. The switch circuit can be configured to close a switch to bypass the filter.

A P-type Extended Drain MOS (PEDMOS) FETs capable of high speed operation and the capability to withstand relatively high drain voltages. The PEDMOS device includes an active layer (preferably <110> orientated Si) having a P+ SiGe source region, a first P− Si drift region, a second P− SiGe drift region, and a P+ SiGe drain region. The SiGe regions exert compression on the N-type Si channel, improving hole mobility within the PEDMOS device and resulting in low leakage currents at active layer edges, low channel resistance, and good HCI and GIDL characteristics. Forming the SiGe regions may include etching voids in the Si active layer and depositing SiGe within the voids; implanting Ge into defined regions of the Si active layer; or etching partial voids in the Si active layer, depositing SiGe within the partial voids in contact with Si, and diffusing the Ge into the Si.

The invention discloses a capacitor dielectric layer and a preparation method thereof and a capacitor structure, the capacitor dielectric layer comprises at least two of a first lamination layer, a second lamination layer and a third lamination layer which are stacked along a first direction, and each lamination layer comprises a first dielectric layer and a second dielectric layer, the main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthogonal structure phase, and the main crystal phase of the second dielectric layer is at least one of the tetragonal structure phase and the orthogonal structure phase. The capacitor dielectric layer has a high dielectric constant and a low leakage current.

The invention provides an erasing method of a flash memory unit. The flash memory cell includes a memory transistor and a gate transistor connected in series. The erasing method comprises the steps that erasing voltages are applied to electrodes of the flash memory unit and gate electrodes of transistors, the erasing voltages applied to the gate electrodes of the erased memory transistors are lower than second power supply voltages, and therefore the channel hot electron induced hot hole injection physical effect occurs. Therefore, hot holes in the channel are attracted into the storage medium layer to realize erasing. Compared with the existing band-to-band tunneling hot hole (BBHH) erasing method, the erasing method of the flash memory unit disclosed by the invention has wider hole distribution and higher injection efficiency, so that the erasing method disclosed by the invention has higher erasing speed, larger erasing window, smaller hot carrier damage, lower leakage current and higher durability and reliability.

The invention relates to a low-channel-resistance SiC VDMOSFET device and a manufacturing method thereof, a conducting channel of the low-channel-resistance SiC VDMOSFET device comprises a laminated channel region, the laminated channel region is composed of n groups of P-type channel layers and N-type channel layers which are sequentially laminated, and n is larger than or equal to 1. According to the structure, accurate regulation and control of channel doping concentration and distribution can be realized. Moreover, the effective conductive depth of the channel is obviously increased by the multilayer conductive channel formed by the laminated channel region structure. The characteristic effectively weakens the interference of coulomb scattering, surface roughness scattering and other main scattering mechanisms on the channel carrier transport process, and further significantly improves the mobility of the carriers in the channel. According to the invention, the on-resistance is effectively reduced while the low leakage current of the device is ensured, so that the conduction loss is reduced, and the energy conversion efficiency is improved.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

A video encoder and video decoder may include a video syntax processing (VSP) engine configured to process the video data at a syntax element level, and a video pixel processing (VPP) engine configured to process the video data at a pixel level. The video encoder and video decoder may further include a controller configured to control a power of the VSP engine based on the VSP engine being idle.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P– hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

The present invention provides a microbubble generating device and a microbubble generating method. The microbubble generating device includes a housing with openings at both ends, and at least one shearing assembly is disposed within the housing. The shearing assembly includes a first internal component, a second internal component, and a third internal component, wherein a shearing chamber is formed between the first internal component, the second internal component, and the third internal component. The microbubble generating device provided by the present invention can produce microbubbles with uniform micron and nanometer sizes according to practical production needs, and the microbubbles can exist stably in a liquid phase and are not prone to coalescence. The microbubble generating device also has the advantages of a simple structure, easy disassembly, good sealing, low leakage risk, low energy consumption, low equipment cost, and a small size.

The invention discloses a low leakage current enabling control circuit and method suitable for a high-voltage LDO, the low leakage current enabling control circuit comprises a bias unit, a turn-off unit and an output unit, and the output end of the bias unit is connected with the input end of the turn-off unit to provide static bias current for the turn-off unit; the output end of the turn-off unit is connected with the input end of the output unit to provide a controllable high-voltage domain power supply for the output unit, and the first output end of the output unit is connected with the first input end of the low-voltage circuit module to provide a low-voltage domain power supply for the low-voltage circuit module. And the second output end of the output unit is connected with the second input end of the low-voltage circuit module and is used for controlling the enabling and turn-off of the low-voltage circuit module. According to the invention, the isolation degree of the chip in the disable state is improved, and the leakage current of the chip in the disable state is effectively reduced.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P− hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

A pixel driving circuit, a driving method thereof, and a display panel are proposed. The pixel driving circuit includes a switching transistor connected between a gate of the driving transistor and the initialization voltage node and between the first electrode of the driving transistor. The active layer of the switching transistor includes an oxide semiconductor with a characteristics of low leakage current. The display quality is improved when the display panel is operated in the low-frequency driving mode for display.

A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

The invention relates to the technical field of MOS semiconductors, and discloses an ultra-low leakage current VDMOS switch element and a manufacturing method thereof, the ultra-low leakage current VDMOS switch element comprises a metal drain electrode, a metal source electrode, a semiconductor epitaxial layer and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, and a connecting layer is arranged between the metal source electrode and the N well layer. According to the invention, TiSi, CoSi or highly-doped polycrystalline silicon is adopted as the material of the connecting layer between the metal source electrode and the N well layer, so that the interface contact resistance is obviously reduced, and the materials have excellent conductivity and low interface potential barrier characteristics, so that efficient ohmic contact can be realized, scattering and energy loss of carriers at the interface are reduced, and the performance of the device is improved. According to the design, Joule heat accumulation caused by poor contact is directly inhibited, so that leakage current is effectively reduced, and meanwhile, the conduction efficiency and the thermal stability of the device are improved.

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

The invention discloses a local platinum doping method for a fast soft recovery diode, and relates to the technical field of semiconductor manufacturing. According to the local platinum doping method for the fast soft recovery diode, hydrogen ions and helium ions are injected to form prefabricated atom vacancy defects, platinum atoms are induced to gather and stay in a prefabricated vacancy defect area, and local platinum atom doping is achieved. The performance advantages of traditional global platinum doping life control and local hydrogen / helium ion life control on the silicon-based fast recovery diode are organically combined, and prefabricated vacancy defects are flexibly formed at different depths through hydrogen ions and helium ions, so that precise local doping of platinum atoms is realized; meanwhile, the fast soft recovery diode has the performance advantages of good reverse recovery characteristic, high softness factor, low reverse recovery voltage change rate, good long-term reliability, low electric leakage, high device junction temperature and the like.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

The utility model discloses a nuclear power low-temperature low-leakage heat preservation electric heating regulating valve which comprises an actuator, the actuator is fixed to the side face of a valve body, and the output end of the actuator is in transmission connection with a driving shaft. The driving shaft penetrates through the first blade assembly and is rotationally connected with the valve body. The driving shaft is in transmission connection with the driven shaft through a rotating arm assembly; the driven shaft penetrates through the second blade assembly and is rotationally connected with the valve body. When the valve is closed, the first blade assembly and the second blade assembly are both tightly attached to the valve seat, and the first blade assembly and the second blade assembly are tightly attached. A first wiring terminal assembly and a second wiring terminal assembly are further fixed to the side face of the valve body, the first wiring terminal assembly is electrically connected with a first electric heating strip in the first blade assembly, and the second wiring terminal assembly is electrically connected with a second electric heating strip in the second blade assembly. The utility model can meet the requirement of stable operation with low leakage rate under the low-temperature condition.

The invention provides a TFET device and a forming method thereof, and the TFET device comprises a semiconductor substrate which comprises a first region and a second region; the gate structure is located on the surface of the semiconductor substrate and stretches across the first region and the second region, and the part, located in the first region, of the gate structure comprises an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer which are sequentially located on the surface of the semiconductor substrate; a part of the gate structure located in the second region comprises an oxide layer, an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer which are sequentially located on the surface of the semiconductor substrate; the source electrode and the drain electrode are located in the semiconductor substrate on the two sides of the gate structure respectively, the source electrode is located in the first area, and the drain electrode is located in the second area. According to the TFET device and the forming method thereof provided by the invention, the on-state current of the TFET device can be increased, the leakage current can be reduced, and the bipolar effect of the TFET can be weakened, so that the performance of the device can be improved.

The present invention belongs to the technical field of circuit design, and discloses a low-leakage current gating switch circuit for high-precision measurement of multiple resistors, including: diodes D1 to D7, triode Q3, MOS transistors Q1, Q4, Q5, Q6, operational amplifiers U1, U2; the standard current input terminal is grounded through diode D1, MOS transistor Q1, the source electrode of MOS transistor Q1, diode D3 and the resistor under test R4, and diode D3 is also connected to the ADC sampling terminal through MOS transistors Q5, Q4, Q6, the positive terminal of operational amplifier U2 is connected to the standard current input terminal, the negative terminal is connected to the output terminal, and the negative terminal is also connected to MOS transistor Q1 through diode D7 and diode D2; the positive terminal of operational amplifier U1 is connected to the ADC sampling terminal, the negative terminal is connected to the output terminal, the output terminal is connected to diode D2 through diode D6, and the output terminal of operational amplifier U1 is also connected to the source electrode of MOS transistor Q6 through diode D4. The present invention can reduce the overall leakage current of the circuit to the picoampere level, greatly improving the measurement accuracy.

Provided are an electrolytic capacitor and a manufacturing method capable of achieving both low specific resistance electrolyte and low leakage current. An anode body comprises an anode body of a valve metal, and a powder layer which is made of a valve metal powder and is formed on the anode body. A capacitor element includes the anode body, a cathode body, a separator, and an electrolyte containing moisture. The moisture content of the capacitor element is 4 wt% to 20 wt% inclusive relative to the electrolyte. This manufacturing method comprises: an element formation step for forming a capacitor element by stacking an anode body and a cathode body with a separator interposed therebetween; an impregnation step for impregnating the capacitor element with an electrolyte containing moisture; and an adjustment step for adjusting the moisture content of the capacitor element. In the element formation step, the anode body, which is formed by forming a powder layer of valve metal powder on an anode body of a valve metal, is overlaid on the cathode body with the separator interposed therebetween. In the adjustment step, the moisture content of the capacitor element is adjusted to 4-20 wt% relative to the electrolyte.

The invention provides a memory device and a reading method thereof. The memory device comprises a four-transistor (4T-SRAM) unit and a sensing circuit. The 4T-SRAM cell comprises two P-type MOSFET devices used for data bit storage and two N-type MOSFET devices used for access switches, and the 4T-SRAM cell has the advantages that the number of the MOSFET devices is small, and smaller cell size and low leakage current can be achieved. The sensing circuit comprises a switching device, a sensing latch and a discharging device. The switching device coupled between the sense latch and a ground voltage rail is designed to reduce read disturbances of the sense circuit to the 4T SRM cell by cutting off a channel leakage current path from an NMOSFET transistor in the sense latch to the ground voltage rail. A differential voltage signal for reading digital data stored in a 4T SRAM cell is enhanced by increasing sensing time. The read margin of the 4T SRAM is then greatly improved, thereby achieving an excellent and reliable read.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A circuit includes: a low-pass filter that includes a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a reference node. The circuit further includes: a first transistor, where a drain terminal of the first transistor is coupled to the second node, and a source terminal of the first transistor is coupled to the first node; and a second transistor, where a drain terminal of the second transistor is coupled to the first node, and a source terminal of the second transistor is coupled to the reference node, where a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control node.

The present invention provides a TCAM unit, belonging to the field of semiconductor integrated circuit design. The TCAM unit of the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a memory cell, whose first end is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode and can be in a high resistance state and a low resistance state; a complementary memory cell, whose first end is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode; a bit / select line, which is electrically connected to the second end of the memory cell; a complementary bit / select line, which is electrically connected to the second end of the complementary memory cell; a match line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor. The TCAM unit of the present invention has low leakage current, low power consumption in operation and standby mode, fewer connection lines, and high storage density.

FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-κ) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-K material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-κ material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-κ material.

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

The present disclosure relates to a body voltage generator for tracking current. Systems and devices are provided for tracking a bandgap current generated by a bandgap circuit and reducing leakage current regardless of changes in PVT conditions. An apparatus may include one or more power amplifiers that power components of the apparatus and include transistors. The apparatus may further include a bandgap current mirror processing circuitry that generates a mirror current that mirrors a received current independent of process, voltage, and temperature (PVT). The apparatus may further include a body voltage generator circuit that includes an amplifier having an input coupled to the bandgap current mirror processing circuitry. A body voltage control circuitry is coupled to an output of the amplifier and generates a body voltage based on a relationship between the mirror current and the leakage current.

This invention relates to the field of chip technology, specifically to a high-voltage GPP chip with composite trenches and its fabrication method, comprising: N layers arranged sequentially from bottom to top. + Substrate, N-layer, P-layer + Layer, the N + The substrate layer and the N layer form an N-N + Substrate, the P + Layer P and N layers constitute P + -N junction; trenches in the chip edge region, with the inner walls of the trenches covered by a composite passivation layer, the composite passivation layer comprising an inner boron-doped silicon glass layer and an outer phosphorus-doped silicon glass layer; an isolation ring on the inner side of the trench; covering P + Layer surface and N + The metal layer on the lower surface of the substrate serves as the electrode lead-out layer of the chip. The optimized fabrication process of this invention is highly compatible with each structure, achieving a comprehensive improvement in the overall performance of the chip. The matching of each fabrication step with the structural design allows the functions of each component of the chip to be fully utilized, synergistically achieving a comprehensive effect of high breakdown voltage, low leakage current, low forward voltage drop, and excellent high-temperature stability.