208 results about "Low leakage" patented technology

The invention discloses a capacitor dielectric layer and a preparation method thereof and a capacitor structure, the capacitor dielectric layer comprises at least two of a first lamination layer, a second lamination layer and a third lamination layer which are stacked along a first direction, and each lamination layer comprises a first dielectric layer and a second dielectric layer, the main crystal phase of the first dielectric layer is at least one of a tetragonal structure phase and an orthogonal structure phase, and the main crystal phase of the second dielectric layer is at least one of the tetragonal structure phase and the orthogonal structure phase. The capacitor dielectric layer has a high dielectric constant and a low leakage current.

The invention relates to a low-channel-resistance SiC VDMOSFET device and a manufacturing method thereof, a conducting channel of the low-channel-resistance SiC VDMOSFET device comprises a laminated channel region, the laminated channel region is composed of n groups of P-type channel layers and N-type channel layers which are sequentially laminated, and n is larger than or equal to 1. According to the structure, accurate regulation and control of channel doping concentration and distribution can be realized. Moreover, the effective conductive depth of the channel is obviously increased by the multilayer conductive channel formed by the laminated channel region structure. The characteristic effectively weakens the interference of coulomb scattering, surface roughness scattering and other main scattering mechanisms on the channel carrier transport process, and further significantly improves the mobility of the carriers in the channel. According to the invention, the on-resistance is effectively reduced while the low leakage current of the device is ensured, so that the conduction loss is reduced, and the energy conversion efficiency is improved.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

A video encoder and video decoder may include a video syntax processing (VSP) engine configured to process the video data at a syntax element level, and a video pixel processing (VPP) engine configured to process the video data at a pixel level. The video encoder and video decoder may further include a controller configured to control a power of the VSP engine based on the VSP engine being idle.

The present invention provides a microbubble generating device and a microbubble generating method. The microbubble generating device includes a housing with openings at both ends, and at least one shearing assembly is disposed within the housing. The shearing assembly includes a first internal component, a second internal component, and a third internal component, wherein a shearing chamber is formed between the first internal component, the second internal component, and the third internal component. The microbubble generating device provided by the present invention can produce microbubbles with uniform micron and nanometer sizes according to practical production needs, and the microbubbles can exist stably in a liquid phase and are not prone to coalescence. The microbubble generating device also has the advantages of a simple structure, easy disassembly, good sealing, low leakage risk, low energy consumption, low equipment cost, and a small size.

A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

The invention provides a TFET device and a forming method thereof, and the TFET device comprises a semiconductor substrate which comprises a first region and a second region; the gate structure is located on the surface of the semiconductor substrate and stretches across the first region and the second region, and the part, located in the first region, of the gate structure comprises an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer which are sequentially located on the surface of the semiconductor substrate; a part of the gate structure located in the second region comprises an oxide layer, an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer which are sequentially located on the surface of the semiconductor substrate; the source electrode and the drain electrode are located in the semiconductor substrate on the two sides of the gate structure respectively, the source electrode is located in the first area, and the drain electrode is located in the second area. According to the TFET device and the forming method thereof provided by the invention, the on-state current of the TFET device can be increased, the leakage current can be reduced, and the bipolar effect of the TFET can be weakened, so that the performance of the device can be improved.

Provided are an electrolytic capacitor and a manufacturing method capable of achieving both low specific resistance electrolyte and low leakage current. An anode body comprises an anode body of a valve metal, and a powder layer which is made of a valve metal powder and is formed on the anode body. A capacitor element includes the anode body, a cathode body, a separator, and an electrolyte containing moisture. The moisture content of the capacitor element is 4 wt% to 20 wt% inclusive relative to the electrolyte. This manufacturing method comprises: an element formation step for forming a capacitor element by stacking an anode body and a cathode body with a separator interposed therebetween; an impregnation step for impregnating the capacitor element with an electrolyte containing moisture; and an adjustment step for adjusting the moisture content of the capacitor element. In the element formation step, the anode body, which is formed by forming a powder layer of valve metal powder on an anode body of a valve metal, is overlaid on the cathode body with the separator interposed therebetween. In the adjustment step, the moisture content of the capacitor element is adjusted to 4-20 wt% relative to the electrolyte.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A circuit includes: a low-pass filter that includes a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a reference node. The circuit further includes: a first transistor, where a drain terminal of the first transistor is coupled to the second node, and a source terminal of the first transistor is coupled to the first node; and a second transistor, where a drain terminal of the second transistor is coupled to the first node, and a source terminal of the second transistor is coupled to the reference node, where a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control node.

FET designs, and in particular NMOSFET designs based on SOI fabrication technology, that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments include FETs in which the threshold voltage VTE of the edge FETs is increased to a level that is at least equal to the threshold voltage VTC of the central conduction channel FET using a novel dual work function configuration of a high dielectric constant (high-κ) replacement metal gate (RMG) structure. One embodiment encompasses a FET including an RMG structure overlying a doped silicon region, the RMG structure including: an interface insulator formed over the doped silicon region; a high-K material formed over the interface insulator; an N-type work function material overlaying and in contact with a central portion of the high-κ material; and a P-type work function material overlaying and in contact with at least one edge portion of the high-κ material.

This invention relates to the field of chip technology, specifically to a high-voltage GPP chip with composite trenches and its fabrication method, comprising: N layers arranged sequentially from bottom to top. + Substrate, N-layer, P-layer + Layer, the N + The substrate layer and the N layer form an N-N + Substrate, the P + Layer P and N layers constitute P + -N junction; trenches in the chip edge region, with the inner walls of the trenches covered by a composite passivation layer, the composite passivation layer comprising an inner boron-doped silicon glass layer and an outer phosphorus-doped silicon glass layer; an isolation ring on the inner side of the trench; covering P + Layer surface and N + The metal layer on the lower surface of the substrate serves as the electrode lead-out layer of the chip. The optimized fabrication process of this invention is highly compatible with each structure, achieving a comprehensive improvement in the overall performance of the chip. The matching of each fabrication step with the structural design allows the functions of each component of the chip to be fully utilized, synergistically achieving a comprehensive effect of high breakdown voltage, low leakage current, low forward voltage drop, and excellent high-temperature stability.

The invention discloses a leakage detection method for a barrier barrier of a refuse landfill, and belongs to the technical field of leakage detection. According to the invention, a sound wave source and equidistant linear arrangement detection points are arranged in a refuse landfill, low-frequency, medium-frequency and high-frequency sound waves are emitted, and corresponding forced vibration signals are collected; calculating an energy value, an energy stray value and a frequency stray value of each signal, and constructing a signal energy ratio, an energy stray ratio and a frequency stray ratio enhancement vector of adjacent detection points under the same emission frequency; calculating change values of a signal energy ratio, an energy stray ratio and a frequency stray ratio according to the enhancement vectors under the three emission frequencies; a barrier leakage detection model is adopted to process an enhancement vector, a leakage degree value is obtained based on change value feature adjustment, and the problem of low leakage detection precision in the prior art is solved.

Fast low leakage SRAM cells, e.g., for digital display systems, are disclosed herein. In one embodiment, a bit memory circuit includes a latch coupled between a supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.

The present invention provides a method for forming a high-k metal oxide. By using a small amount of a precursor mainly composed of trisilyl amine (TSA, chemical formula: N(SiH3)3) to generate silicon dioxide (SiO2), and incorporating it into a high-k metal oxide with an organometallic compound as its precursor, a high-performance high-k metal oxide with a good interface layer to the substrate is formed. This approach effectively prevents leakage in a metal-insulator-semiconductor (MIS) structure and achieves a transistor gate oxide layer with high dielectric constant, low leakage current, high breakdown voltage, and high reliability, while also lowering production costs.

The invention provides sealing glass as well as a preparation method and application thereof. The preparation method comprises the following steps: preparing materials according to a sealing glass formula, uniformly mixing, and carrying out first ball milling; the raw materials are subjected to high-temperature melting, clarification, leakage forming and annealing, and lead glass is obtained; crushing lead glass, performing secondary ball milling, sieving, preparing the obtained glass powder into slurry, coating the surface of the to-be-passivated area with the slurry, and performing heat treatment to form a glass passivation layer; and immersing the glass passivation layer into molten toughening molten salt, and carrying out chemical toughening treatment at a designed temperature to synchronously remove sodium ions, so as to obtain the high-strength low-leakage-current sealing glass. The technical problem to be solved is how to prepare the sealing glass which has higher strength and chemical stability on the basis of meeting the performance that low-melting-point glass can be used for electronic device packaging in the prior art, the strength of the sealing glass can reach 300 MPa or above, the expansion coefficient is 35 * 10 <-6 >-50 * 10 <-6 > / DEG C, and the sealing glass is excellent in insulating property and can be applied to electronic device packaging. And the requirements of development in the fields of semiconductor surface passivation and the like on a sealing glass material can be met.

The invention provides a static random access memory, which comprises at least a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPD). The gate structures of the first pull-down transistor (PD1), the second pull-down transistor (PD2), the first access transistor (PG1) and the second access transistor (PG2) each include a P type work function metal layer, and an N type work function metal layer is located on the P type work function metal layer. The invention provides a static random access memory with low leakage current.

The application discloses a low-leakage on-chip interconnection signal line system and an addressable test array circuit, and relates to the technical field of solving the problem of leakage of interconnection signal lines. The low-leakage on-chip interconnection signal line system comprises interconnection signal lines and signal protection channels which can be configured to have equal voltages, wherein the signal protection channels comprise: a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer shield the interconnection signal lines in the vertical projection direction of a chip, and the interconnection signal lines are located between the first shielding layer and the second shielding layer; a first shielding wall and a second shielding wall, the first shielding wall and the second shielding wall are connected to the first shielding layer and the second shielding layer respectively, and the interconnection signal lines are located between the first shielding wall and the second shielding wall.

The application discloses a temperature and pressure sensor, and relates to the technical field of sensors.The temperature and pressure sensor comprises a shell, an electrical connector, a ceramic core, a temperature sensing element and a flexible circuit board.The shell forms a containing cavity with an opening.The electrical connector covers the opening at one end of the shell.The ceramic core is located in the containing cavity and jointly seals the containing cavity with the electrical connector.The ceramic core comprises a ceramic core substrate and a ceramic core pressure sensing sheet which are integrally connected, and a pin for connection.The temperature sensing element is located in the containing cavity and is welded with the pin of the ceramic core.The flexible circuit board is located in the containing cavity and is connected with the electrical connector and the ceramic core respectively.The temperature and pressure sensor provided by the application has simple structure, is convenient to assemble, has good sealing performance and low leakage risk.

The utility model aims at providing a kind of high energy efficiency, with weak energy collection and high integration, small size's low leakage rectifier unit.The utility model includes field effect tube and operational amplifier, the drain electrode of field effect tube is connected with power input terminal, the source of field effect tube is connected with output terminal, the output terminal of operational amplifier is connected with the grid of field effect tube, the opposite input terminal of operational amplifier is connected with power input terminal by feedback resistance, the same phase input terminal of operational amplifier is connected with the source of field effect tube, the source of field effect tube is also connected with output energy storage capacitor.The utility model is applied to the technical field of circuit structure.

The invention relates to the technical field of high polymer materials, and discloses a super junction MOSFET device structure and a manufacturing method thereof, and the method comprises the steps: forming a catalyst nano dot matrix on a semiconductor substrate; and then, in a single and continuous epitaxial growth process, N-type pulses and P-type pulses are alternately executed at high frequency, so that catalyst-guided growth of the N-type semiconductor columns and selective epitaxial filling growth of the P-type semiconductor columns are realized, and a self-aligned super junction structure is formed. According to the method, an in-situ real-time optical monitoring system is utilized, and according to different thicknesses of an epitaxial layer in the initial growth stage, the middle growth stage and the final growth stage, the duration time of pulses is adjusted in a self-adaptive mode, and surface topology is compensated. The prepared super junction structure is an integral single crystal structure without a physical interface, so that an atomic-scale steep doped junction is realized, the process is simplified, interface defects are eliminated, and charge balance can be accurately controlled, thereby obtaining a device with low leakage current, high breakdown voltage uniformity and high surface flatness.

This application discloses a state adjustment method, device, electronic device, and storage medium based on a single-qubit gate, relating to qubit gate state control technology. The method includes: performing charge drive and flux drive on a superconducting qubit Fluxonium equivalent circuit; adjusting the amplitudes of an AC voltage source and an AC current source respectively to equalize the Rabi oscillation frequency of the flux drive and the charge drive; adjusting the drive frequency and the qubit frequency to meet resonance conditions; adjusting the dimensionless envelope function and the phases of the charge drive and flux drive to rotate about a rotation axis located in a first coordinate plane; and adjusting the rotation axis to different rotation angles to represent different states of the qubit. This application enables superconducting qubits to have both a low leakage error rate and fast single-quantum gate operation.

Circuits and methods are disclosed that include a boost rail having a first voltage and an electrostatic discharge (ESD) rail having a second voltage that is less than the first voltage. An ESD protection circuit may include a trigger circuit configured to determine an ESD event on the boost rail and to selectively activate a clamp circuit to shunt current from the ESD rail to a power supply terminal in response to the ESD event. The circuit may include a first voltage drop circuit having a first configuration and coupled between a first power supply terminal and the boost rail to provide the first voltage and a second voltage drop circuit having a second configuration and coupled between the ESD rail and one of the boost rail or the first power supply terminal.

A multiplexer circuit includes a plurality of switch circuits coupled between respective input nodes and an output node. The switch circuits include first and second switch elements coupled in series, at an intermediate node, between the respective input node and the output node. A third switch element is coupled between an output of a buffer and the intermediate node. The buffer is configured to generate a buffered voltage based on the output voltage. When a particular switch circuit is selected, its respective first and second switch elements are active while its third switch element is inactive, resulting in a path between its input node and the output node. When the particular switch circuit is not selected, its third switch element is active while its first and second switch elements are inactive. The buffered voltage is driven to the intermediate node via the active third switch element.

The present application discloses a method for improving the defects of ultra-low leakage device after chemical mechanical polishing, the ultra-low leakage device adopts tungsten gate, and the thickness of tungsten layer deposited before chemical mechanical polishing is less than 2000 angstroms. The present application adopts tungsten metal gate instead of traditional aluminum metal gate, which can greatly reduce the resistance, and at the same time, provides positive pressure for the gate, which can effectively improve the performance of NMOS device. Meanwhile, the present application adjusts and controls the thickness of tungsten deposition of tungsten metal gate, which can significantly reduce the total number of defects of tungsten metal gate after chemical mechanical polishing, so that the tungsten residue is within the process allowable range, which effectively expands the window of chemical mechanical polishing defects of tungsten metal gate.

The embodiment of the invention provides a frequency determination method and device, electronic equipment and a storage medium. According to the scheme, the method comprises the following steps: obtaining a first corresponding relation between coupler frequencies and leakage rates according to operation of at least one resonance type double-quantum logic gate on a first quantum bit and a second quantum bit in a target system under different coupler frequencies; based on the first corresponding relation, the coupler frequency corresponding to the lowest leakage rate is selected as the target frequency, and the target frequency is the frequency of a control signal applied to the adjustable coupler when the first quantum bit and the second quantum bit execute the resonance type double-quantum logic gate operation. Through the technical scheme provided by the embodiment of the invention, the frequency of the control signal applied to the adjustable coupler during the execution period of the resonance type double-quantum logic gate can be determined, so that an observer error is effectively inhibited, and the fidelity of quantum calculation is improved.

The invention relates to the technical field of diode preparation, and particularly discloses a low-leakage Schottky diode and a preparation method thereof. The first N type GaN layer is arranged on the substrate; the first N-type GaN layer comprises a plane layer and a boss structure arranged on the plane layer; the N-type buried layer is arranged on the first N-type GaN layer; the second N-type GaN layer is arranged on the boss structure; the JTE region is arranged on the partial upper surface of the second N-type GaN layer, the side wall of the second N-type GaN layer, the side wall of the boss structure and the partial upper surface of the plane layer; the JTE region is a P-type GaN layer, is formed by Mg ion injection activation, and is not in contact with the Schottky electrode, the front ohmic electrode and the back ohmic electrode. The Mg-JTE terminal is adopted, a metal P-type terminal layer is not used, and the shielding effect, electric field reflection and distortion and high-frequency stray capacitance interference or inductance interference of metal under high frequency are eliminated from the source.