49 results about "Gate leakage current" patented technology

The invention relates to the technical field of on-line health monitoring of wide bandgap semiconductor power devices, and discloses an on-line gate leakage current monitoring method and system for a GaN power device, and the method comprises the steps: extracting an average gate driving current which is within a complete switching period, an average value of instantaneous currents flowing into or out of the gate of the GaN power device; and on the basis of the average gate driving current, gate leakage current is obtained, so that online gate leakage current monitoring of the GaN power device can be carried out. The system corresponds to the method. According to the invention, the core problem that the traditional voltage detection method is insufficient in resolution and cannot realize early warning is fundamentally solved; meanwhile, a source electrode series sampling and non-intrusive signal conditioning circuit is adopted, a switch and a voltage stabilizing circuit are prevented from being introduced into a grid electrode driving loop, and therefore interference on parasitic parameters of the grid electrode loop is eliminated, and feasibility and reliability of application in a high-frequency and high-sensitivity GaN power device are ensured.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

The present invention relates to a single-crystalline Al2O3 dielectric compatible with two-dimensional materials and an integrated device thereof. A single-crystalline Al thin film is produced on a single-crystalline graphene / germanium (110) substrate via the van der Waals (vdW) epitaxy approach, the single-crystalline Al thin film is peeled off from the graphene / germanium substrate, and intercalative oxidation is performed to produce the single-crystalline Al2O3 dielectric compatible with two-dimensional materials on the lower surface of the single-crystalline Al thin film. The gate leakage current (J<1×10−5 A cm−2), interface state density (Dit=8.4×109 cm−2 eV−1), and dielectric strength (Ebd=17.4 MV / cm) of the single-crystalline Al2O3 dielectric obtained in the present invention can meet the requirements of the international roadmap for devices and systems (IRDS) for low power consumption devices.

The invention discloses a power semiconductor device thermal resistance monitoring method and system based on grid leakage current. The system comprises a voltage source, a current source, a thermocouple and a grid leakage current monitoring module. The voltage source is used for providing voltage excitation for the power semiconductor device to be tested; the current source is used for applying current excitation to the to-be-tested power semiconductor device, so that the to-be-tested power semiconductor device reaches a thermal stable state; the thermocouple is used for extracting the shell temperature of the to-be-tested power semiconductor device in a thermal stable state and further obtaining the thermal resistance value of the to-be-tested power semiconductor device by combining the power loss and the temperature rise data; and the grid leakage current monitoring module is used for evaluating the junction temperature of the power semiconductor device to be measured based on the grid leakage current. According to the monitoring method, direct junction temperature extraction is completed based on grid leakage current, thermal resistance is measured and calculated in combination with current excitation, shell temperature collection and power loss data, and integrated acquisition of thermal characteristic parameters is achieved.

The application provides a high-temperature bias test system and method for a power semiconductor device, which comprises a control module (1), a temperature control module (3), a detection module (4), a test channel (5) and a power module (2); the detection module (4) is used for simultaneously detecting the gate leakage current, the gate voltage, the collector-emitter leakage current and the collector-emitter voltage of the power semiconductor device, and can realize single or double test of high-temperature gate bias test and high-temperature blocking test of power semiconductor devices with the same or different specifications, has good compatibility, can meet the batch test demand, does not need to be equipped with multiple test systems, has low cost, high test efficiency, convenient maintenance, independent test branches, safe isolation, small mutual influence, accurate detection and high reliability; the requirements of test voltage and test junction temperature are strictly guaranteed, and the compatibility, utilization rate and accuracy of the test system are improved.

This invention discloses a GaN bidirectional blocking device with a polarized gate structure and its fabrication method, relating to the field of semiconductor device technology. The device includes a substrate with a thickness of 400 μm-1000 μm, a buffer layer of GaN with a thickness of 500 μm-5000 μm disposed on the substrate, a GaN channel layer disposed on the buffer layer, and an AlGaN barrier layer disposed on the GaN channel layer with a thickness of 15 nm-30 nm. An active electrode is disposed on the AlGaN barrier layer. This GaN bidirectional blocking device with a polarized gate structure and its fabrication method, based on the material structure, allows the p-GaN layer at the drain electrode and the drain metal to form a junction barrier Schottky diode structure, which can constitute a bidirectional blocking device as a whole, extending its application to more power applications. It solves the problem of how to improve the structure of traditional p-GaN gate devices to increase their forward gate withstand voltage, reduce gate leakage current, and improve the device's threshold voltage.

The invention discloses a gate structure based on an array p-GaN layer embedded MIS and a semiconductor power device, the gate structure is arranged on the surface of an AlGaN barrier potential layer, and comprises a continuous p-GaN layer, a gate sinking metal and an interval p-GaN layer which are sequentially arranged on the surface of the AlGaN barrier potential layer along the transverse direction; the continuous p-GaN layer is close to the source electrode, and the interval p-GaN layer is close to the drain electrode; wherein the interval p-GaN layer is divided into a plurality of segments at equal intervals along the longitudinal direction by the bulges on the surface of the gate sinking metal; the semiconductor power device comprises a substrate, a nucleating layer, an AlGaN transition layer with gradually-changed Al components, a GaN buffer layer, an AlGaN back barrier layer, a UID GaN layer and an AlGaN barrier layer which are sequentially covered from top to bottom, and the gate structure is installed on the AlGaN barrier layer. According to the gate structure, the dynamic threshold voltage drift caused by the gate-drain coupling barrier lowering effect is reduced, and the problem that the dynamic on-resistance is increased in the switching process caused by the back gate effect is inhibited; the problem of electric field concentration below the grid electrode is optimized, the voltage resistance of the device is improved, and the leakage current of the grid electrode is reduced.

This paper presents a low-interface-state gallium nitride (GaN) power device structure and fabrication method based on fluoride gate dielectric, belonging to the field of semiconductor device technology. Firstly, utilizing the principle of seamless filling in high aspect ratio structures, dielectric filling and repair are achieved in the deep recesses of the gate trench in the MIS recessed gate structure, suppressing electric field concentration at the corners and long-term device reliability degradation. Next, the principle of fluoride ion implantation is introduced to grow fluoride as the gate dielectric, improving current density while maintaining high interface quality and strong gate control capability, and reducing device instability caused by fluoride ion implantation. Secondly, fluoride is selectively grown in the gate region using magnetron sputtering, leveraging the advantages of fluoride treatment while ensuring device current density and on-resistance. The wide bandgap of fluoride can suppress hot electron injection under high electric field conditions, while the strong electronegativity of fluoride ions helps passivate the donor states on the GaN surface, forming better interface quality and improving gate leakage current and reliability degradation.

The invention provides a GaN HEMT (High Electron Mobility Transistor) device and a manufacturing method thereof, which are characterized in that at least one heat conduction hole is arranged in a field plate area corresponding to the GaN HEMT device, the heat conduction hole extends upwards from the back of the device and stops on the lower surface of a passivation layer on the surface of the device, and a heat conduction material is formed in the heat conduction hole and can conduct heat from a heating core of the device to the outside. According to the GaN HEMT device provided by the invention, the heat dissipation capability of the GaN HEMT device is effectively improved, the influence of a self-heating effect on the carrier mobility is reduced, the saturation leakage current and the reduction of transconductance are avoided, the gate leakage current and the hot electron damage are reduced, the reliability of the device is improved, and the service life of the device is prolonged.

The invention provides a test circuit, a test method and a test system for gate leakage current of an MOS (Metal Oxide Semiconductor) tube. The test circuit comprises a band-gap reference voltage module, a high-resistance module, a leakage current detection module and a test voltage excitation module, and the output end of the band-gap reference voltage module is coupled with the first end of the high-resistance module. The second end of the high-resistance module, the output end of the test voltage excitation module and the leakage current detection module are coupled to a grid current test node used for being connected with the MOS tube to be tested. The band-gap reference voltage module provides a bias voltage with a first preset threshold value; the test voltage excitation module provides continuous scanning voltage; the leakage current detection module detects the test current of the current test node and obtains a leakage current detection result according to the bias voltage, the scanning voltage and the test current. According to the invention, the detection of the gate leakage current of the to-be-tested MOS transistor at the fA magnitude can be realized, and the charge stability of the gate node of the to-be-tested MOS transistor can be ensured, so that the consistency of batch testing can be ensured, and the reliability is high.

The application belongs to the technical field of power devices, and provides a self-alignment patterning preparation method, a trench silicon carbide device and a chip. A trench etching mask is used to define a trench region. A gate trench is etched to reach the N-type drift region under the coverage of the trench etching mask. A first self-alignment medium layer is used to form a P-type shielding region at the bottom of the trench by using a self-alignment patterning process. A second self-alignment medium layer is used to form a concave corner protection layer along the inner wall of the gate trench. The self-alignment medium layer is used as an implantation mask and an isolation layer at the same time, thereby saving multiple photolithography steps. The alignment accuracy of the P-type shielding region is improved, the electric field of the central oxide layer at the bottom of the trench gate is reduced, the device gate leakage current phenomenon is reduced, the reliability of the device is improved, and the two core problems of high-precision doping and high-temperature process compatibility in the silicon carbide power device are solved.

A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate, a nucleation layer, a first GaN buffer layer, a source-drain p-GaN buried layer, a second GaN buffer layer, a GaN layer, and an AlGaN barrier layer. A drain electrode and a source electrode are respectively provided on both sides of the AlGaN barrier layer, and a gate electrode trench is provided on the side of the AlGaN barrier layer near the drain electrode. Toothed protrusions and grooves matching the protrusions are distributed on the opposite side of the first and second GaN buffer layers. The toothed source-drain junction between the first and second GaN buffer layers... The buried p-GaN layer improves the electric field distribution between the gate and drain, the gate and source, and the source and drain of the device, reducing the average electric field magnitude. Compared with previous methods, this invention has a better effect on electric field mitigation, increases the breakdown voltage of the device, and makes the device more difficult to break down. In addition, by etching the barrier layer in the region below the gate to form a gate electrode trench, depositing a p-GaN layer on top of the gate electrode trench, and growing a gate dielectric layer between the p-GaN layer in the gate electrode trench and the gate electrode, a high threshold voltage and a large current are obtained, reducing the gate leakage current of the device, while improving the gate's withstand voltage capability, increasing the switching speed of the device, and improving the reliability of the device operation.

The invention belongs to the technical field of power devices, and provides a trench silicon carbide device and a chip, a P-type shielding region is formed at the bottom of a trench of the trench silicon carbide device, a corner protection layer of a concave structure is formed on the P-type shielding region, and a gate dielectric layer is located on the corner protection layer. A gate dielectric layer and a field oxide layer form a closed structure wrapping a gate material layer, so that the two sides of the bottom of the gate dielectric layer are isolated by a corner protection layer and an N-type drift region respectively, the electric field of a central oxide layer at the bottom of a trench type gate can be reduced, the gate leakage current phenomenon of the device is reduced, and the reliability of the device is improved.

The invention relates to the technical field of semiconductors, and provides a gallium nitride device and method, and the gallium nitride device comprises a two-dimensional electron gas layer group which is used for forming two-dimensional electron gas; the first gallium nitride layer is arranged on the two-dimensional electron gas layer group; the gradient layer group is arranged on the first gallium nitride layer; and the gate metal layer is arranged on the gradient layer group. And an energy band potential barrier is formed in an energy band between the metal layer and the first gallium nitride layer through the gradient layer group, so that the hole blocking capability is enhanced. When positive bias voltage is applied to the grid electrode, the energy band potential barrier of the gradient layer group can inhibit injection of holes from the grid electrode to the two-dimensional electron gas, the height of the potential barrier is firstly increased and then reduced in the direction away from the two-dimensional electron gas, and the gradually-changed potential barrier height can form a corresponding electric field inside to further inhibit injection of the holes. And meanwhile, injection of electrons from the two-dimensional electron gas to the grid electrode is inhibited, so that the leakage current of the grid electrode is reduced, the threshold voltage drift is reduced, and the voltage endurance capability and robustness of the grid electrode are enhanced.

The invention belongs to the technical field of power devices, and provides a trench silicon carbide device and a chip, a P-type shielding region is formed at the bottom of a trench of the trench silicon carbide device, a gate oxide layer of a concave structure is formed on the P-type shielding region, and the gate oxide layer and a field oxide layer form a closed structure wrapping gate polycrystalline silicon. And the first isolation dielectric layer and the second isolation dielectric layer are respectively formed on two sides of the bottom of the gate oxide layer, so that the electric field of the central oxide layer at the bottom of the trench-type gate can be reduced, the gate leakage current phenomenon of the device is reduced, and the reliability of the device is improved.

The application discloses a gallium oxide MODFET device with a p-SnO hybrid gate and a preparation method thereof, which comprises buffer, interval, doping and barrier layers on a substrate, forms source-drain regions, source-drain electrodes, a p-SnO layer, a gate dielectric, a first passivation layer, a gate electrode, a floating field plate, a second passivation layer, a dielectric layer and a source field plate and the like. A p-n junction and a MIS structure are deposited in a gate recess, a three-dimensional gate control is realized by fully surrounding the gate electrode, strong depletion of the p-n junction is realized, a high-quality interface of the MIS structure is combined, high threshold voltage is obtained, low gate leakage current and high reliability are maintained. A composite field plate of an integrated discrete floating field plate and a high-k dielectric recess and a source field plate is adopted, on the one hand, a capacitive coupling effect of the floating field plate is used to realize a stepwise and smooth lateral electric field and hardly add gate-drain capacitance, and low Miller capacitance is maintained; on the other hand, high-k dielectric is introduced in a high electric field area near a drain electrode, and redistribution of a longitudinal electric field is realized; and the two kinds of field plates are cooperated to realize three-dimensional modulation of an internal electric field of the device, increase a breakdown voltage and maintain a relatively fast switching speed.

This invention discloses a GaN field-effect transistor, comprising a substrate; an epitaxial layer having a source, a drain, and an epitaxial trench near the source; and a gate structure disposed within the epitaxial trench, the gate structure comprising: a heavily doped p-GaN layer deposited at the bottom of the epitaxial trench for conducting a two-dimensional electron gas channel for depleting the gate structure; a lightly doped p-GaN layer deposited on the heavily doped p-GaN layer, with trench structures formed on both sides of the lightly doped p-GaN layer; a gate dielectric layer covering the sidewalls of the lightly doped p-GaN layer and the trench structures, and the sidewalls of the heavily doped p-GaN layer; and a gate metal layer in contact with the top of the lightly doped p-GaN layer for forming a gate Schottky contact with the lightly doped p-GaN layer. This invention overcomes the problem that the gate breakdown voltage of traditional p-GaN gate HEMT devices is generally less than 10V, significantly improving the gate forward breakdown voltage of GaNHEMT devices and reducing the gate leakage current.

The invention discloses a grid stress testing method, device and equipment of a power semiconductor device and a medium. The method comprises the steps of obtaining a to-be-tested power semiconductor device, and performing electrical short circuit on a drain electrode and a source electrode of the to-be-tested power semiconductor device; applying a grid source stress voltage pulse higher than a rated working grid voltage between the grid electrode and the source electrode of the power semiconductor device to be tested; measuring the gate leakage current of the to-be-tested power semiconductor device under the preset gate voltage after the gate source stress voltage pulse is applied; and comparing the measured value of the gate leakage current with a preset threshold value, and screening out the power semiconductor device with potential gate defects according to a comparison result. According to the invention, the semiconductor power device with the potential defect problem in the grid electrode can be effectively screened out.

The application provides a HEMT device and a preparation method thereof, and the HEMT device comprises a semiconductor layer, a cap layer, a passivation dielectric layer, a source / drain / gate and a gate contact structure, wherein the semiconductor layer comprises a channel layer and a barrier layer which are stacked in sequence; the cap layer is located on the upper surface of the barrier layer; the passivation dielectric layer covers the exposed upper surface of the barrier layer and the exposed surface of the cap layer; the source and the drain respectively penetrate through the passivation dielectric layer and are electrically connected with the conductive channel at the interface of the barrier layer and the channel layer, and the source and the drain are located on the two sides of the cap layer which are oppositely arranged and are arranged at intervals from the cap layer; the gate contact structure penetrates through the passivation dielectric layer, and the gate contact structure comprises first and second barrier contact parts which respectively form Schottky contact with the cap layer and have different barrier heights between the cap layer; the gate is electrically connected with the top of the first and second barrier contact parts. Through the arrangement of the gate contact structure, the gate leakage current is reduced, the threshold voltage drift is avoided, and the performance of the device is improved.

An apparatus for measuring a gate leakage current of a MOSFET. The apparatus includes a current mirror adapted to be connected to a gate of a MOSFET, a gate driver adapted to generate a driving signal for the MOSFET, and a sensing resistor connected to the current mirror. An input current path of the current mirror is adapted to receive a gate leakage current of the MOSFET. The current mirror provides a high sensitivity of the measurement because the voltage across the current mirror is nearly constant, which therefore caters for different situations no matter if the gate leakage current is high or low.

The invention discloses a transverse conductive gallium nitride-based normally-off field effect transistor and a preparation method thereof, and relates to the technical field of power electronic devices. The structure comprises a substrate, a buffer layer, an i-GaN epitaxial layer, an AlN epitaxial layer, a SiO2 layer, an Mg-Al-O layer located above the AlN epitaxial layer, a source electrode and a drain electrode which are arranged on the AlN epitaxial layer, a diffusion layer generated after high-temperature processing, and a grid electrode arranged on the Mg-Al-O layer. The preparation process is simple, the threshold voltage of the obtained device is easy to adjust, and the performance is stable and reliable; the high-temperature-resistant lithium ion battery not only has high output current density, but also has good high-temperature-resistant operation capability. In addition, the Al-Mg-O structure is adopted as the gate oxide layer of the field effect transistor device, the gate leakage current is small, and the transconductance of the device is obviously improved compared with the transconductance of the device when the gate is made of a single material.

The application discloses a power device and a preparation method thereof. The power device comprises a substrate, a channel layer, a barrier layer, a gate structure covering part of the barrier layer, a first passivation structure covering the gate structure and part of the barrier layer, and the first passivation structure comprises an opening, the opening exposes a surface of the barrier layer away from the substrate, the opening comprises at least a first opening, the first opening is located on one side of the gate structure adjacent to the drain, the surface of the barrier layer exposed by the opening away from the substrate is doped with electronegative atoms, and the oxidizability of the electronegative atoms is greater than or equal to that of oxygen atoms, a second passivation structure covers the first passivation structure and the surface of the barrier layer exposed by the opening away from the substrate, the source and the drain are both located on a surface of the barrier layer away from the channel layer, and the distance between the source and the gate structure is smaller than the distance between the gate structure and the drain. The application can reduce the gate leakage current, improve the concentration of the two-dimensional electron gas in the drift region and the dynamic performance of the device.

The application relates to a high-voltage-resistant reinforced double-heterojunction gate HEMT and a preparation method thereof, which comprises a nucleation layer, a buffer layer, a p-type buried layer, a channel layer, an insertion layer and a barrier layer which are sequentially stacked on a substrate, and a double-heterojunction gate, a source and a drain are arranged on the barrier layer, wherein the double-heterojunction gate is composed of a PNP double-heterojunction cap layer and a gate metal layer on the double-heterojunction cap layer. The double-heterojunction gate in the device is in contact with the barrier layer, can deplete the two-dimensional electron gas of the channel, makes the threshold voltage of the device increase, and when the device wants to reach the conduction state, the PNP double-heterojunction serves as two face-to-face diodes, the two diodes consume a certain voltage drop, makes the voltage reaching the channel layer decrease, and further makes the threshold voltage of the device increase, and the PNP double-heterojunction can prevent the electrons from entering the channel layer from the gate, thereby reducing the gate leakage current and improving the breakdown voltage of the device.

The invention discloses a semiconductor structure and a preparation method thereof, a chip, an integrated circuit and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a high dielectric medium layer on the substrate; forming a protective metal layer on one side, far away from the substrate, of the high-dielectric dielectric layer; performing oxidation treatment on the protective metal layer to form a protective layer; forming a barrier layer on one side, far away from the high dielectric medium layer, of the protective layer; and forming a gate metal layer on one side, far away from the protective layer, of the barrier layer. According to the semiconductor structure, the reaction between disadvantageous oxygen such as free oxygen and unbonded oxygen existing on the surface of the barrier layer and the surface of the high-dielectric dielectric layer can be reduced, the gate leakage current is improved, and the carrier mobility is improved, so that the electrical performance of the metal gate is improved.

The invention discloses a two-dimensional semiconductor top gate field effect transistor and a preparation method thereof, and the preparation method comprises the steps: preparing a source electrode and a drain electrode on the surface of a two-dimensional semiconductor material, defining a two-dimensional semiconductor channel region, carrying out the plasma processing of an exposed region of the two-dimensional semiconductor channel region, and forming an oxide layer. And preparing a gate dielectric layer, and preparing a gate on the surface of the gate dielectric layer. In the invention, the seed crystal layer is obtained by directly carrying out plasma treatment on the two-dimensional semiconductor, interlayer coupling and a good interlayer interface of a two-dimensional material are utilized, defects between the seed crystal layer and a two-dimensional semiconductor channel are effectively reduced, and the seed crystal layer is used for assisting growth of the gate dielectric layer, so that the high-quality gate dielectric layer is obtained; the finally prepared top gate field effect transistor has good electrical properties of low gate leakage current, small hysteresis and the like, reduces power consumption, can adapt to an advanced process, and has a wide application prospect in manufacturing of large-scale integrated circuits.

The present invention provides a pixel driving circuit and a display panel. The pixel driving circuit comprises a sixth transistor, a third scan signal line, and a third capacitor; the sixth transistor is a dual-gate transistor; and a first electrode of the third capacitor is connected to the third scan signal line, and a second electrode of the third capacitor is connected to the midpoint of the sixth transistor. The present invention can reduce a gate leakage current of a driving transistor, mitigate the low-frequency flicker phenomenon of a display panel, and improve the user experience.

The invention provides a semiconductor structure and a forming method thereof, in the forming method of the semiconductor structure, a first gate dielectric layer is firstly formed, and the first gate dielectric layer covers substrates of a first well region and a second well region; forming a second gate dielectric layer by adopting an atomic layer deposition process, wherein the second gate dielectric layer covers the first gate dielectric layer; wherein the second gate dielectric layer is made of HfTiO. Titanium is an effective dopant, the oxide of titanium has a high k value, and the k value of HfTiO is about 30; and in addition, the HfTiO also shows good thermal stability and is relatively high in crystallization temperature. In addition, Ti and Hf are tetravalent elements, and Ti-doped HfO2 does not cause increase of oxygen vacancies, so that increase of leakage current in the film is avoided. Therefore, by using the Ti-doped hafnium oxide film as the gate oxide dielectric layer, the k value is improved, so that the lower equivalent oxide thickness is obtained under the same thickness, the gate leakage current is reduced, and the device performance is improved.

To provide a polarization superjunction field effect transistor capable of significantly reducing the gate leakage current that flows when a positive voltage is applied to the gate electrode. 【Solution means】This field effect transistor includes a first undoped GaN layer 11, Al x , x , 1-x , x , 1-x , x , 1-x , 1-y , 1-x , 1-x , y Ga 1-x N layer 12 (0.17 ≤ x ≤ 0.35), a second undoped GaN layer 13, a p-type GaN layer 15, Al x Ga 1-x An intermediate layer 14 between the Al x Ga 1-x N layer and the second undoped GaN layer, a source electrode 18 and a drain electrode 19 on the Al x Ga 1-x N layer, and a gate electrode 17 on the p-type GaN layer. The intermediate layer is a graded Al x Ga 1-x N layer (x ≤ y < 0.5) in which the bandgap increases continuously and / or stepwise from the bandgap of the Al y Ga 1-y N layer at the interface between the N layer and the intermediate layer towards the interface between the second undoped GaN layer and the intermediate layer, and has a thickness such that carriers do not substantially move due to the tunneling effect.

This invention discloses a gallium oxide power transistor containing a high-resistivity gallium oxide thin layer and its fabrication method, belonging to the field of gallium oxide transistor technology. From bottom to top, it comprises: a substrate, a buffer layer, a conductive channel layer, a high-resistivity gallium oxide thin layer, a gate dielectric layer, and a gate. The two sides of the gate are connected to the source and drain, which are electrically connected to the conductive channel layer. The resistivity of the high-resistivity gallium oxide thin layer is higher than that of the conductive channel layer. The gallium oxide power transistor of this invention effectively suppresses electron leakage from the channel layer to the gate, thereby directly reducing the gate leakage current and improving the dielectric reliability of the gate and the long-term stability of the gallium oxide power transistor.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, the semiconductor device comprises at least one storage unit located on a substrate, the storage unit comprises a first transistor, the first transistor comprises a first gate electrode, a first gate dielectric layer, a second gate electrode, a second gate dielectric layer and a first semiconductor layer, the first semiconductor layer is located on the side, away from the substrate, of the first gate electrode, the second gate electrode is located on the side, away from the substrate, of the first semiconductor layer, and the first semiconductor layer extends in the row direction parallel to the substrate; the first gate dielectric layer is located between the first gate electrode and the first semiconductor layer, and the second gate dielectric layer is located between the second gate electrode and the first semiconductor layer; the first gate dielectric layer and the second gate dielectric layer are made of different materials. The semiconductor device provided by the embodiment of the invention has relatively high storage density and strong grid control capability, can reduce grid electric leakage, and further improves the performance of the device.