111 results about "Gate leakage current" patented technology

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

The invention relates to the technical field of on-line health monitoring of wide bandgap semiconductor power devices, and discloses an on-line gate leakage current monitoring method and system for a GaN power device, and the method comprises the steps: extracting an average gate driving current which is within a complete switching period, an average value of instantaneous currents flowing into or out of the gate of the GaN power device; and on the basis of the average gate driving current, gate leakage current is obtained, so that online gate leakage current monitoring of the GaN power device can be carried out. The system corresponds to the method. According to the invention, the core problem that the traditional voltage detection method is insufficient in resolution and cannot realize early warning is fundamentally solved; meanwhile, a source electrode series sampling and non-intrusive signal conditioning circuit is adopted, a switch and a voltage stabilizing circuit are prevented from being introduced into a grid electrode driving loop, and therefore interference on parasitic parameters of the grid electrode loop is eliminated, and feasibility and reliability of application in a high-frequency and high-sensitivity GaN power device are ensured.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

The invention relates to the technical field of state monitoring, in particular to an optical storage device state monitoring method and system based on an FPGA. The method comprises the following steps: acquiring FPGA structure data; deploying a ring oscillator unit in an FPGA idle logic resource area based on the FPGA structure data, and configuring a leakage current measurement channel on an FPGA programmable I / O pin to obtain leakage current measurement channel configuration data; acquiring RO oscillation frequency data and grid leakage current data according to the leakage current measurement channel configuration data; and performing mapping calculation on the RO oscillation frequency data and the grid leakage current data based on a preset temperature calibration curve and a voltage calibration curve. Through high-precision real-time monitoring and multiple regression modeling based on the FPGA, the diagnosis precision and intelligent early warning capability of the temperature and stress of the key area of the optical storage equipment are effectively improved, and the problem that a traditional monitoring system is insufficient in accuracy, real-time performance and pertinence is solved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide SiCMOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) device with improved gate oxide layer reliability, the silicon carbide SiCMOSFET device is composed of a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, a high-K medium is arranged between the grid electrode and the P well layer, and doped polycrystalline silicon is arranged on one side of the high-K medium and located between the source electrode and the N well layer. The high-K medium is one of hafnium oxide, aluminum oxide or zirconium dioxide. Through the double-layer stacked structure of the high-K dielectric and the SiOO gate oxide layer, the high dielectric constant of the high-K material is utilized to share the gate voltage, the electric field intensity of a SiOO interface is remarkably reduced, meanwhile, two orders of magnitude of gate leakage current are reduced, and gate oxide layer degradation caused by hot carrier injection is fundamentally inhibited.

The invention discloses a multi-scale electronic component service life prediction method based on physical deep learning, and relates to the field of intelligent prediction of electronic component service life. The objective of the invention is to solve the problem that a machine learning model adopted during life prediction is limited in multi-scale multi-source data cooperative processing capability and is difficult to accurately characterize the performance change of the whole life cycle of a device. Constructing a threshold voltage model with the simultaneous influence of the interface state and the oxide trap charge based on the dominating factor; considering the threshold voltage model with the simultaneous influence of the interface state and the oxide trapped charge, and constructing a variable quantity model of the on-resistance; establishing a comprehensive index model including drain current, gate leakage current, transconductance, capacitance, switching time and power consumption and thermal resistance of the tested electronic component; and taking the output results of the threshold voltage model, the on-resistance variable quantity model and the comprehensive index model as the input of a deep learning model, and predicting through the deep learning model to obtain the service life of the tested electronic component.

The invention provides a gallium nitride P-type channel field effect transistor, and relates to the technical field of transistor manufacturing. According to the invention, the first transistor structure and the second transistor structure are cascaded, and the ohmic contact is formed, so that the two-dimensional hole gas current of the second transistor structure can be used as the gate leakage current of the first transistor structure to control the on and off of the first transistor structure; the current amplification effect can be controlled by analogy of the current of a bipolar transistor, and the current density is improved.

The present invention relates to a single-crystalline Al2O3 dielectric compatible with two-dimensional materials and an integrated device thereof. A single-crystalline Al thin film is produced on a single-crystalline graphene / germanium (110) substrate via the van der Waals (vdW) epitaxy approach, the single-crystalline Al thin film is peeled off from the graphene / germanium substrate, and intercalative oxidation is performed to produce the single-crystalline Al2O3 dielectric compatible with two-dimensional materials on the lower surface of the single-crystalline Al thin film. The gate leakage current (J<1×10−5 A cm−2), interface state density (Dit=8.4×109 cm−2 eV−1), and dielectric strength (Ebd=17.4 MV / cm) of the single-crystalline Al2O3 dielectric obtained in the present invention can meet the requirements of the international roadmap for devices and systems (IRDS) for low power consumption devices.

To address the problems that existing device models fail to simultaneously consider the effects of dislocations on both drain current and gate leakage current, the models for dislocation effects on drain current fail to dynamically simulate charge capture and release, and the gate leakage current models fail to fully consider the effects of dislocations, the present invention discloses a modeling method for a GaN HEMT device model that considers dislocation effects. The modeling method includes: establishing a model for the effects of dislocations on GaN HEMT drain current; establishing a model for the effects of dislocations on GaN HEMT gate leakage current; integrating the models for the effects of dislocations on GaN HEMT drain current and gate leakage current into a surface potential-based model to obtain a GaN HEMT device model that considers dislocation effects and describes it using the Verilog‑A language; and providing a parameter extraction method for the GaN HEMT device model that considers dislocation effects.

The invention discloses a grid leakage current model of an MOS device. The expression of the grid leakage current model is shown in the specification. Wherein the gate-substrate voltage Vgb is used as a functional expression of an independent variable, and the functional expression is used for describing the change trend of the gate leakage current Igate along with the gate-substrate voltage Vgb; the functional expression takes gate-substrate voltage Vgb and gate oxide layer thickness tox of the device as independent variables and is used for describing the difference phenomenon of the gate leakage current Igate in an accumulation region and a depletion region; the temperature compensation function takes the current temperature T as an independent variable. According to the scheme, the fitting precision of the gate leakage current in the depletion region can be improved.

The invention discloses a power semiconductor device thermal resistance monitoring method and system based on grid leakage current. The system comprises a voltage source, a current source, a thermocouple and a grid leakage current monitoring module. The voltage source is used for providing voltage excitation for the power semiconductor device to be tested; the current source is used for applying current excitation to the to-be-tested power semiconductor device, so that the to-be-tested power semiconductor device reaches a thermal stable state; the thermocouple is used for extracting the shell temperature of the to-be-tested power semiconductor device in a thermal stable state and further obtaining the thermal resistance value of the to-be-tested power semiconductor device by combining the power loss and the temperature rise data; and the grid leakage current monitoring module is used for evaluating the junction temperature of the power semiconductor device to be measured based on the grid leakage current. According to the monitoring method, direct junction temperature extraction is completed based on grid leakage current, thermal resistance is measured and calculated in combination with current excitation, shell temperature collection and power loss data, and integrated acquisition of thermal characteristic parameters is achieved.

The application provides a high-temperature bias test system and method for a power semiconductor device, which comprises a control module (1), a temperature control module (3), a detection module (4), a test channel (5) and a power module (2); the detection module (4) is used for simultaneously detecting the gate leakage current, the gate voltage, the collector-emitter leakage current and the collector-emitter voltage of the power semiconductor device, and can realize single or double test of high-temperature gate bias test and high-temperature blocking test of power semiconductor devices with the same or different specifications, has good compatibility, can meet the batch test demand, does not need to be equipped with multiple test systems, has low cost, high test efficiency, convenient maintenance, independent test branches, safe isolation, small mutual influence, accurate detection and high reliability; the requirements of test voltage and test junction temperature are strictly guaranteed, and the compatibility, utilization rate and accuracy of the test system are improved.

This invention discloses a GaN bidirectional blocking device with a polarized gate structure and its fabrication method, relating to the field of semiconductor device technology. The device includes a substrate with a thickness of 400 μm-1000 μm, a buffer layer of GaN with a thickness of 500 μm-5000 μm disposed on the substrate, a GaN channel layer disposed on the buffer layer, and an AlGaN barrier layer disposed on the GaN channel layer with a thickness of 15 nm-30 nm. An active electrode is disposed on the AlGaN barrier layer. This GaN bidirectional blocking device with a polarized gate structure and its fabrication method, based on the material structure, allows the p-GaN layer at the drain electrode and the drain metal to form a junction barrier Schottky diode structure, which can constitute a bidirectional blocking device as a whole, extending its application to more power applications. It solves the problem of how to improve the structure of traditional p-GaN gate devices to increase their forward gate withstand voltage, reduce gate leakage current, and improve the device's threshold voltage.

The invention provides a SiC UMOSFET device with stacked gate dielectric layers. The SiC UMOSFET device comprises an N + substrate region, an N-drift region, a P-well region, a P + region, an N + region and the gate dielectric layers. The N-drift region is arranged above the N + substrate region, and a P-well region is arranged on the N-drift region; a P + region and an N + region are correspondingly arranged on the P-well region; the middle parts of the N + region and the P-well region are provided with U-shaped grooves, and the U-shaped grooves are filled with gate dielectric layers. According to the invention, the stacked gate dielectric layers can effectively suppress gate leakage current and improve the reliability and voltage resistance of the device, and the thin layer SiO2 in the stacked gate dielectric layers can improve the barrier height of the device, suppress carriers from penetrating through the barrier and reduce the gate leakage current; according to the thin-layer SiO2, the interface characteristics between SiC and SiO2 and between SiO2 and HfO2 can be improved, the interface state density is reduced, and the performance of a device is further improved.

The present disclosure relates to a semiconductor structure, a method for fabricating the same, and a buried wordline structure. The semiconductor structure includes a substrate, a trench, a first dielectric layer, a first conductive layer, a second conductive layer, a target sidewall spacer, and a third conductive layer. The substrate includes spaced doped regions; the trench is located between the doped regions, with its bottom surface no higher than the bottom surface of the doped regions; the first dielectric layer covers the sidewalls and bottom surface of the trench; the first conductive layer is located on the surface of the first dielectric layer at the bottom of the trench, with its top surface no higher than the bottom surface of the doped regions; the second conductive layer is located on the top surface of the first conductive layer, with its top surface lower than the top surface of the doped regions; the target sidewall spacer is located on the top surface of the second conductive layer and covers a portion of the side surface of the first dielectric layer; and the third conductive layer is located on the top surface of the second conductive layer, with its top surface higher than the bottom surface of the doped regions and lower than the top surface of the target sidewall spacer. This semiconductor structure can increase drive current and reduce gate leakage current, thereby improving the read and write speed and reliability of the semiconductor structure.

The invention discloses a gate structure based on an array p-GaN layer embedded MIS and a semiconductor power device, the gate structure is arranged on the surface of an AlGaN barrier potential layer, and comprises a continuous p-GaN layer, a gate sinking metal and an interval p-GaN layer which are sequentially arranged on the surface of the AlGaN barrier potential layer along the transverse direction; the continuous p-GaN layer is close to the source electrode, and the interval p-GaN layer is close to the drain electrode; wherein the interval p-GaN layer is divided into a plurality of segments at equal intervals along the longitudinal direction by the bulges on the surface of the gate sinking metal; the semiconductor power device comprises a substrate, a nucleating layer, an AlGaN transition layer with gradually-changed Al components, a GaN buffer layer, an AlGaN back barrier layer, a UID GaN layer and an AlGaN barrier layer which are sequentially covered from top to bottom, and the gate structure is installed on the AlGaN barrier layer. According to the gate structure, the dynamic threshold voltage drift caused by the gate-drain coupling barrier lowering effect is reduced, and the problem that the dynamic on-resistance is increased in the switching process caused by the back gate effect is inhibited; the problem of electric field concentration below the grid electrode is optimized, the voltage resistance of the device is improved, and the leakage current of the grid electrode is reduced.

The invention discloses a high-performance two-dimensional transistor and a preparation method and application thereof, and relates to the technical field of semiconductor material manufacturing, and the structure of the transistor comprises a channel layer, a gate dielectric layer and an electrode assembly. Wherein the channel layer is made of a two-dimensional semiconductor material; the gate dielectric layer is made of a layered phosphorus gallium sulfide material; the electrode assembly comprises a grid electrode, a source electrode and a drain electrode; the channel layer and the gate dielectric layer are combined through Van der Waals force. The preparation method comprises the following steps: obtaining a two-dimensional material sheet through mechanical stripping, and sequentially stacking the two-dimensional semiconductor material channel, the layered phosphorus gallium sulfide dielectric layer and the graphite grid electrode by adopting a dry transfer technology. The obtained transistor shows excellent electrical properties: the current on-off ratio is greater than or equal to 3 * 10 < 8 >, the gate leakage current is less than or equal to 1 * 10 <-13 > A, the subthreshold swing is about 85 mV / dec, and the interface hysteresis voltage is as low as 20 mV. The method is suitable for low-power-consumption and high-performance integrated circuits, logic electronic devices and optoelectronic devices.

This paper presents a low-interface-state gallium nitride (GaN) power device structure and fabrication method based on fluoride gate dielectric, belonging to the field of semiconductor device technology. Firstly, utilizing the principle of seamless filling in high aspect ratio structures, dielectric filling and repair are achieved in the deep recesses of the gate trench in the MIS recessed gate structure, suppressing electric field concentration at the corners and long-term device reliability degradation. Next, the principle of fluoride ion implantation is introduced to grow fluoride as the gate dielectric, improving current density while maintaining high interface quality and strong gate control capability, and reducing device instability caused by fluoride ion implantation. Secondly, fluoride is selectively grown in the gate region using magnetron sputtering, leveraging the advantages of fluoride treatment while ensuring device current density and on-resistance. The wide bandgap of fluoride can suppress hot electron injection under high electric field conditions, while the strong electronegativity of fluoride ions helps passivate the donor states on the GaN surface, forming better interface quality and improving gate leakage current and reliability degradation.

The invention discloses a device for testing electric leakage of an IGBT (Insulated Gate Bipolar Translator) of an automobile-level power component, which comprises a functional module, a man-machine interaction unit and a power adapter, and is characterized in that the functional module is provided with an input interface and an output interface; the function module comprises a battery grid driving voltage source automatic adjusting part, a grid leakage current acquisition unit, a test monomer, a DC-DC power supply unit, an MCU and a battery management unit. The MCU controls the 24BIT ADC through the SPI, reads a sampled voltage value after the acquired data is stable, converts a current value according to an acquisition process development proportion and a sampling resistance value, and controls and stores the current value after the read current value is subjected to algorithm processing; according to the invention, a modular design is adopted, functions are complete, expandability is high, use is simple and convenient, the device can be suitable for technical index test scenes such as field detection and laboratory test, professional design thoughts are integrated, a function circuit special for IGBT monomer or module leakage current test is designed, different connection modes are matched, and parameters are convenient to set.

The invention provides a GaN HEMT (High Electron Mobility Transistor) device and a manufacturing method thereof, which are characterized in that at least one heat conduction hole is arranged in a field plate area corresponding to the GaN HEMT device, the heat conduction hole extends upwards from the back of the device and stops on the lower surface of a passivation layer on the surface of the device, and a heat conduction material is formed in the heat conduction hole and can conduct heat from a heating core of the device to the outside. According to the GaN HEMT device provided by the invention, the heat dissipation capability of the GaN HEMT device is effectively improved, the influence of a self-heating effect on the carrier mobility is reduced, the saturation leakage current and the reduction of transconductance are avoided, the gate leakage current and the hot electron damage are reduced, the reliability of the device is improved, and the service life of the device is prolonged.

The invention relates to a power semiconductor device in GaN technology. The present disclosure proposes an integrated auxiliary (dual) gate terminal and pull-down network to achieve a normally-off (E-mode) GaN transistor with a threshold voltage above 2V, low gate leakage current, and enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device and a low voltage auxiliary GaN device, the high voltage GaN device having a gate (10) transistor connected to a source (12) of the integrated auxiliary low voltage GaN and a drain as an external high voltage drain terminal (9) and a source as an external source terminal (8), the low-voltage auxiliary GaN transistor has a gate (first auxiliary electrode 15) serving as an external gate terminal connected to the drain (second auxiliary electrode 16). In an embodiment, a pull-down network for turning off a high threshold voltage GaN transistor is formed from an additional auxiliary low voltage GaN transistor (34) and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.

The invention provides a test circuit, a test method and a test system for gate leakage current of an MOS (Metal Oxide Semiconductor) tube. The test circuit comprises a band-gap reference voltage module, a high-resistance module, a leakage current detection module and a test voltage excitation module, and the output end of the band-gap reference voltage module is coupled with the first end of the high-resistance module. The second end of the high-resistance module, the output end of the test voltage excitation module and the leakage current detection module are coupled to a grid current test node used for being connected with the MOS tube to be tested. The band-gap reference voltage module provides a bias voltage with a first preset threshold value; the test voltage excitation module provides continuous scanning voltage; the leakage current detection module detects the test current of the current test node and obtains a leakage current detection result according to the bias voltage, the scanning voltage and the test current. According to the invention, the detection of the gate leakage current of the to-be-tested MOS transistor at the fA magnitude can be realized, and the charge stability of the gate node of the to-be-tested MOS transistor can be ensured, so that the consistency of batch testing can be ensured, and the reliability is high.

The present application provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, an in-situ insulating layer is formed on a heterojunction. The in-situ insulating layer has a groove, and a transition layer is provided in the groove and on the in-situ insulating layer. A p-type semiconductor layer is formed in a gate region on the transition layer. The transition layer facilitates the formation of the p-type semiconductor layer outside the groove during the process. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be relatively small, thereby increasing the threshold voltage. In addition, due to the provision of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of two-dimensional electron gas can be increased, the control ability of the gate over the channel can be improved, and the working current can be enhanced.

The application belongs to the technical field of power devices, and provides a self-alignment patterning preparation method, a trench silicon carbide device and a chip. A trench etching mask is used to define a trench region. A gate trench is etched to reach the N-type drift region under the coverage of the trench etching mask. A first self-alignment medium layer is used to form a P-type shielding region at the bottom of the trench by using a self-alignment patterning process. A second self-alignment medium layer is used to form a concave corner protection layer along the inner wall of the gate trench. The self-alignment medium layer is used as an implantation mask and an isolation layer at the same time, thereby saving multiple photolithography steps. The alignment accuracy of the P-type shielding region is improved, the electric field of the central oxide layer at the bottom of the trench gate is reduced, the device gate leakage current phenomenon is reduced, the reliability of the device is improved, and the two core problems of high-precision doping and high-temperature process compatibility in the silicon carbide power device are solved.

This invention discloses a method for fabricating a low-frequency, low-noise operational amplifier, including the steps of growing an oxide layer on the surface of a silicon substrate, forming a P-well region within the substrate using photolithography, ion implantation, and push-well thermal diffusion, and the following steps: N+ source / drain fabrication, N-channel fabrication, P+ gate region fabrication, BPSG protective film fabrication, metal fabrication, and passivation layer fabrication. This invention utilizes a grid-like JFET gate structure to increase the device gate area and improve JFET transconductance. Simultaneously, the parallel structure of the JFETs effectively reduces gate leakage current and input noise voltage. Furthermore, by fabricating an N+ contact region, the ohmic contact resistance between the source and the metal is reduced, effectively decreasing thermal resistance noise and lowering the device noise voltage.

A grooved MIS structure transistor with a toothed p-GaN buried layer includes, from bottom to top, a substrate, a nucleation layer, a first GaN buffer layer, a source-drain p-GaN buried layer, a second GaN buffer layer, a GaN layer, and an AlGaN barrier layer. A drain electrode and a source electrode are respectively provided on both sides of the AlGaN barrier layer, and a gate electrode trench is provided on the side of the AlGaN barrier layer near the drain electrode. Toothed protrusions and grooves matching the protrusions are distributed on the opposite side of the first and second GaN buffer layers. The toothed source-drain junction between the first and second GaN buffer layers... The buried p-GaN layer improves the electric field distribution between the gate and drain, the gate and source, and the source and drain of the device, reducing the average electric field magnitude. Compared with previous methods, this invention has a better effect on electric field mitigation, increases the breakdown voltage of the device, and makes the device more difficult to break down. In addition, by etching the barrier layer in the region below the gate to form a gate electrode trench, depositing a p-GaN layer on top of the gate electrode trench, and growing a gate dielectric layer between the p-GaN layer in the gate electrode trench and the gate electrode, a high threshold voltage and a large current are obtained, reducing the gate leakage current of the device, while improving the gate's withstand voltage capability, increasing the switching speed of the device, and improving the reliability of the device operation.

The invention belongs to the technical field of power devices, and provides a trench silicon carbide device and a chip, a P-type shielding region is formed at the bottom of a trench of the trench silicon carbide device, a corner protection layer of a concave structure is formed on the P-type shielding region, and a gate dielectric layer is located on the corner protection layer. A gate dielectric layer and a field oxide layer form a closed structure wrapping a gate material layer, so that the two sides of the bottom of the gate dielectric layer are isolated by a corner protection layer and an N-type drift region respectively, the electric field of a central oxide layer at the bottom of a trench type gate can be reduced, the gate leakage current phenomenon of the device is reduced, and the reliability of the device is improved.

The invention relates to the technical field of semiconductors, and provides a gallium nitride device and method, and the gallium nitride device comprises a two-dimensional electron gas layer group which is used for forming two-dimensional electron gas; the first gallium nitride layer is arranged on the two-dimensional electron gas layer group; the gradient layer group is arranged on the first gallium nitride layer; and the gate metal layer is arranged on the gradient layer group. And an energy band potential barrier is formed in an energy band between the metal layer and the first gallium nitride layer through the gradient layer group, so that the hole blocking capability is enhanced. When positive bias voltage is applied to the grid electrode, the energy band potential barrier of the gradient layer group can inhibit injection of holes from the grid electrode to the two-dimensional electron gas, the height of the potential barrier is firstly increased and then reduced in the direction away from the two-dimensional electron gas, and the gradually-changed potential barrier height can form a corresponding electric field inside to further inhibit injection of the holes. And meanwhile, injection of electrons from the two-dimensional electron gas to the grid electrode is inhibited, so that the leakage current of the grid electrode is reduced, the threshold voltage drift is reduced, and the voltage endurance capability and robustness of the grid electrode are enhanced.

The invention provides a preparation method of a GaN-based power device and the GaN-based power device, in the process of forming the GaN-based power device, when a grid electrode or a passivation layer is formed, the grid electrode layer is passivated to reduce the activation amount of the grid electrode layer; or, when the gate layer is formed, the activation amount of the gate layer is controlled to be gradually reduced from the bottom to the top, so that the hole concentration of doped ions of the gate layer is reduced, and the purpose of reducing the gate leakage current is achieved.

The invention belongs to the technical field of power devices, and provides a trench silicon carbide device and a chip, a P-type shielding region is formed at the bottom of a trench of the trench silicon carbide device, a gate oxide layer of a concave structure is formed on the P-type shielding region, and the gate oxide layer and a field oxide layer form a closed structure wrapping gate polycrystalline silicon. And the first isolation dielectric layer and the second isolation dielectric layer are respectively formed on two sides of the bottom of the gate oxide layer, so that the electric field of the central oxide layer at the bottom of the trench-type gate can be reduced, the gate leakage current phenomenon of the device is reduced, and the reliability of the device is improved.