2results about "Marginal circuit testing" patented technology

Described is a method for connectivity testing of integrated circuits. The method includes connecting an integrated circuit comprising an internal measurement component and a plurality of connection elements to an automated testing apparatus via a first common test channel connected to a first set of non-neighbouring connection elements of the plurality of connection elements and a second common test channel connected to a second set of non-neighbouring connection elements of the plurality of connection elements, different to the first set of non-neighbouring connection elements. The connection elements of the first set of non-neighbouring connection elements neighbour connection elements of the second set of non-neighbouring connection elements. The method further includes connecting a connection element of the plurality of connection elements to the internal measurement component, testing the connected connection element, and identifying a pass or fail for the connected connection element based on the testing. Also described is a system for connectivity testing of integrated circuits, and an adaptor for use with an system for connectivity testing of integrated circuits.

The invention relates to a MOS, BiCMOS or CMOS-based analog circuit (1). The analog circuit (1) is designed to implement a predetermined circuit function in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal, or has an analog signal inside the analog circuit (1). The analog circuit (1) is connected to test logic (38). The test logic (38) is designed to bring the analog circuit (1) into the normal state and into at least a first test state. The analog circuit (1) comprises a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which is designed to perform a function of the analog circuit (1) in accordance with the predetermined circuit function during normal operation. According to the invention, the analog circuit (1) further comprises a second component (S1 to S9; G1 to G9) which is designed to enable the test logic (38) to set a switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in at least the first test state of the analog circuit (1).