110results about "Marginal circuit testing" patented technology

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.

A method of estimating a breakdown voltage of a silicon dioxide film includes; generating breakdown voltage information associated with first test dies selected from among test dies, generating a breakdown voltage estimation model by updating a parameter of a neural network model based on the breakdown voltage information, applying test voltages to second test die selected from among the test dies and distinct from the first dies and receiving currents levels for current generated by the second test dies in response to the test voltages, wherein the test voltages have respective levels lower than levels of breakdown voltages for the first test dies, and estimating breakdown voltages of the second test dies using the breakdown voltage estimation model in relation to the currents levels.

A monitoring circuit includes a sensor circuit having a plurality of devices and a selection circuit, which selects a device to be monitored among the plurality of devices, an input circuit, which applies, based on input digital data, a first signal to the device to be monitored and an output circuit, which generates output digital data based on a second signal generated by the sensor circuit. The input circuit includes a digital-to-analog converter, and the output circuit includes an analog-to-digital converter.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a ±5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise / fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a ±10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise / fall timing and 8 to 12 nanosecond minimum pulse widths.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.

Embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses. The generation method for the chip internal voltage prediction model includes: obtaining a load data set and a relevant index data set of a chip respectively; calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training. The method provided by the embodiments of the present disclosure can predict the situation of the chip internal voltage in advance, so that timely intervention can be made in the operating status of the chip.

In an aspect, a method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test (DUT); providing an input signal to the DUT and measuring the input signal; tracking the measurements over time by overlapping the measured input signal with sequential measurement windows that do not overlap with each other, each measurement window spanning a constant measurement period and a constant signal value range while shifting according to measured changes in the input signal such that each measurement window overlaps at least a portion of the measured input signal corresponding to a preceding measurement window; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining that a settle point has been reached after detecting that the settle count has been met or exceeded by the measured input signal tracked by the sequential measurement windows. Aspects also include an apparatus for adapted performing the aforementioned method and a non-transitory computer storage medium containing instructions that when read by one or more computer processors perform the aforementioned method.

Embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses. The generation method for the chip internal voltage prediction model includes: obtaining a load data set and a relevant index data set of a chip respectively; calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training. The method provided by the embodiments of the present disclosure can predict the situation of the chip internal voltage in advance, so that timely intervention can be made in the operating status of the chip.

Disclosed is a built-in self-test (BIST) methodology of SFQ circuits focused on a novel readout of test signals by using side-channel leakage information. The side-channel leakage can exhibit the dependence of internal data (logical '1' and '0') on the power consumption. By measuring the variations in the power supply of an SFQ circuit at room temperature, the information about internal test signal states can be extracted. As a case study, a rapid SFQ (RSFQ) 4-to-2 priority encoder circuit is considered. The location of faults, which are artificially inserted in circuit-level simulations, is identified by applying the disclosed methodology. The BIST design is compared with a conventional shift register-based readout circuitry. The BIST design can provide 79% lower static power consumption and 65% lower layout area.

The disclosure describes a method, a device, and a system for processing transmission line pulse data. In the method, the component characteristic of a protection component is determined. A voltage-current characteristic generated by applying transmission pulses to the protection component is analyzed based on the transmission line pulse data of the protection component. Based on the design window such as an operation voltage value, a breakdown voltage value, and a required current capability, a corresponding visual graph is generated to determine the characteristic, advantages, and disadvantages of the protection component more accurately.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

A test device for testing the invariability of the output voltage of a voltage regulator with transient loads, and the test device includes a switch connected with a switch drain contact to an output contact of the voltage regulator and with a switch source contact to ground potential, where a load resistance is arranged within this path from the output contact to ground potential, a switch driver connected with a switch driver output contact via a gate resistance to a switch gate contact to change the switch into a connected state, where the voltage regulator is loaded with a variable drain-source resistance of the switch and the load resistor, and to change the switch into a disconnected state, where the voltage regulator is disconnected from the load resistor, and a feedback resistor connected between the switch source contact and an inverted input contact of the switch driver.

An automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads, determining a minimum safe voltage for each of the one or more cores based on the user-specified workloads, and changing the voltage configuration of each of the one or more cores based on the respective minimum safe voltage.

Embodiments of the present disclosure includes a margin measurement circuit to determine margin of one or more signal monitoring circuits. Signals corresponding to voltages, temperatures, or clock signals may monitor deviation above or below trip points. Faults are triggered if the signals deviate outside a range set by the trip points. Margin between actual signal trip points and the set high and low trip points of the monitoring circuits may be measured by a margin measurement circuit. In some embodiments, the set trip points may be optimized for particular electronic system operation conditions. The present techniques may improve an electronic system's ability to detect and prevent remote or local attacks.

A method for detecting the interruption of the connection of the neutral line (6) of a three-phase electric power network, the method being implemented in a processing unit (7A) of an item of electrical equipment (7) connected to the electric power network (1) and comprising the following steps: - acquisition, at a time T, of a first phase voltage (V1), a second phase voltage (V2) and a third phase voltage (V3) measured by a voltage sensor (7D) of the electrical equipment (7); evaluation of a first quantity representative of the ratio of the maximum voltage to the minimum voltage from the first, second and third phase voltages; - if the first quantity is greater than a predetermined threshold: o evaluation of a second quantity based on the first phase voltage, the second phase voltage and the third phase voltage; o detection of the interruption of the neutral line (6) at the time T when the second quantity satisfies a predetermined reference criterion.

A wafer test system includes a chuck for supporting a wafer including a plurality of dies, a probe head for inputting a test signal for an electrical test to the probe card and receiving an electrical test result corresponding to the test signal, a probe card for inputting test signals to the dies through a plurality of pins and receiving test result, a sensing device mounted on the surface of the probe card, for sensing an active state occurring in the wafer when the electrical test is performed, and a determination unit for receiving the electrical test result and the active state information for the dies and determining whether each of the dies has failed using the result of the electrical test on the wafer and active state information.

A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.

The application provides a monitoring circuit, an integrated circuit and a monitoring protection method thereof. The monitoring circuit comprises a quieting filter, a voltage sensor and a latch. The quieting filter is configured to absorb energy of a first voltage signal terminal and a second voltage signal terminal. The voltage sensor is configured to detect a voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the quieting filter absorbs the energy of the first voltage signal terminal and the second voltage signal terminal, and output an adjustment signal to the latch when the voltage fluctuation meets a set condition. The latch is configured to output a first logic state at an output end after receiving the adjustment signal, so as to determine that an electrostatic discharge event occurs. The monitoring circuit of the application monitors the electrostatic discharge event by identifying the change of the power supply voltage, and then triggers a protection mechanism to protect the integrated circuit, thereby avoiding damage to the integrated circuit caused by the electrostatic discharge event.

SOLUTION: In described examples of a device (305) with built-in-self-test, a multiplexer (315) has at least first and second input terminals and is coupled to receive a first input signal (A) at the first input terminal, a second input signal (B) at the second input terminal, and selection signals (S1, S2). Also, the multiplexer (315) is coupled to output: the first input signal (A) in response to a first combination of the selection signals; the second input signal (B) in response to a second combination of the selection signals; and an analog summation of the first and second input signals (A, B) in response to a third combination of the selection signals (S1, S2).SELECTED DRAWING: Figure 3A

Examples relate to control apparatus, a control device, a method and a computer program for determining a device-specific supply voltage for a semiconductor device, and to a corresponding semiconductor device and corresponding systems. The control apparatus is configured to obtain measurement data of measurement circuitry of the semiconductor device, the measurement data being related to a progress of aging of the semiconductor device. The control apparatus is configured to determine the device-specific supply voltage of the semiconductor device based on the measurement data. The control apparatus is configured to provide information on the device-specific supply voltage for a supply voltage control apparatus.

An electrical leakage test structure and an electrical leakage testing method are disclosed. The electrical leakage test structure comprises: a substrate; a first well region and a second well region, which are both formed in the substrate; a first shallow trench isolation structure formed between the second and first well regions; a first source / drain region formed in the first well region; a plurality of second source / drain regions formed in the second well region; and a test gate formed on the substrate. In the electrical leakage testing method, a plurality of electrical leakage test structures with different designed dimensions are tested to perform leakage current evaluation on each electrical leakage test structure, and a designed dimension vs. leakage current relationship is developed based on the leakage current evaluation on each electrical leakage test structure, which reflects whether the internal design of a corresponding semiconductor device is associated with any problem such as parasitic leakage.

A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.

A test device for testing the invariability of the output voltage of a voltage regulator with transient loads, and the test device includes a switch connected with a switch drain contact to an output contact of the voltage regulator and with a switch source contact to ground potential, where a load resistance is arranged within this path from the output contact to ground potential, a switch driver connected with a switch driver output contact via a gate resistance to a switch gate contact to change the switch into a connected state, where the voltage regulator is loaded with a variable drain-source resistance of the switch and the load resistor, and to change the switch into a disconnected state, where the voltage regulator is disconnected from the load resistor, and a feedback resistor connected between the switch source contact and an inverted input contact of the switch driver.

A method (100) for detecting damage to a diode (12) connected in a card chip (11) of a card-shaped data carrier (10) between a first terminal (13) of the card chip (11) and a second terminal (14) of the card chip (11) is disclosed.The method comprises contacting (110) the first terminal (13) and the second terminal (14) of the card chip (11) with corresponding outputs (21, 22) of a voltage source (20), applying (120) an electrical voltage between the first terminal (13) and the second terminal (14) of the card chip (11) via the voltage source (20), determining (130) a current flow through the diode (12) in reverse bias to determine a leakage current value, comparing (140) the leakage current value with a leakage current threshold value, and, based on the comparison of the leakage current value with the leakage current threshold value, determining (150) whether the diode (12) is defective and the card-shaped data carrier (10) is therefore faulty. Furthermore, a test system (200) for carrying out the method (100) is disclosed.

Method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test; input signal to the DUT and measuring the input signal; trackis measurements over time by overlapping measured input signals with sequential measurement windows non-overlapping with each other, each measurement window spanning a constant measurement period and signal value range while shifting to measured changes in the input signal, where each measurement window overlaps at a portion of the measured input signal; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining a settle point has been reached after detecting the settle count has been exceeded by the measured input signal tracked.

An electronic device testing system, including: a standardized control system, an in-circuit tester configured to mate with the standardized control system and a device, a remote cloud system, a user interface, and / or any other suitable components. The user interface can optionally be configured to send a test plan to the remote processing system and / or to receive a test report associated with the device from the remote processing system.

The technology is directed to a di / dt circuit for detecting and measuring the di / dt droops on silicon. The circuit may be calibrated to account for silicon process spread. When a di / dt droop has been detected by the circuit, the magnitude of the droop can be measured by the circuit, allowing the system to determine the best course of action. For instance, when the measured droop is within predetermined limits, the system can continue to operate. However, in the event the measured droop is outside of the limits, the system can take different measures to reduce the clock frequency and therefore reduce the step change in power to prevent SDCs.

Described is a method for connectivity testing of integrated circuits. The method includes connecting an integrated circuit comprising an internal measurement component and a plurality of connection elements to an automated testing apparatus via a first common test channel connected to a first set of non-neighbouring connection elements of the plurality of connection elements and a second common test channel connected to a second set of non-neighbouring connection elements of the plurality of connection elements, different to the first set of non-neighbouring connection elements. The connection elements of the first set of non-neighbouring connection elements neighbour connection elements of the second set of non-neighbouring connection elements. The method further includes connecting a connection element of the plurality of connection elements to the internal measurement component, testing the connected connection element, and identifying a pass or fail for the connected connection element based on the testing.

The invention relates to a built-in self-test (BIST) circuit, an integrated circuit device and a method. A built-in self-test (BIST) circuit includes a first switch, a first resistor, at least one first transistor, and a control circuit. The first switch, the first resistor, and the at least one first transistor are coupled in series between a first supply terminal of a first supply voltage and an I / O terminal of an input / output (I / O) circuit. The control circuit is configured to close the first switch in a first BIST operation, and detect a first leakage current between the I / O terminal and a second power supply terminal of a second power supply voltage different from the first power supply voltage when the first switch is closed.

A system for generating and measuring electrical signals is disclosed. The system includes a digital-to-analog converter module configured to generate one or more analog signals based on a control signal and one or more channels. Each channel includes an output terminal configured to be electrically connected to an electrical device and a buffer circuit. The buffer circuit is configured to receive one of the one or more analog signals and provide a voltage at the output terminal based on a voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow a current to flow between the current source and the output terminal. The system further includes a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of a voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, a current flowing through the output terminal of the channel. A method for generating and measuring electrical signals is also disclosed.