53results about "Marginal circuit testing" patented technology

A method of estimating a breakdown voltage of a silicon dioxide film includes; generating breakdown voltage information associated with first test dies selected from among test dies, generating a breakdown voltage estimation model by updating a parameter of a neural network model based on the breakdown voltage information, applying test voltages to second test die selected from among the test dies and distinct from the first dies and receiving currents levels for current generated by the second test dies in response to the test voltages, wherein the test voltages have respective levels lower than levels of breakdown voltages for the first test dies, and estimating breakdown voltages of the second test dies using the breakdown voltage estimation model in relation to the currents levels.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a ±5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise / fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a ±10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise / fall timing and 8 to 12 nanosecond minimum pulse widths.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.

Embodiments of the present disclosure provide a generation method for a chip internal voltage prediction model, a prediction method, and related apparatuses. The generation method for the chip internal voltage prediction model includes: obtaining a load data set and a relevant index data set of a chip respectively; calibrating the relevant index data set according to a calibration cycle number and obtaining a calibrated relevant index data set; and training the chip internal voltage prediction model based on the load data set and the calibrated relevant index data set, and obtaining the chip internal voltage prediction model with completed training. The method provided by the embodiments of the present disclosure can predict the situation of the chip internal voltage in advance, so that timely intervention can be made in the operating status of the chip.

In an aspect, a method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test (DUT); providing an input signal to the DUT and measuring the input signal; tracking the measurements over time by overlapping the measured input signal with sequential measurement windows that do not overlap with each other, each measurement window spanning a constant measurement period and a constant signal value range while shifting according to measured changes in the input signal such that each measurement window overlaps at least a portion of the measured input signal corresponding to a preceding measurement window; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining that a settle point has been reached after detecting that the settle count has been met or exceeded by the measured input signal tracked by the sequential measurement windows. Aspects also include an apparatus for adapted performing the aforementioned method and a non-transitory computer storage medium containing instructions that when read by one or more computer processors perform the aforementioned method.

The disclosure describes a method, a device, and a system for processing transmission line pulse data. In the method, the component characteristic of a protection component is determined. A voltage-current characteristic generated by applying transmission pulses to the protection component is analyzed based on the transmission line pulse data of the protection component. Based on the design window such as an operation voltage value, a breakdown voltage value, and a required current capability, a corresponding visual graph is generated to determine the characteristic, advantages, and disadvantages of the protection component more accurately.

Embodiments of the present disclosure includes a margin measurement circuit to determine margin of one or more signal monitoring circuits. Signals corresponding to voltages, temperatures, or clock signals may monitor deviation above or below trip points. Faults are triggered if the signals deviate outside a range set by the trip points. Margin between actual signal trip points and the set high and low trip points of the monitoring circuits may be measured by a margin measurement circuit. In some embodiments, the set trip points may be optimized for particular electronic system operation conditions. The present techniques may improve an electronic system's ability to detect and prevent remote or local attacks.

A method for detecting the interruption of the connection of the neutral line (6) of a three-phase electric power network, the method being implemented in a processing unit (7A) of an item of electrical equipment (7) connected to the electric power network (1) and comprising the following steps: - acquisition, at a time T, of a first phase voltage (V1), a second phase voltage (V2) and a third phase voltage (V3) measured by a voltage sensor (7D) of the electrical equipment (7); evaluation of a first quantity representative of the ratio of the maximum voltage to the minimum voltage from the first, second and third phase voltages; - if the first quantity is greater than a predetermined threshold: o evaluation of a second quantity based on the first phase voltage, the second phase voltage and the third phase voltage; o detection of the interruption of the neutral line (6) at the time T when the second quantity satisfies a predetermined reference criterion.

A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.

The application provides a monitoring circuit, an integrated circuit and a monitoring protection method thereof. The monitoring circuit comprises a quieting filter, a voltage sensor and a latch. The quieting filter is configured to absorb energy of a first voltage signal terminal and a second voltage signal terminal. The voltage sensor is configured to detect a voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the quieting filter absorbs the energy of the first voltage signal terminal and the second voltage signal terminal, and output an adjustment signal to the latch when the voltage fluctuation meets a set condition. The latch is configured to output a first logic state at an output end after receiving the adjustment signal, so as to determine that an electrostatic discharge event occurs. The monitoring circuit of the application monitors the electrostatic discharge event by identifying the change of the power supply voltage, and then triggers a protection mechanism to protect the integrated circuit, thereby avoiding damage to the integrated circuit caused by the electrostatic discharge event.

Method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test; input signal to the DUT and measuring the input signal; trackis measurements over time by overlapping measured input signals with sequential measurement windows non-overlapping with each other, each measurement window spanning a constant measurement period and signal value range while shifting to measured changes in the input signal, where each measurement window overlaps at a portion of the measured input signal; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining a settle point has been reached after detecting the settle count has been exceeded by the measured input signal tracked.

The technology is directed to a di / dt circuit for detecting and measuring the di / dt droops on silicon. The circuit may be calibrated to account for silicon process spread. When a di / dt droop has been detected by the circuit, the magnitude of the droop can be measured by the circuit, allowing the system to determine the best course of action. For instance, when the measured droop is within predetermined limits, the system can continue to operate. However, in the event the measured droop is outside of the limits, the system can take different measures to reduce the clock frequency and therefore reduce the step change in power to prevent SDCs.

Described is a method for connectivity testing of integrated circuits. The method includes connecting an integrated circuit comprising an internal measurement component and a plurality of connection elements to an automated testing apparatus via a first common test channel connected to a first set of non-neighbouring connection elements of the plurality of connection elements and a second common test channel connected to a second set of non-neighbouring connection elements of the plurality of connection elements, different to the first set of non-neighbouring connection elements. The connection elements of the first set of non-neighbouring connection elements neighbour connection elements of the second set of non-neighbouring connection elements. The method further includes connecting a connection element of the plurality of connection elements to the internal measurement component, testing the connected connection element, and identifying a pass or fail for the connected connection element based on the testing.

The invention relates to a built-in self-test (BIST) circuit, an integrated circuit device and a method. A built-in self-test (BIST) circuit includes a first switch, a first resistor, at least one first transistor, and a control circuit. The first switch, the first resistor, and the at least one first transistor are coupled in series between a first supply terminal of a first supply voltage and an I / O terminal of an input / output (I / O) circuit. The control circuit is configured to close the first switch in a first BIST operation, and detect a first leakage current between the I / O terminal and a second power supply terminal of a second power supply voltage different from the first power supply voltage when the first switch is closed.

A system for generating and measuring electrical signals is disclosed. The system includes a digital-to-analog converter module configured to generate one or more analog signals based on a control signal and one or more channels. Each channel includes an output terminal configured to be electrically connected to an electrical device and a buffer circuit. The buffer circuit is configured to receive one of the one or more analog signals and provide a voltage at the output terminal based on a voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow a current to flow between the current source and the output terminal. The system further includes a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of a voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, a current flowing through the output terminal of the channel. A method for generating and measuring electrical signals is also disclosed.

A power source emulator is provided for testing programmable switchgear that switches to an alternative three-phase power source upon sensing a failure of a grid source. The emulator provides three simulated three-phase power sources for testing switchgear. Each source is identical in voltage and phase to the current normally distributed by the switchgear but has less than 1% of the amperage. Each power source includes a single three-phase contactor for simultaneously controlling all three phases of the power source, and three solid-state relays for controlling each of the three phases of the power source. A control circuit controls the three-phase contactor and each of the three solid state relays of each power source to simulate various types of power failures that the switchgear is programmed to respond to.

The present disclosure relates to a controller area network, CAN, transceiver, comprising: a transmit data, TXD, interface, a receive data, RXD, interface, a CAN Bus interface, a transmitter, a reducer, and a test unit, wherein a transmitter input of the transmitter is coupled to the TXD interface for receiving a TXD signal, wherein a transmitter output of the transmitter is coupled to a test unit input of the test unit and a first test unit output of the test unit is coupled to the CAN Bus interface, wherein the CAN Bus interface is coupled to a receiver input of the receiver via the reducer, wherein a receiver output of the receiver is coupled to the RXD interface, wherein a second test unit output of the test unit is coupled to the receiver input of the receiver, wherein the test unit is configured to change from a first state to a second state, and vice versa, wherein the test unit is configured, in the first state, to couple the test unit input to the first test unit output and to decouple the test unit input from the second test unit output, wherein the test unit is configured, in the second state, to decouple the test unit input from the first test unit output and to couple the test unit input to the second test unit output. The present disclosure also relates to a method for the CAN transceiver.

Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.

In some aspects, an apparatus includes a processing system that includes one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to send one or more memory access commands to a volatile memory. The one or more memory access commands are associated with a first address. The processing system if further configured to access, based on detecting a row-hammer condition associated with the one or more memory access commands, a physically adjacent row mapping table to determine at least a second address. The first address and the second address correspond to physically adjacent rows within the volatile memory. The processing system if further configured to send one or more row refresh commands to the volatile memory based on the row-hammer condition. The one or more row refresh commands are associated with at least the second address.

This document describes systems and methods for power prediction based leakage screening. In particular, the described systems and methods estimate use case power (e.g., low power, ambient power, high power, gaming power) during a silicon manufacturing process to apply leakage screening for a part (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) can be used for use case power prediction. Using the described methods, a maximum allowed predicted use case power can be determined and used for leakage screening regardless of individual rail leakage or voltage bin assignments.

A built-in self-test (BIST) circuit includes a first switch, a first resistor, at least one first transistor, and a control circuit. The first switch, the first resistor and the at least one first transistor are coupled in series between a first power supply terminal of a first power supply voltage and an input / output (I / O) terminal of an I / O circuit. The control circuit is configured to, in a first BIST operation, close the first switch and, while the first switch is being closed, detect a first leakage current between the I / O terminal and a second power supply terminal of a second power supply voltage different from the first power supply voltage.

A self-diagnostic circuit (BST1) diagnoses an abnormality detection circuit (20) having a first comparator (CMP1) to which a first reference voltage (Vref1) and a voltage based on an abnormality detection target voltage (Vo1) can be inputted. The self-diagnostic circuit has: a voltage switching unit (50) that switches the level of a voltage based on a second reference voltage (Vref2) and outputs same; a first path switching unit (51) that switches between the path on which the voltage outputted from the voltage switching unit is inputted to the first comparator, and the path on which the voltage based on the abnormality detection target voltage is inputted to the first comparator; and a control unit (15) that controls the voltage switching unit and the path switching unit.

The present specification discloses a test device, a test system, a test method, and a test apparatus. The test device provided in the present specification includes an FPGA chip capable of controlling a target power supply that supplies power to an MCU under test. In practice, different test logic programs can be configured in the FPGA chip based on actual needs, to satisfy a need of flexibly testing different types of MCUs under test. In addition, the FPGA chip in the test device can be used to generate a high-frequency clock signal, to ensure time accuracy when voltage glitch faults are injected into the MCU under test, so as to further ensure a test effect for the MCU under test.

A sensing electronic device includes a substrate, and a reference voltage control unit. The sensing array is arranged on the substrate, and includes a first sensing electrode and a second sensing electrode. The reference voltage control unit is electrically connected to the sensing array. In an operation period, the reference voltage control unit has a first voltage, the first sensing electrode has a second voltage, and the second sensing electrode has a third voltage, wherein a difference between the first voltage and the second voltage is different from a difference between the first voltage and the third voltage.

The invention relates to a data-based state monitoring method for monitoring a grid-side component, in particular to a computer-implemented method, a computer-implemented device, a computer program product and a system for determining a degradation progress of a load following a power converter and / or an intermediate circuit, the computer-implemented method comprises: acquiring a time profile of a control variable, the control variable being determined for controlling an output voltage and / or an output current of the power converter and / or the intermediate circuit, and wherein the output voltage and / or the output current are determined for supply to a load; determining the amplitude of at least one higher harmonic of the fundamental oscillation of the acquired time curve; comparing the amplitude to a reference amplitude, where the reference amplitude is associated with a known progress of degradation of the load; and determine a degradation progress of the load based on the comparison.

An apparatus for measuring electrical characteristics of a test system includes a base board and an interface. The base board is arranged to host circuit boards. Each circuit board includes a measurement module. The base board includes an interface configured to connect with the test system. The interface is arranged to receive a current, on a current channel, from the test system, and voltages, on respective voltage channels, from the test system. The circuit boards include one or more voltage testing modules. Each voltage testing module includes voltage measurement units. Each voltage measurement unit is configured to measure a voltage on a respective voltage channel. The circuit boards include a current testing module configured to measure a current on the current channel. The interface is arranged to output voltage information from the one or more voltage testing modules and current information from the current testing module.

An apparatus for measuring a gate leakage current of a MOSFET. The apparatus includes a current mirror adapted to be connected to a gate of a MOSFET, a gate driver adapted to generate a driving signal for the MOSFET, and a sensing resistor connected to the current mirror. An input current path of the current mirror is adapted to receive a gate leakage current of the MOSFET. The current mirror provides a high sensitivity of the measurement because the voltage across the current mirror is nearly constant, which therefore caters for different situations no matter if the gate leakage current is high or low.

A computer-implemented method for determining a degradation progression of a load connected downstream of a power converter or of an intermediate circuit includes measuring a time profile of a control variable controlling an output voltage or an output current of the power converter or of the intermediate circuit supplied to the load, determining an amplitude of at least one higher harmonic of a fundamental oscillation of the captured time profile, comparing the amplitude with a reference amplitude associated with a known degradation progression of the load; and determining the degradation progression of the load based on the comparison. A computer-implemented apparatus, a computer program product and a system for determining a degradation progression of a load connected downstream of the power converter and / or the intermediate circuit are also disclosed.

A measurement apparatus is described which has a base board to host a plurality of circuit boards containing measurement circuitry for measuring current and voltage information of a device under test, on a plurality of channels. The apparatus is suitable for mounting in a test rack as a modular system for measuring electrical parameters of a plurality of devices during electromagnetic compatibility tests.

Solid state ESD SIC simulator. An electrostatic discharge (ESD) test system includes a FET-based pulse generator that uses a pair of back-to-back FETs coupled to generate an ESD pulse based on discharging a capacitor coupled in series with a device under test (DUT). A number of FETs can be selected based on an expected ESD test voltage amplitude.