7 results about "Temperature instability" patented technology

An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and / or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is / are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

A bias temperature instability (BTI) measurement system is disclosed. One example includes a method for performing a BTI test procedure (106) of a DUT (110). The method includes coupling a contact pad of a DUT circuit (112) to a test device (102). The DUT circuit (112) includes a differential input stage and a gain stage. The differential input stage includes a differential pair of transistors fabricated to match the DUT (110). The method also includes providing a BTI stress from the test apparatus (102) to one of the differential pairs of transistor devices to simulate BTI aging of a respective one of the differential pairs of transistors. The method also includes providing a differential input voltage from the test device (102) to the differential input stage. The method further includes measuring, via the test apparatus (102), an output voltage at an output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

A delay circuit with bias temperature instability (BTI) mitigation includes an input node; an output node configured to provide a delayed output signal that is a delayed representation of an input signal; a first inverter stage including a first complementary metal-oxide-semiconductor (CMOS) inverter and a resistive-capacitive (RC) delay circuit configured to provide an RC delay for a signal transition of the input signal, wherein the RC delay circuit includes a resistive network of transistors coupled between a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor of the first CMOS inverter; a second inverter stage including a second CMOS inverter coupled between the first inverter stage and the output node; and a supply cutoff circuit configured to disconnect the resistive network of transistors and / or the second CMOS inverter from respective voltage supplies based on one or more supply cutoff conditions being satisfied.

A reservoir computing method (700) and related system (100) are disclosed. The reservoir computing system includes at least one non-linear computing node (103) with a computing node MOSFET (113), a drive circuit (110) coupled with the at least one non-linear computing node (103), and a readout unit (104) for acquiring an output sequence associated with the at least one non-linear computing node (103). The MOSFET has charge trapping sites positioned in a gate dielectric that exhibit a bias temperature instability when subjected to a voltage stress and exhibit a threshold voltage recovery after removal of the voltage stress. The drive circuit is configured to apply an input pulse and a readout pulse to a gate of the MOSFET. The readout unit (104) is configured to detect a current flowing through a channel region of the MOSFET when the drive circuit is applying the readout pulse. The readout pulse has a smaller voltage amplitude than the input pulse.

The invention discloses an inverter, an inverter module and a control method of the inverter, the inverter comprises a first transistor and a second transistor, the grid electrode of the first transistor is connected to a first input end, and the grid electrode of the second transistor is connected to a second input end; a first node is arranged between the first input end and the grid electrode of the first transistor, and a second node is arranged between the second input end and the grid electrode of the second transistor; the bias temperature instability recovery unit is respectively connected to a first node and a second node and is used for enabling the first node and the second node to be connected when the first transistor and the second transistor are in a working state; and when the first transistor and the second transistor are in a recovery state, the first node and the second node are disconnected, a first recovery voltage signal is provided for the first node, and a second recovery voltage signal is provided for the second node. The inverter is capable of recovering bias temperature instability of the inverter.

One example includes a method for performing a BTI test process of DUTs. The method includes coupling contact pads of a DUT circuit to testing equipment. The DUT circuit includes a differential input stage and a gain stage. The differential input stage include a differential pair of transistors that are fabrication matched to the DUTs. The method also includes providing a BTI stress from the testing equipment to one of the differential pair of transistor devices to simulate BTI aging of the respective one of the differential pair of the transistors. The method also includes providing a differential input voltage from the testing equipment to the differential input stage. The method further includes measuring an output voltage at an output of the gain stage via the testing equipment in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.