27 results about "Temperature instability" patented technology

The invention discloses a thermal power generating unit peak regulation control method and device, electronic equipment and a storage medium, and can integrate historical data, real-time parameters and external environment variables of a thermal power generating unit peak regulation operation interval, and construct a unit peak regulation state multi-dimensional representation space through time alignment and feature extraction. A dynamic response model reflecting actual operation characteristics of equipment is established, pre-compensation and dynamic correction can be performed on a peak regulation instruction, nonlinear time-varying characteristics of a boiler, a steam turbine and an auxiliary engine link are fully considered, and limitation of a layered decoupling control framework is avoided, so that the problem that existing layered decoupling control neglects the nonlinear time-varying characteristics of the equipment, and the nonlinear time-varying characteristics of the boiler, the steam turbine and the auxiliary engine link are not fully considered can be solved. According to the method, the technical problems of model prediction precision degradation, reheater temperature instability and other cascading failures caused by thermal power generating unit peak regulation are solved, and the technical effects that the thermal power generating unit peak regulation model prediction precision is improved, cascading failures in the peak regulation process are prevented, the unit peak regulation operation stability is guaranteed, and the regulation capacity of a thermal power generating unit in a new energy high-permeability power grid is enhanced are achieved.

The invention provides a method for improving negative bias temperature instability of a PMOS (P-channel Metal Oxide Semiconductor) device, which is characterized in that a silicon nitride thin film layer with tensile stress is prepared by adopting a furnace tube deposition process, the silicon nitride furnace tube deposition process is characterized in that a reaction gas source is heated and decomposed at high temperature to carry out chemical reaction, and ions in the process belong to thermal motion; therefore, the surface of the substrate does not have large acceleration, bombardment of reaction source ions to the gate dielectric layer of the PMOS device in the chemical reaction process can be effectively reduced or even avoided, the risk of damage to the gate dielectric layer of the PMOS device is reduced, and the effect of improving NBTI of the PMOS device is achieved.

The invention relates to a manufacturing method of a CMOS (Complementary Metal Oxide Semiconductor) device, which optimizes the manufacturing process of a tensile stress film and a compressive stress film and ensures that an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) can adopt a stress technology at the same time. The stress films (the tensile stress film and the pressure stress film) corresponding to the NMOS area and the PMOS area are subjected to ultraviolet curing treatment, H in the films is removed, the H is prevented from entering the device during subsequent annealing, the short-channel effect is weakened, the negative bias temperature instability is relieved, the device performance is improved, and the reliability of the device during working is guaranteed.

The invention belongs to the technical field of integrated circuits, and particularly relates to a multi-port on-chip interconnection reliability analysis method. According to the method, a key path of on-chip interconnection is evaluated by establishing a multi-port on-chip interconnection physical model; the delay change of a gate on a critical path under the action of an NBTI effect is estimated by calculating the port utilization rate according to the working load condition, and the service life of the multi-port on-chip interconnection is predicted, namely, the time of failure caused by the fact that the delay exceeds an allowable range after long-term working of the multi-port on-chip interconnection is estimated. When the influence of a reverse bias temperature instability (NBTI) effect on the service life of the circuit is evaluated, a physical implementation method of a regular layout multi-port on-chip interconnection data path is considered, and the port utilization rate is calculated according to a port access conflict probability model. According to the method, accurate critical path estimation is obtained through a physical model, and efficient analysis of the reliability of the multi-port on-chip interconnection is realized in combination with an efficient port utilization rate calculation method.

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

The present disclosure relates to power saving mode switching that prevents bias temperature instability. Systems and methods for introducing a switching signal in a command pipeline configured to receive a plurality of command types for a memory device. Switching circuitry is configured to introduce the switching signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline does not contain a valid command. When a command that is not valid in the power saving mode is asserted during the power saving mode, the switching is prevented from causing a write by disabling data strobe.

The utility model relates to the technical field of material mechanical property testing, in particular to a metal cold and hot fatigue testing device in a molten salt environment. The device comprises a container device, a cooling device, a cold and hot fatigue device, a push-pull device, a connecting support device and a central control panel, the cold and hot fatigue device enables the test process to be closer to the actual working condition through independent arrangement of a high-temperature area and a low-temperature area, the problems of prolonged test period, unstable temperature and the like caused by frequent heating and cooling can be avoided, and the test efficiency is improved. A cooling device is arranged between the high-temperature area and the low-temperature area, the cooling process is accelerated, and the test period is further shortened; meanwhile, the central control panel is linked with the cooling device, the cold and hot fatigue device and the push-pull device, so that automatic control can be realized, manual intervention is reduced, and the test accuracy and efficiency are improved.

The embodiment of the present disclosure provides a protection circuit, a protection method and a semiconductor memory, the protection circuit comprising a power supply module, a switch module and a delay phase-locked loop module, wherein: one end of the switch module is connected with the power supply module, the other end of the switch module is connected with the delay phase-locked loop module, and the control end of the switch module receives a mode control signal, and the mode control signal is used for controlling the switch module to be in an off state in an aging mode, so that the power supply module is disconnected with the delay phase-locked loop module. In this way, by receiving the mode control signal at the control end of the switch module, the switch module is in the off state in the aging mode, so that the power supply module is disconnected with the delay phase-locked loop module, so that the delay phase-locked loop module can be prevented from accelerating voltage, the protection of the delay phase-locked loop module under the negative bias temperature instability effect can be realized, and the test power consumption can be reduced.

Circuit (100), comprising: a first vibration damping circuit (104P) coupled between an input / output pad (102) and a buffer circuit (106), wherein the first vibration damping circuit (104P) comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain; and a second vibration damping circuit (104N) coupled between the input / output pad and the buffer circuit (106), wherein the first vibration damping circuit (104P) is configured to increase a voltage received by corresponding gates of a first subset of transistors of the buffer circuit (106) when a voltage applied to the input / output pad (102) is equal to a first supply voltage, and the second vibration damping circuit (104N) is configured to decrease a voltage received by respective gates of a second subset of transistors of the buffer circuit (106) when the voltage applied to the input / output pad (102) is equal to a second supply voltage.

The invention belongs to the technical field of semiconductor materials, and relates to a preparation method of a large-size high-performance single crystal, which at least comprises the following steps: S1, material preparation and melting, S2, seeding and necking, S3, shouldering: carrying out gradient shouldering after necking is completed, S4, rotating the shouldering, S5, carrying out diameter equalization: carrying out gradient pressurization and diameter equalization, S6, ending, and S7, annealing: carrying out two-stage annealing treatment on the crystal in a furnace. According to the method, through temperature segmented regulation and control of gradient shouldering, the problems of edge breakage, dislocation proliferation and the like easily caused by misalignment of temperature-pulling speed coupling control in a traditional process are solved, and the shouldering success rate in the crystal preparation process is greatly increased. According to the invention, the problem of temperature instability in the prior art is systematically solved through temperature control at three different stages, and the overall crystal quality is improved.

An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and / or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is / are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

The present invention discloses a method and device for evaluating the performance of a field-effect transistor containing black phosphorus. The method specifically includes the following steps: preparing a field-effect transistor containing black phosphorus; giving a transmission model of the field-effect transistor through electrical characteristic measurement under a first controllable environmental variable; obtaining bias temperature instability data and analyzing the failure behavior; combining the characterization of channel defects and surface potential to optimize the transmission model of the field-effect transistor and the analysis of the failure behavior; and realizing the performance evaluation of the field-effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior. The present invention combines electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential, and gives an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of the field-effect transistor device structure, and the optimization of the manufacturing process in the field-effect transistor containing black phosphorus.

A bias temperature instability (BTI) measurement system is disclosed. One example includes a method for performing a BTI test procedure (106) of a DUT (110). The method includes coupling a contact pad of a DUT circuit (112) to a test device (102). The DUT circuit (112) includes a differential input stage and a gain stage. The differential input stage includes a differential pair of transistors fabricated to match the DUT (110). The method also includes providing a BTI stress from the test apparatus (102) to one of the differential pairs of transistor devices to simulate BTI aging of a respective one of the differential pairs of transistors. The method also includes providing a differential input voltage from the test device (102) to the differential input stage. The method further includes measuring, via the test apparatus (102), an output voltage at an output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface therebetween, incorporating a modifying ion at the first interface, the modifying ion being bonded with an ion in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than before the modifying ion is incorporated, the first chemical bond formed by a defect ion and an ion in the gate dielectric layer (or the gate oxide layer) at the first interface being less likely to be broken, reducing the probability of interface trap charge, thereby reducing the interface state density, reducing the threshold voltage and the saturated drain current of the device from drifting, and improving the negative bias temperature instability.

A delay circuit with bias temperature instability (BTI) mitigation includes an input node; an output node configured to provide a delayed output signal that is a delayed representation of an input signal; a first inverter stage including a first complementary metal-oxide-semiconductor (CMOS) inverter and a resistive-capacitive (RC) delay circuit configured to provide an RC delay for a signal transition of the input signal, wherein the RC delay circuit includes a resistive network of transistors coupled between a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor of the first CMOS inverter; a second inverter stage including a second CMOS inverter coupled between the first inverter stage and the output node; and a supply cutoff circuit configured to disconnect the resistive network of transistors and / or the second CMOS inverter from respective voltage supplies based on one or more supply cutoff conditions being satisfied.

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.

A reservoir computing method (700) and related system (100) are disclosed. The reservoir computing system includes at least one non-linear computing node (103) with a computing node MOSFET (113), a drive circuit (110) coupled with the at least one non-linear computing node (103), and a readout unit (104) for acquiring an output sequence associated with the at least one non-linear computing node (103). The MOSFET has charge trapping sites positioned in a gate dielectric that exhibit a bias temperature instability when subjected to a voltage stress and exhibit a threshold voltage recovery after removal of the voltage stress. The drive circuit is configured to apply an input pulse and a readout pulse to a gate of the MOSFET. The readout unit (104) is configured to detect a current flowing through a channel region of the MOSFET when the drive circuit is applying the readout pulse. The readout pulse has a smaller voltage amplitude than the input pulse.

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.

Examples of input stages of circuits are configured to reduce both negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) in PMOS transistors therein. Current-switched PMOS source follower transistors and a low-side NMOS differential pair is used to process a lower range of a rail-to-rail input signal range of a circuit. A PMOS source follower is disposed between the positive input of the circuit and the positive input of the low-side NMOS differential pair. Another PMOS source follower is disposed between the negative input of the circuit and the negative input of the low-side NMOS differential pair. Various arrangements are provided for generating and maintaining the bias currents of the two PMOS source followers to be approximately the same through the entire lower input signal range.

The invention discloses development of a coplanar waveguide ferromagnetic resonance measurement and multifunctional magnetoelectric measurement platform based on coil modulation microwaves of a phase-locked amplifier, and mainly relates to the technical field of ferromagnetic resonance testing. The measurement precision of ferromagnetic resonance is improved through a series of settings, the sample table and the connecting column are made of high-heat-conductivity red copper and have good heat conduction, high-precision temperature control is provided through the compressor, the heating resistor and the temperature sensor, the precision can reach 0.005 K, and noise caused by unstable temperature is reduced; the high vacuum environment prevents the sample from being oxidized, provides a stable test environment, and provides a basis for low-temperature measurement. The coplanar waveguide designed by the invention has good impedance matching, so that a sample can be fully acted by a microwave alternating magnetic field.

The invention provides a threshold voltage adjusting method and manufacturing method of a semiconductor device and the semiconductor device, and the adjusting method comprises the steps: providing a substrate, and forming a gate oxide layer in the semiconductor device on the substrate; and performing hydrogen plasma treatment on the gate oxide layer to adjust the effective work function of the semiconductor device. The effective work function of the semiconductor device is adjusted by performing hydrogen ion treatment on the gate oxide layer, so that the threshold voltage of the semiconductor device is adjusted, meanwhile, the negative bias temperature instability can be improved, and compared with the prior art, the threshold voltage adjusting efficiency is improved, the performance of the semiconductor device is improved, and the manufacturing cost of the semiconductor device is reduced. And the service life of the semiconductor device is prolonged.

The invention discloses an inverter, an inverter module and a control method of the inverter, the inverter comprises a first transistor and a second transistor, the grid electrode of the first transistor is connected to a first input end, and the grid electrode of the second transistor is connected to a second input end; a first node is arranged between the first input end and the grid electrode of the first transistor, and a second node is arranged between the second input end and the grid electrode of the second transistor; the bias temperature instability recovery unit is respectively connected to a first node and a second node and is used for enabling the first node and the second node to be connected when the first transistor and the second transistor are in a working state; and when the first transistor and the second transistor are in a recovery state, the first node and the second node are disconnected, a first recovery voltage signal is provided for the first node, and a second recovery voltage signal is provided for the second node. The inverter is capable of recovering bias temperature instability of the inverter.

One example includes a method for performing a BTI test process of DUTs. The method includes coupling contact pads of a DUT circuit to testing equipment. The DUT circuit includes a differential input stage and a gain stage. The differential input stage include a differential pair of transistors that are fabrication matched to the DUTs. The method also includes providing a BTI stress from the testing equipment to one of the differential pair of transistor devices to simulate BTI aging of the respective one of the differential pair of the transistors. The method also includes providing a differential input voltage from the testing equipment to the differential input stage. The method further includes measuring an output voltage at an output of the gain stage via the testing equipment in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

This invention discloses a method for calculating transistor aging stress based on an analytical model. It is an analytical formula automatic generation method applicable to transistors with aging mechanisms of bias temperature instability (BTI) and hot carrier degradation (HCD). The analytical model of this invention calculates the stress of the internal transistor based on statistical dynamic information such as duty factor (DF) and toggle rate (TR) obtained from gate-level simulation. The analytical formula used is automatically generated through transistor-level logic simulation and supports stress analysis for different aging mechanisms.

The application discloses a MOS field effect transistor failure physical model migration learning method, a storage medium and equipment, and belongs to the technical field of MOS field effect transistor bias temperature instability failure physical modeling. In order to solve the problem that the existing migration learning method cannot perform migration learning on the failure mechanism derivation law of the MOS field effect transistor failure physical model, thereby leading to an unsatisfactory model effect after migration, the application combines historical data and a simulation analysis method, constructs different candidate source field correlation models, determines key parameters affecting failure physical model coefficients, then calculates the distance between different candidate source fields and a target field according to the correlation models, and constructs a MOS field effect transistor migration discriminant criterion; then, an electronic component failure physical parameter identification model of the candidate source field is established, and based on the migration domain discriminant criterion, an instance migration learning method is adopted to construct a parameter identification model of the failure physical model coefficients of the target field and the affected failure physical model coefficients.