44 results about "Temperature instability" patented technology

The invention discloses an accelerated degradation model of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) under alternating gate drive, which takes gate negative bias voltage, junction temperature, multiple stresses of gate voltage rise time and switching times as inputs and threshold voltage variation as outputs, solves the problem of inaccurate threshold voltage drift prediction of the SiC MOSFET under alternating-current BTI (Bias Temperature Instability), and improves the prediction accuracy of the SiC MOSFET under alternating-current BTI. The method can be used for describing the SiC MOSFET threshold voltage degradation rule in the alternating gate drive mode. According to the invention, the change rule of key performance parameters in the long-term use process of the SiC MOSFET device can be reflected, and the method has important significance for accurately evaluating and optimizing and improving the use reliability of the device.

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

The invention discloses an MOS field effect transistor failure physical model transfer learning method, a storage medium and equipment, and belongs to the technical field of MOS field effect transistor bias temperature instability failure physical modeling. The objective of the invention is to solve the problem that an existing transfer learning method cannot carry out transfer learning on a failure mechanism development rule of an MOS field effect transistor failure physical model, so that the effect of a migrated model is not ideal. According to the method, historical data and a simulation analysis method are combined, multiple correlation models of different candidate source fields are constructed, key parameters influencing failure physical model coefficients are determined, then according to the multiple correlation models, the distances between the different candidate source fields and a target field are calculated, and a mobility judgment criterion of the MOS field effect transistor is constructed; secondly, establishing an electronic component failure physical parameter identification model in the candidate source field, and constructing a parameter identification model of a target domain and a failure physical model coefficient influenced by the target domain by adopting an instance transfer learning method based on a transferable domain discrimination criterion;

The invention discloses a chip high and low temperature test method based on multi-point acquisition, and the method specifically comprises the following steps: 1, carrying out the real-time data analysis of the temperature of a chip through a dynamic temperature control array, and adjusting the working state of a temperature control unit; 2, constructing a three-dimensional temperature monitoring network, deploying a plurality of high-precision temperature sensors in a three-dimensional space on the surface of the chip and around the chip, capturing the spatial distribution and change of the temperature in real time, and importing three-dimensional temperature data into visual software to generate a real-time three-dimensional temperature distribution diagram; through intelligent control and self-adaptive adjustment, precise control of local temperature is realized, the problem of temperature instability is effectively solved, the accuracy and reliability of testing are improved, meanwhile, an omnibearing temperature monitoring system is constructed, spatial distribution and change of temperature can be captured in real time, and the accuracy and reliability of testing are improved. Powerful support is provided for identifying and correcting temperature nonuniformity, and temperature measurement errors caused by direct contact between the temperature sensor and the chip are avoided.

The invention discloses a thermal power generating unit peak regulation control method and device, electronic equipment and a storage medium, and can integrate historical data, real-time parameters and external environment variables of a thermal power generating unit peak regulation operation interval, and construct a unit peak regulation state multi-dimensional representation space through time alignment and feature extraction. A dynamic response model reflecting actual operation characteristics of equipment is established, pre-compensation and dynamic correction can be performed on a peak regulation instruction, nonlinear time-varying characteristics of a boiler, a steam turbine and an auxiliary engine link are fully considered, and limitation of a layered decoupling control framework is avoided, so that the problem that existing layered decoupling control neglects the nonlinear time-varying characteristics of the equipment, and the nonlinear time-varying characteristics of the boiler, the steam turbine and the auxiliary engine link are not fully considered can be solved. According to the method, the technical problems of model prediction precision degradation, reheater temperature instability and other cascading failures caused by thermal power generating unit peak regulation are solved, and the technical effects that the thermal power generating unit peak regulation model prediction precision is improved, cascading failures in the peak regulation process are prevented, the unit peak regulation operation stability is guaranteed, and the regulation capacity of a thermal power generating unit in a new energy high-permeability power grid is enhanced are achieved.

A bias temperature instability recovery circuit and recovery method of an inverter, the bias temperature instability recovery circuit of the inverter comprising: a first recovery unit coupled to a first transistor, applying a first recovery voltage signal to a well region of the first transistor when the first transistor is in a recovery state, and applying a second recovery voltage signal to a well region of the first transistor when the first transistor is in a recovery state; the first transistor is used for performing first bias temperature instability recovery on the first transistor; and the second recovery unit is coupled with the second transistor, and when the second transistor is in a recovery state, a second recovery voltage signal is applied to the well region of the second transistor so as to carry out second bias temperature instability recovery on the second transistor. According to the technical scheme, bias temperature instability recovery of the first transistor and the second transistor in the phase inverter can be achieved at the same time, the electrical performance of the phase inverter is improved correspondingly, and the aging speed of the phase inverter is delayed.

Methods, systems, and devices for techniques for clock doubling are described. A clock adjustment circuit may receive as inputs two clock signals that each have the same frequency and different phases and may generate a clock signal with a higher frequency than the two clock signal inputs. A duty cycle monitor may monitor and support correction of a shift in the relative phases of the two input clocks to maintain a consistent duty cycle of the generated higher frequency clock signal. The clock adjustment circuit may reduce the length of a clock tree that is traversed by the higher frequency clock, such as to reduce bias temperature instability degradation or other types of signal degradation.

The invention provides a method for improving negative bias temperature instability of a PMOS (P-channel Metal Oxide Semiconductor) device, which is characterized in that a silicon nitride thin film layer with tensile stress is prepared by adopting a furnace tube deposition process, the silicon nitride furnace tube deposition process is characterized in that a reaction gas source is heated and decomposed at high temperature to carry out chemical reaction, and ions in the process belong to thermal motion; therefore, the surface of the substrate does not have large acceleration, bombardment of reaction source ions to the gate dielectric layer of the PMOS device in the chemical reaction process can be effectively reduced or even avoided, the risk of damage to the gate dielectric layer of the PMOS device is reduced, and the effect of improving NBTI of the PMOS device is achieved.

The invention relates to a manufacturing method of a CMOS (Complementary Metal Oxide Semiconductor) device, which optimizes the manufacturing process of a tensile stress film and a compressive stress film and ensures that an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) can adopt a stress technology at the same time. The stress films (the tensile stress film and the pressure stress film) corresponding to the NMOS area and the PMOS area are subjected to ultraviolet curing treatment, H in the films is removed, the H is prevented from entering the device during subsequent annealing, the short-channel effect is weakened, the negative bias temperature instability is relieved, the device performance is improved, and the reliability of the device during working is guaranteed.

The invention belongs to the technical field of integrated circuits, and particularly relates to a multi-port on-chip interconnection reliability analysis method. According to the method, a key path of on-chip interconnection is evaluated by establishing a multi-port on-chip interconnection physical model; the delay change of a gate on a critical path under the action of an NBTI effect is estimated by calculating the port utilization rate according to the working load condition, and the service life of the multi-port on-chip interconnection is predicted, namely, the time of failure caused by the fact that the delay exceeds an allowable range after long-term working of the multi-port on-chip interconnection is estimated. When the influence of a reverse bias temperature instability (NBTI) effect on the service life of the circuit is evaluated, a physical implementation method of a regular layout multi-port on-chip interconnection data path is considered, and the port utilization rate is calculated according to a port access conflict probability model. According to the method, accurate critical path estimation is obtained through a physical model, and efficient analysis of the reliability of the multi-port on-chip interconnection is realized in combination with an efficient port utilization rate calculation method.

The voltage at the input of an electronic device is regulated by performing at least the following: receiving a monitoring voltage corresponding to a power system at a voltage monitoring circuit (210), determining at the voltage monitoring circuit whether the monitoring voltage is equal to or exceeds a monitoring threshold voltage, (204) receiving an output at the voltage monitoring circuit indicating whether an input reference voltage at a comparator circuit is different from an input feedback voltage, (218) adjusting a feedback voltage at the voltage monitoring circuit to match the input reference voltage, (204), and providing the feedback voltage from the voltage monitoring circuit to the comparator circuit (220) as an updated input feedback voltage.

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

The present disclosure relates to power saving mode switching that prevents bias temperature instability. Systems and methods for introducing a switching signal in a command pipeline configured to receive a plurality of command types for a memory device. Switching circuitry is configured to introduce the switching signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline does not contain a valid command. When a command that is not valid in the power saving mode is asserted during the power saving mode, the switching is prevented from causing a write by disabling data strobe.

A method including: Receiving timing data of multiple data paths of an integrated circuit (IC) design. Simulating degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation includes: simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency; simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and / or time-dependent dielectric breakdown (TDDB); and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, outputs a time series of values of a worst-case remaining margin of the multiple data paths.

The utility model relates to the technical field of material mechanical property testing, in particular to a metal cold and hot fatigue testing device in a molten salt environment. The device comprises a container device, a cooling device, a cold and hot fatigue device, a push-pull device, a connecting support device and a central control panel, the cold and hot fatigue device enables the test process to be closer to the actual working condition through independent arrangement of a high-temperature area and a low-temperature area, the problems of prolonged test period, unstable temperature and the like caused by frequent heating and cooling can be avoided, and the test efficiency is improved. A cooling device is arranged between the high-temperature area and the low-temperature area, the cooling process is accelerated, and the test period is further shortened; meanwhile, the central control panel is linked with the cooling device, the cold and hot fatigue device and the push-pull device, so that automatic control can be realized, manual intervention is reduced, and the test accuracy and efficiency are improved.

A reservoir computing method (700) and related system (100) are disclosed. The reservoir computing system comprises at least one nonlinear compute node (103) with compute node MOSFET (113), a driver circuit(110) coupled to the at least one nonlinear compute node (103), and a readout unit (104) for acquiring an output sequence related to the at least one nonlinear compute node (103). The MOSFET has charge trapping sites located in a gate dielectric and displays bias temperature instability when subjected to voltage stress and threshold voltage recovery after removal of the voltage stress. The driver unit is configured to apply input pulses and readout pulses to a gate of the MOSFET. The readout unit (104) is configured to detect a current through a channel region of the MOSFET while the driver circuit is applying the readout pulses. The readout pulses have a smaller voltage amplitude compared to the input pulses.

A reservoir computing method (700) and related system (100) are disclosed. The reservoir computing system comprises at least one nonlinear compute node (103) with compute node MOSFET (113), a driver circuit (110) coupled to the at least one nonlinear compute node (103), and a readout unit (104) for acquiring an output sequence related to the at least one nonlinear compute node (103). The MOSFET has charge trapping sites located in a gate dielectric and displays bias temperature instability when subjected to voltage stress and threshold voltage recovery after removal of the voltage stress. The driver unit is configured to apply input pulses and readout pulses to a gate of the MOSFET. The readout unit (104) is configured to detect a current through a channel region of the MOSFET while the driver circuit is applying the readout pulses. The readout pulses have a smaller voltage amplitude compared to the input pulses.

A p-channel metal oxide semiconductor (pMOS) transistor includes a gate stack, the gate stack including: a dielectric interlayer containing silicon oxide on a substrate, wherein the thickness of the dielectric interlayer is less than 1 nm; a high-k dielectric layer having a higher dielectric constant than the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the substrate, wherein the thickness of the first dipole-forming capping layer is less than 2 nm; and at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and high reliability without the use of reliability annealing, which makes the pMOS transistor suitable for use as a back-end-of-line (BEOL) device.

The embodiment of the present disclosure provides a protection circuit, a protection method and a semiconductor memory, the protection circuit comprising a power supply module, a switch module and a delay phase-locked loop module, wherein: one end of the switch module is connected with the power supply module, the other end of the switch module is connected with the delay phase-locked loop module, and the control end of the switch module receives a mode control signal, and the mode control signal is used for controlling the switch module to be in an off state in an aging mode, so that the power supply module is disconnected with the delay phase-locked loop module. In this way, by receiving the mode control signal at the control end of the switch module, the switch module is in the off state in the aging mode, so that the power supply module is disconnected with the delay phase-locked loop module, so that the delay phase-locked loop module can be prevented from accelerating voltage, the protection of the delay phase-locked loop module under the negative bias temperature instability effect can be realized, and the test power consumption can be reduced.

Circuit (100), comprising: a first vibration damping circuit (104P) coupled between an input / output pad (102) and a buffer circuit (106), wherein the first vibration damping circuit (104P) comprises a first p-type metal-oxide-semiconductor field-effect transistor driven by a first bias voltage and a second p-type metal-oxide-semiconductor field-effect transistor with the first bias voltage applied to its drain; and a second vibration damping circuit (104N) coupled between the input / output pad and the buffer circuit (106), wherein the first vibration damping circuit (104P) is configured to increase a voltage received by corresponding gates of a first subset of transistors of the buffer circuit (106) when a voltage applied to the input / output pad (102) is equal to a first supply voltage, and the second vibration damping circuit (104N) is configured to decrease a voltage received by respective gates of a second subset of transistors of the buffer circuit (106) when the voltage applied to the input / output pad (102) is equal to a second supply voltage.

The invention belongs to the technical field of semiconductor materials, and relates to a preparation method of a large-size high-performance single crystal, which at least comprises the following steps: S1, material preparation and melting, S2, seeding and necking, S3, shouldering: carrying out gradient shouldering after necking is completed, S4, rotating the shouldering, S5, carrying out diameter equalization: carrying out gradient pressurization and diameter equalization, S6, ending, and S7, annealing: carrying out two-stage annealing treatment on the crystal in a furnace. According to the method, through temperature segmented regulation and control of gradient shouldering, the problems of edge breakage, dislocation proliferation and the like easily caused by misalignment of temperature-pulling speed coupling control in a traditional process are solved, and the shouldering success rate in the crystal preparation process is greatly increased. According to the invention, the problem of temperature instability in the prior art is systematically solved through temperature control at three different stages, and the overall crystal quality is improved.

An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.

The invention discloses a performance evaluation method and device for a field effect transistor containing black phosphorus. The method specifically comprises the following steps: preparing the field effect transistor containing black phosphorus; providing a transmission model of the field effect transistor by measuring the electrical characteristics of the first controllable environment variable; acquiring bias temperature instability data, and analyzing a failure behavior; the transmission model of the field effect transistor is optimized and the failure behavior is analyzed in combination with the characterization of the channel defect and the surface potential; and in combination with the optimized transmission model and the analysis of the failure behavior, the performance evaluation of the field effect transistor containing black phosphorus is realized. According to the invention, electrical characteristic measurement, failure analysis of bias temperature instability data and characterization of defects and surface potential are fused, and an optimized transmission model and failure behavior analysis are given. And the selection of heterojunction materials in the field effect transistor containing black phosphorus, the structural design of the field effect transistor and the optimization of the preparation process can be more effectively guided.

Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and / or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is / are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

The present invention discloses a method and device for evaluating the performance of a field-effect transistor containing black phosphorus. The method specifically includes the following steps: preparing a field-effect transistor containing black phosphorus; giving a transmission model of the field-effect transistor through electrical characteristic measurement under a first controllable environmental variable; obtaining bias temperature instability data and analyzing the failure behavior; combining the characterization of channel defects and surface potential to optimize the transmission model of the field-effect transistor and the analysis of the failure behavior; and realizing the performance evaluation of the field-effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior. The present invention combines electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential, and gives an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of the field-effect transistor device structure, and the optimization of the manufacturing process in the field-effect transistor containing black phosphorus.

The present invention relates to the field of voltage measurement technology, and proposes a method and system for measuring the accelerating voltage of a medical cyclotron, including: obtaining a resistor voltage sequence and a resistor temperature sequence; obtaining an abnormality according to the resistor voltage value in the resistor voltage sequence; obtaining a load impedance influence according to the difference in the abnormality of different parallel resistors at the same time; obtaining several trend time periods according to the resistor temperature sequence; obtaining a temperature influence according to the resistor temperature value in the trend time period; obtaining a voltage instability coefficient according to the temperature influence and the load impedance influence; obtaining a temperature influence index according to the voltage instability coefficient; obtaining an abnormality probability according to the temperature influence index; and cleaning the resistor voltage sequence according to the abnormality probability and the load impedance influence to obtain an accelerating voltage sequence. The present invention improves the accuracy of the acceleration voltage measurement of a medical cyclotron by cleaning the resistor voltage sequence.

A bias temperature instability (BTI) measurement system is disclosed. One example includes a method for performing a BTI test procedure (106) of a DUT (110). The method includes coupling a contact pad of a DUT circuit (112) to a test device (102). The DUT circuit (112) includes a differential input stage and a gain stage. The differential input stage includes a differential pair of transistors fabricated to match the DUT (110). The method also includes providing a BTI stress from the test apparatus (102) to one of the differential pairs of transistor devices to simulate BTI aging of a respective one of the differential pairs of transistors. The method also includes providing a differential input voltage from the test device (102) to the differential input stage. The method further includes measuring, via the test apparatus (102), an output voltage at an output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate oxide layer and a gate dielectric layer on the substrate, the gate dielectric layer and the gate oxide layer having a first interface therebetween, incorporating a modifying ion at the first interface, the modifying ion being bonded with an ion in the gate dielectric layer or the gate oxide layer, forming a first chemical bond at the first interface, the first chemical bond having a stronger bond strength than before the modifying ion is incorporated, the first chemical bond formed by a defect ion and an ion in the gate dielectric layer (or the gate oxide layer) at the first interface being less likely to be broken, reducing the probability of interface trap charge, thereby reducing the interface state density, reducing the threshold voltage and the saturated drain current of the device from drifting, and improving the negative bias temperature instability.

A delay circuit with bias temperature instability (BTI) mitigation includes an input node; an output node configured to provide a delayed output signal that is a delayed representation of an input signal; a first inverter stage including a first complementary metal-oxide-semiconductor (CMOS) inverter and a resistive-capacitive (RC) delay circuit configured to provide an RC delay for a signal transition of the input signal, wherein the RC delay circuit includes a resistive network of transistors coupled between a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor of the first CMOS inverter; a second inverter stage including a second CMOS inverter coupled between the first inverter stage and the output node; and a supply cutoff circuit configured to disconnect the resistive network of transistors and / or the second CMOS inverter from respective voltage supplies based on one or more supply cutoff conditions being satisfied.

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).