Building-out circuit and testing method for testing negative bias temperature instability

Abstract

The invention provides a building-out circuit and a testing method for testing the negative bias temperature instability (NBTI). The building-out circuit is respectively connected with a source-measurement unit and a PMOS (P-channel Metal Oxide Semiconductor) to be measured; the building-out circuit comprises an NMOS (N-channel metal oxide semiconductor); a base electrode of the NMOS is electrically connected with a source electrode of the NMOS by a resistor R0; a drain electrode fo the NMOS is electrically connected with a grid electrode of the PMOS to be measured by a resistor R1; a grid electrode fo the NMOS is electrically connected with the grid electrode of the PMOS to be measured by a resistor R2; the potential of the base electrode of the NMOS is set into a value of less than 0V; and the voltage input end of the source-measurement unit is connected with the grid electrode of the NMOS. When an input voltage of the source-measurement unit is changed into 0V, due to the voltage division of the resistor R2, the voltage of the grid electrode of the PMOS to be measured is less than 0V, i.e. when the NBTI recovery effect occurs after the stress voltage is switched off, a partial pressure of the R2 is still applied to the grid electrode of the PMOS to be measured to inhibit the NBTI recovery effect in the PMOS, so that the measurement result is more accurate.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a negative bias temperature instability (negative bias temperature instability, NBTI) testing additional circuit and testing method. Background technique [0002] Negative bias temperature instability (NBTI) is an important factor affecting the reliability of CMOS (Complementary Metal Oxide Semiconductor Complementary Metal Oxide Semiconductor) integrated circuits. The NBTI phenomenon has been discovered very early. For larger-sized semiconductor devices, the NBTI effect has little influence on its reliability, so it has not been paid enough attention. With the rapid development of VLSI technology to ultra-deep submicron, the device trench length L and gate oxide thickness tox continue to shrink, the voltage applied to the gate oxide layer is getting higher and higher, and the operating temperature is also increasing accordingly. Devices are becoming more and more sensitive ...

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Problems solved by technology

However, the SMU in the old test machine cannot provide the special conditions requir

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