183 results about "AND gate" patented technology

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric / paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and / or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

The invention relates to a quantum gate simulation and control parameter optimization method based on numerical calculation, and the method sequentially comprises the following three modules: a model Hamiltonian matrix representation module can calculate the matrix representation of a model Hamiltonian according to a specific problem; a time evolution and fidelity calculation module of the system discretely solves a Schrodinger equation by using a Hamiltonian matrix, gives a corresponding time evolution matrix, and calculates gate operation fidelity by using the obtained time evolution matrix; and the control parameter optimization module calls the first two modules, optimizes control parameters and quantum gate operation time by adopting a local optimization algorithm or a global optimization algorithm, and gives optimal control parameters and gate operation time. The problem that the gate fidelity of a current superconducting quantum computing system cannot meet the requirement for reliable operation of a practical quantum algorithm is solved, the detailed process of quantum gate operation can be simulated through a numerical calculation method, and the quantum gate operation fidelity is improved by optimizing control parameters.

A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared variables in the register stage. Thus, the inputs to the cross-domain multiplication and the compression are performed on variables that have been refreshed by additional randomness. This AND gate does not need statistically independent inputs, is secure in the probing model even in the presence of glitches, also known as the robust probing model. A two-domain input and two domain output AND gate can be implemented using six (6) registers, four (4) two input logical AND gates, and eight (8) exclusive-OR (XOR) gates. The AND gate may also be used to implement an AES S-box that has two (2) register stages and takes two (2) clock cycles per computation.

The invention relates to a controllable scaling convolution processing device and a controllable scaling convolution processing method based on random calculation, which share a pseudo random number sequence generated by a random number source in a random number generation module, so that only one linear feedback shift register is used in one round of convolution calculation, the hardware cost and the calculation overhead are greatly reduced, and the processing efficiency is improved. And meanwhile, the random number generation module performs operations such as shifting and interchanging on the pseudo-random number sequence through shuffling operation, so that the correlation between data is effectively weakened, and the precision error caused by the correlation in random calculation is greatly reduced. In the convolution calculation module, a JK trigger is used for replacing a binary divider to generate a control signal of a multiplexer in convolution calculation, and a large number of AND gates or exclusive-OR gates are not needed, so that the complexity of a convolution calculation architecture is greatly simplified, and the hardware cost, the area occupation and the power consumption are further reduced; and finally, the data processing module completes conversion and recovery of binary numbers.

The invention relates to the technical field of gate control, and discloses an intelligent control method and system for a channel gate based on data analysis, and the method comprises the steps: obtaining historical and current user passing data and gate environment data, carrying out the time-frequency domain denoising of the historical data through wavelet transform, and obtaining the denoised data; performing correlation analysis on the denoised historical data, extracting a main environment item and a user behavior item which are remarkably correlated, and establishing an environment-behavior mapping model through linear regression; and generating portraits of different users by using a density clustering algorithm in combination with the mapping model. And further establishing a mapping relationship between the user portrait and the de-noised historical data through a deep learning network, and constructing a user portrait model. And finally, inputting the current data into the model, generating an optimal gate control strategy for different types of users, and realizing intelligent control of the channel gate. According to the method, the user portrait model is established to adapt to multi-user characteristics and complex environment changes, and personalized and accurate control of the gate system is realized.

The invention relates to the technical field of quantum cryptographic analysis, in particular to a parallelization solution optimization method and system for a quantum cryptographic analysis Grover-mets-Simon problem, and aims at solving the Grover-mets-Simon problem by verifying whether an object function in a quantum cryptographic algorithm meets a solution condition or not and constructing a truncated periodic function for the met object function. The solution search space is divided into a parallel solution high bit string period solution space and a general solution low bit string period solution space; solving the truncated periodic function in a parallel high-bit string periodic solving space by using a quantum register according to a parallel Grover-mets-Simon algorithm, so as to obtain quantum key algorithm periodic data through a plurality of parallel Simon threads; and a Grover-mets-Simon algorithm is utilized to carry out supplementary solution on the periodic function in a general low-bit string periodic solution space so as to obtain a quantum key algorithm key and periodic residual bits. According to the method, the depth, width and gate circuit expenditure of the quantum circuit required by quantum cryptographic analysis solution can be flexibly adjusted by adjusting truncation parameters.

The invention provides a quantum circuit semi-cutting mechanism for a distributed quantum computing environment, and the mechanism comprises an isomorphic sub-circuit multiplexing mechanism which is used for recognizing isomorphic sub-circuits in a quantum circuit, and cutting the quantum circuit into the isomorphic sub-circuits, so as to facilitate the multiplexing of an execution result of the isomorphic sub-circuits; according to the quantum circuit semi-cutting mechanism, remote operation is eliminated by cutting key quantum bits in a quantum circuit and gate operation, and the classic post-processing overhead during cutting of a large quantum circuit is reduced. The mechanism solves the problems that in the prior art, isomorphic sub-circuits cannot be reused, and the number of cutting operations is large; the remote communication operation in distributed quantum computing is reduced, and the execution reliability of the quantum circuit is improved.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

The invention relates to the technical field of data processing and provides a device and a method for high-speed input and output. In one embodiment, an apparatus includes a cross-clock-domain transmission logic to periodically receive N beats of input data of single N bits according to a write clock signal, and to individually write the input data bitwise to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal, and to transmit the input data to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal. Reading as output data according to a read enable control signal; and the cross-clock-domain sending control logic is used for writing a write enable control signal into the cross-clock-domain sending control logic, reading as a gating signal according to the read clock signal, and gating the read clock signal according to the gating signal to obtain a read enable control signal, and the frequency ratio of the read clock signal to the write clock signal is N. Therefore, cross-clock-domain interaction of the read-write pointers is avoided, the logic depth and the chip complexity are reduced, and the speed can be increased and the power consumption can be reduced.

An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

The invention relates to the technical field of wireless communication synchronization and gate valve action collaboration, in particular to a multichannel audio master-slave sound role intelligent conversion system and method.A master control unit broadcasts a time calibration packet to synchronize unit clocks, and an automatic calibration protocol is executed to generate an inherent processing delay baseline value; the subordinate gate valve unit records an instruction receiving and action completion timestamp through a delay detection module, calculates actual delay containing wireless transmission and local processing delay, and packages the actual delay into a structured feedback data packet for real-time feedback; a dynamic adjustment module of the main control unit filters noise through a weighted moving average algorithm, and calculates individual compensation delay parameters in combination with the dynamic buffer compensation amount of the environment interference monitoring module and delay trend prediction of an adaptive learning engine; and when abnormity occurs, historical data is called for replacement and self-inspection is triggered, an instruction distribution time sequence is adjusted according to compensation parameters, a gate valve action execution confirmation module verifies the displacement precision, and the fluid control precision and stability are improved.

The invention provides a relay protection device constant value state validity automatic checking system and method, and relates to the technical field of relay protection. Fixed value information of a protection device and input / exit state information of a tripping outlet pressing plate are collected through a data collection module, data processing is carried out, then in a two-way checking engine, a forward character comparison unit carries out character comparison item by item, a reverse logic derivation unit carries out logic relation verification on state data associated with each fixed value, and finally, the protection device and the tripping outlet pressing plate are checked. The comprehensive judgment module verifies whether all the association conditions meet the AND gate relation or not according to the result of the bidirectional check engine, and a final check result is obtained; according to the method, the qualification of the current logic protection circuit to be detected is accurately judged, the detection accuracy is improved, verification interference caused by misoperation of other circuits is avoided, the accuracy of a verification result is improved, the misjudgment risk is reduced, and the reliability of relay protection is improved.

To generate a feedback signal by performing collation of all gate instructions for a multigate semiconductor element against corresponding actual gate voltages, and determine which gate terminal does not match when the result of the collation does not match.SOLUTION: A gate driving device for driving a multigate semiconductor element having a plurality of gate terminals generates a feedback signal to a control logic unit on the basis of a result of collation between a driving signal of each of a plurality of gate terminals that was generated based on a command signal input from the control logic unit in order to turn on / off the multigate semiconductor element and each terminal voltage at the gate terminal corresponding to the driving signal.SELECTED DRAWING: Figure 1

The invention discloses a circuit area optimization method based on an AND XOR majority diagram, and relates to a digital logic circuit area optimization method. According to the method, an input integrated circuit is converted into an AIG netlist, then cutting and replacement are carried out in the AIG netlist according to AIG equivalent structures of XOR gate nodes and majority logic gate nodes, equivalent gate nodes are covered on the AIG netlist according to a cutting result, and the AIG netlist is finally converted into an AXMIG netlist through mapping. Area optimization of the AND gate not limited to two inputs can be carried out, the optimization effect is good, and an integrated circuit can have good comprehensive performance. As the area of the circuit is closely related to the number of mapping gates of the logic netlist, the simple logic netlist generally corresponds to a smaller circuit area, and the aim of optimizing the area of the circuit is fulfilled by simplifying the logic netlist.

The present invention relates to a memristor positive and negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder. The 3-line-1-line encoder of the present invention is used to input three binary signals and output a three-value signal; each three-value three-input maximum value gate is used to output the logical maximum value of three input terminals, the three-value three-input minimum value gate is used to output the logical minimum value of three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of two inputs, the three-value two-input OR gate is used to complete the "OR" operation of two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation; the present invention uses a three-value digital signal to communicate at the same frequency, which will have a higher transmission rate, and the corresponding logic function circuit interconnection will also be reduced, and the digital chip can also be smaller and the cost is lower. Combined with the characteristics of the memristor, the efficiency of information storage, processing, and transmission is further improved.

The present application provides a delay circuit and electronic equipment, and relates to the field of circuit delay technology. The delay circuit includes an input module, a trigger module, an AND gate, and a delay module, the input module is used to receive an input signal, and the output end of the input module is respectively connected to the trigger module and the first input end of the AND gate, the output end of the trigger module is respectively electrically connected to the second input end of the AND gate and the delay module, and the delay module is respectively electrically connected to the input module and the third input end of the AND gate; wherein, when the input module receives a delay signal, the input module and the delay module are used to delay the delay signal, and output the delayed signal through the AND gate. The delay circuit and electronic equipment provided by the present application have the advantages of reducing a large amount of capacitor area and reducing the chip production cost.

The present invention discloses a multi-clock domain glitch-free switching method supporting dynamic clock switching, comprising the following steps: S1, a MUX multiplexer outputs a normally-on clk clock signal according to the switching status of each clock source, and sends the clk clock signal to the corresponding clock switching submodule; S2, in the clock switching submodule, a sel clock selection signal corresponding to the clk clock signal is output as a gating signal for the clk clock signal through an AND gate, a three-stage register, and a first-stage register, and a negated signal of the sel clock selection signal is output as a gating signal for the clock to be switched through an AND gate and a three-stage register; S3, the clk clock signal is turned off by the gating signal in a falling-edge-triggered manner, generating a feedback signal. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal, completing the switching. The method proposed by the present invention can be applied to the clock switching system of a low-power MCU and can realize multi-clock switching.

The invention discloses a data receiving device and method with a data effective window extension mechanism. The data delay circuit receives an input data signal to generate a delayed data signal. The AND gate and the OR gate respectively carry out AND logic operation and OR logic operation on the input data signal and the delay data signal so as to generate an AND gate processing signal and an OR gate processing signal. And the positive edge data multiplexer respectively selects the OR gate processing signal and the AND gate processing signal to output the current positive edge data when the previous negative edge sampling result is in the low state and the high state. The negative edge data multiplexer respectively selects the OR gate processing signal and the AND gate processing signal to output current negative edge data when the previous positive edge sampling result is in a low state and a high state. The sampling circuit performs positive edge and negative edge sampling on the current positive edge data and the current negative edge data respectively to generate a current positive edge sampling result and a current negative edge sampling result.

The invention provides a method and device for improving the diagnosis coverage rate, an automobile chip and a medium, and the method comprises the steps: S1, obtaining gate-level netlist data of an IP which does not have a safety mechanism or the safety level of which does not reach a preset value, and storing the gate-level netlist data in a gate-level netlist I; s2, acquiring a register I which is not protected by a security mechanism from the gate-level netlist I, and storing the register I in a register list I; s3, in the first register list, obtaining a second register needing to be added with verification and a corresponding verification logic based on a preset condition, and storing the second register and the corresponding verification logic in a second register list; s4, inserting a check register and a corresponding check logic into the second register, and storing the check register and the corresponding check logic into a second gate-level netlist; s5, judging whether the functions of the gate-level netlist I and the gate-level netlist II are consistent or not, and if not, updating the verification logic corresponding to the register II; and S6, acquiring an IP diagnosis coverage rate and an IP area in the gate-level netlist 2, judging whether the IP diagnosis coverage rate and the IP area reach a preset coverage rate and a preset area, and if not, returning to the step S3.

The invention relates to a simulation method, device, system and equipment of a digital circuit and a medium. Comprising the steps that description information for the same digital circuit is obtained, and the description information comprises at least one of register transfer level description and gate level description; generating a primary circuit model based on the description information; the primary circuit model is converted into a middle layer circuit model connected with a preset basic logic unit, the basic logic unit is single-bit or multi-bit, each basic logic unit is provided with a corresponding model level attribute and a bit width attribute, and the model level attribute is a register transmission level or a gate level; and calling a simulation algorithm based on the intermediate layer circuit model to carry out circuit simulation to obtain a simulation result. By adopting the method, the simulation efficiency can be improved.

The invention provides an AND gate assembly, an OR gate assembly, a NOT gate assembly, an optical computing chip and electronic equipment. The AND gate assembly comprises a first AND gate and a first filter which are connected in sequence, the first AND gate is used for generating a third light beam when receiving the first light beam and the second light beam at the same time, the wavebands of the first light beam, the second light beam and the third light beam are different, and the first filter is used for filtering the output light beam of the first AND gate and outputting the third light beam. According to the AND gate assembly, the operation result of the first AND gate can be directly obtained, and the operation result of the AND gate can be simply and rapidly determined.

The present invention relates to a computer implemented decoding method that includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature. Additionally the present invention also relates to an apparatus configured to carry out the method. The apparatus being implemented either with at least one memory and at least one processor or with a plurality of finite state machines and a plurality of logical AND gates.

The present invention relates to a circuit structure for fine-tuning the square-wave control phase of a brushless DC motor. The circuit structure comprises a PWM configuration register that generates six n-bit PWM signals based on rotor position; a 3-8 decoder that divides the signals into six signals, namely, bit 1 through bit 6; an expansion module that expands the bit 1 through bit 6 signals into n-bit identical signals, resulting in 6n-bit signals; an n-bit AND gate module that performs an AND operation on the expanded 6n-bit signals and the 6n-bit PWM configuration signals; and an n-bit OR gate module that receives the six fused signal groups and performs an OR operation on the six n-bit PWM configuration signals. The circuit structure and method for fine-tuning the square-wave control phase of a brushless DC motor employing the present invention fine-tunes the phase advance or lag by changing the duty cycle configuration register, thereby improving motor operating efficiency without requiring complex software programming. Hardware implementation of the commutation process simplifies software implementation and reduces CPU time, freeing the CPU for other safety controls.

The invention designs and provides a multi-input logic gate operation circuit and method based on a 2T-2C ferroelectric storage unit, and aims at solving the bottleneck of a traditional calculation framework and meeting the requirement of in-memory calculation for efficient multi-input logic. According to the circuit, a majority decision logic principle is applied, and an N input logic gate is realized by combining (2N-1) 2T-2C ferroelectric storage units. Wherein N units receive actual logic variables, and the remaining (N-1) units are preset to be in a fixed logic state ('0' or '1') according to a target logic function ('AND gate' or 'OR gate'). According to the design, function expansion is carried out by utilizing most of logic characteristics which are inherent formed by a small number of 2T-2C units. According to the method, multi-input AND and OR operation can be directly realized in the in-memory computing architecture efficiently and flexibly, the advantages of non-volatility, low power consumption and the like of a ferroelectric memory are inherited, and the integration level and the performance of logic operation are improved.

The invention relates to the technical field of chip testing, in particular to a forced testing circuit of a chip. The circuit comprises a target interface, a forced test signal, a first target three-state gate, a second target three-state gate, a first target AND gate, a first target OR gate, a first target phase inverter, a second target phase inverter, a first target output end, a first target input end, a first control signal and a second control signal. When the forced test signal is at a high level, the first target three-state gate is in a cut-off state, and the second target three-state gate is in a conducting state, so that the target interface is ensured to be in an input state, and the target interface can be a second interface and a third interface; therefore, the second interface and the third interface are kept in the input state in the test mode so as to receive the configuration of the test sub-mode, namely, the priority of the configuration of the test sub-mode is improved.

The present invention relates to the technical field of platform door control, and in particular to a communication-based SIL4-level platform door system, comprising a domain controller, a DCU, an external interface and other subsystem devices; the platform door system realizes interconnection and intercommunication with a signal system and other subsystem devices through bus connection and hard-wire connection, thereby ensuring high security and high reliability of the system, and adopts a dual CPU architecture inside the domain controller and the door control unit, and the dual CPU design can perform double processing and cross-verification on data to ensure the accuracy and consistency of the data, thereby replacing the existing relay circuit to achieve the SIL4 safety level; the data transparent transmission mechanism performed by a single CPU reduces data transmission delay and improves real-time response capability.

The invention provides a three-dimensional computing architecture and a computing method, relates to the field of computing architectures, and aims to solve the problems that an existing computing architecture lacks multifunctional fusion capability and is high in energy consumption. The computing architecture comprises a logic circuit layer electrically connected with a first metal layer; the logic circuit layer is used for preprocessing input data to obtain preprocessed data; the in-memory calculation layer is electrically connected with the first metal layer and the second metal layer respectively; the in-memory calculation layer is used for carrying out storage and matrix calculation on the preprocessed data to obtain calculation data; the first circuit layer is used for carrying out sparse check and gating on the calculation data to obtain effective data; the second circuit layer is electrically connected with the second area of the third metal layer; and the second circuit layer is used for temporarily storing and rearranging the effective data to obtain rearranged data. According to the method and the device, invalid information can be eliminated to the greatest extent before data cross-layer transmission, so that the bandwidth requirement and cross-layer communication energy consumption are effectively reduced.

The invention provides a signal generation method, electronic equipment, a receiver and a computer readable storage medium, relates to the technical field of data processing, and can output PPS signals with a relatively large duration as a period. The method is applied to the electronic equipment, the electronic equipment comprises a target instruction sending device, an AND gate circuit, a signal generation device and an event shielding register, the target instruction sending device is connected with the signal generation device through the AND gate circuit, and the event shielding register is connected with the signal generation device through the AND gate circuit. The method comprises the following steps: configuring an event mask register to be low level in a first time period; the event shielding register is configured to be at a high level in a second time period; the first time period is adjacent to the second time period, the second time length is larger than the first time length, the second time length is the sum of the third time length and the fourth time length, the third time length is the time length of the first time period, the fourth time length is the time length of the second time period, and the fourth time length is smaller than the first time length.

This application provides a signal generation method, an electronic device, a receiver, and a computer-readable storage medium, relating to the field of data processing technology, capable of outputting PPS signals with a relatively long duration. The method is applied to an electronic device, which includes a target instruction transmitting device, an AND gate circuit, a signal generation device, and an event mask register. The target instruction transmitting device is connected to the signal generation device via the AND gate circuit, and the event mask register is also connected to the signal generation device via the AND gate circuit. The method includes: configuring the event mask register to a low level during a first time period; configuring the event mask register to a high level during a second time period; the first time period and the second time period are adjacent, the second duration is longer than the first duration, the second duration is the sum of a third duration and a fourth duration, the third duration is the duration of the first time period, the fourth duration is the duration of the second time period, and the fourth duration is shorter than the first duration.