143 results about "AND gate" patented technology

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

The invention relates to the technical field of gate control, and discloses an intelligent control method and system for a channel gate based on data analysis, and the method comprises the steps: obtaining historical and current user passing data and gate environment data, carrying out the time-frequency domain denoising of the historical data through wavelet transform, and obtaining the denoised data; performing correlation analysis on the denoised historical data, extracting a main environment item and a user behavior item which are remarkably correlated, and establishing an environment-behavior mapping model through linear regression; and generating portraits of different users by using a density clustering algorithm in combination with the mapping model. And further establishing a mapping relationship between the user portrait and the de-noised historical data through a deep learning network, and constructing a user portrait model. And finally, inputting the current data into the model, generating an optimal gate control strategy for different types of users, and realizing intelligent control of the channel gate. According to the method, the user portrait model is established to adapt to multi-user characteristics and complex environment changes, and personalized and accurate control of the gate system is realized.

The invention relates to the technical field of quantum cryptographic analysis, in particular to a parallelization solution optimization method and system for a quantum cryptographic analysis Grover-mets-Simon problem, and aims at solving the Grover-mets-Simon problem by verifying whether an object function in a quantum cryptographic algorithm meets a solution condition or not and constructing a truncated periodic function for the met object function. The solution search space is divided into a parallel solution high bit string period solution space and a general solution low bit string period solution space; solving the truncated periodic function in a parallel high-bit string periodic solving space by using a quantum register according to a parallel Grover-mets-Simon algorithm, so as to obtain quantum key algorithm periodic data through a plurality of parallel Simon threads; and a Grover-mets-Simon algorithm is utilized to carry out supplementary solution on the periodic function in a general low-bit string periodic solution space so as to obtain a quantum key algorithm key and periodic residual bits. According to the method, the depth, width and gate circuit expenditure of the quantum circuit required by quantum cryptographic analysis solution can be flexibly adjusted by adjusting truncation parameters.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

The invention relates to the technical field of data processing and provides a device and a method for high-speed input and output. In one embodiment, an apparatus includes a cross-clock-domain transmission logic to periodically receive N beats of input data of single N bits according to a write clock signal, and to individually write the input data bitwise to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal, and to transmit the input data to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal. Reading as output data according to a read enable control signal; and the cross-clock-domain sending control logic is used for writing a write enable control signal into the cross-clock-domain sending control logic, reading as a gating signal according to the read clock signal, and gating the read clock signal according to the gating signal to obtain a read enable control signal, and the frequency ratio of the read clock signal to the write clock signal is N. Therefore, cross-clock-domain interaction of the read-write pointers is avoided, the logic depth and the chip complexity are reduced, and the speed can be increased and the power consumption can be reduced.

The invention relates to the technical field of wireless communication synchronization and gate valve action collaboration, in particular to a multichannel audio master-slave sound role intelligent conversion system and method.A master control unit broadcasts a time calibration packet to synchronize unit clocks, and an automatic calibration protocol is executed to generate an inherent processing delay baseline value; the subordinate gate valve unit records an instruction receiving and action completion timestamp through a delay detection module, calculates actual delay containing wireless transmission and local processing delay, and packages the actual delay into a structured feedback data packet for real-time feedback; a dynamic adjustment module of the main control unit filters noise through a weighted moving average algorithm, and calculates individual compensation delay parameters in combination with the dynamic buffer compensation amount of the environment interference monitoring module and delay trend prediction of an adaptive learning engine; and when abnormity occurs, historical data is called for replacement and self-inspection is triggered, an instruction distribution time sequence is adjusted according to compensation parameters, a gate valve action execution confirmation module verifies the displacement precision, and the fluid control precision and stability are improved.

The invention provides a relay protection device constant value state validity automatic checking system and method, and relates to the technical field of relay protection. Fixed value information of a protection device and input / exit state information of a tripping outlet pressing plate are collected through a data collection module, data processing is carried out, then in a two-way checking engine, a forward character comparison unit carries out character comparison item by item, a reverse logic derivation unit carries out logic relation verification on state data associated with each fixed value, and finally, the protection device and the tripping outlet pressing plate are checked. The comprehensive judgment module verifies whether all the association conditions meet the AND gate relation or not according to the result of the bidirectional check engine, and a final check result is obtained; according to the method, the qualification of the current logic protection circuit to be detected is accurately judged, the detection accuracy is improved, verification interference caused by misoperation of other circuits is avoided, the accuracy of a verification result is improved, the misjudgment risk is reduced, and the reliability of relay protection is improved.

The present invention discloses a multi-clock domain glitch-free switching method supporting dynamic clock switching, comprising the following steps: S1, a MUX multiplexer outputs a normally-on clk clock signal according to the switching status of each clock source, and sends the clk clock signal to the corresponding clock switching submodule; S2, in the clock switching submodule, a sel clock selection signal corresponding to the clk clock signal is output as a gating signal for the clk clock signal through an AND gate, a three-stage register, and a first-stage register, and a negated signal of the sel clock selection signal is output as a gating signal for the clock to be switched through an AND gate and a three-stage register; S3, the clk clock signal is turned off by the gating signal in a falling-edge-triggered manner, generating a feedback signal. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal, completing the switching. The method proposed by the present invention can be applied to the clock switching system of a low-power MCU and can realize multi-clock switching.

The invention discloses a data receiving device and method with a data effective window extension mechanism. The data delay circuit receives an input data signal to generate a delayed data signal. The AND gate and the OR gate respectively carry out AND logic operation and OR logic operation on the input data signal and the delay data signal so as to generate an AND gate processing signal and an OR gate processing signal. And the positive edge data multiplexer respectively selects the OR gate processing signal and the AND gate processing signal to output the current positive edge data when the previous negative edge sampling result is in the low state and the high state. The negative edge data multiplexer respectively selects the OR gate processing signal and the AND gate processing signal to output current negative edge data when the previous positive edge sampling result is in a low state and a high state. The sampling circuit performs positive edge and negative edge sampling on the current positive edge data and the current negative edge data respectively to generate a current positive edge sampling result and a current negative edge sampling result.

The invention relates to a simulation method, device, system and equipment of a digital circuit and a medium. Comprising the steps that description information for the same digital circuit is obtained, and the description information comprises at least one of register transfer level description and gate level description; generating a primary circuit model based on the description information; the primary circuit model is converted into a middle layer circuit model connected with a preset basic logic unit, the basic logic unit is single-bit or multi-bit, each basic logic unit is provided with a corresponding model level attribute and a bit width attribute, and the model level attribute is a register transmission level or a gate level; and calling a simulation algorithm based on the intermediate layer circuit model to carry out circuit simulation to obtain a simulation result. By adopting the method, the simulation efficiency can be improved.

The invention provides an AND gate assembly, an OR gate assembly, a NOT gate assembly, an optical computing chip and electronic equipment. The AND gate assembly comprises a first AND gate and a first filter which are connected in sequence, the first AND gate is used for generating a third light beam when receiving the first light beam and the second light beam at the same time, the wavebands of the first light beam, the second light beam and the third light beam are different, and the first filter is used for filtering the output light beam of the first AND gate and outputting the third light beam. According to the AND gate assembly, the operation result of the first AND gate can be directly obtained, and the operation result of the AND gate can be simply and rapidly determined.

The present invention relates to a computer implemented decoding method that includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature. Additionally the present invention also relates to an apparatus configured to carry out the method. The apparatus being implemented either with at least one memory and at least one processor or with a plurality of finite state machines and a plurality of logical AND gates.

The present invention relates to a circuit structure for fine-tuning the square-wave control phase of a brushless DC motor. The circuit structure comprises a PWM configuration register that generates six n-bit PWM signals based on rotor position; a 3-8 decoder that divides the signals into six signals, namely, bit 1 through bit 6; an expansion module that expands the bit 1 through bit 6 signals into n-bit identical signals, resulting in 6n-bit signals; an n-bit AND gate module that performs an AND operation on the expanded 6n-bit signals and the 6n-bit PWM configuration signals; and an n-bit OR gate module that receives the six fused signal groups and performs an OR operation on the six n-bit PWM configuration signals. The circuit structure and method for fine-tuning the square-wave control phase of a brushless DC motor employing the present invention fine-tunes the phase advance or lag by changing the duty cycle configuration register, thereby improving motor operating efficiency without requiring complex software programming. Hardware implementation of the commutation process simplifies software implementation and reduces CPU time, freeing the CPU for other safety controls.

The invention designs and provides a multi-input logic gate operation circuit and method based on a 2T-2C ferroelectric storage unit, and aims at solving the bottleneck of a traditional calculation framework and meeting the requirement of in-memory calculation for efficient multi-input logic. According to the circuit, a majority decision logic principle is applied, and an N input logic gate is realized by combining (2N-1) 2T-2C ferroelectric storage units. Wherein N units receive actual logic variables, and the remaining (N-1) units are preset to be in a fixed logic state ('0' or '1') according to a target logic function ('AND gate' or 'OR gate'). According to the design, function expansion is carried out by utilizing most of logic characteristics which are inherent formed by a small number of 2T-2C units. According to the method, multi-input AND and OR operation can be directly realized in the in-memory computing architecture efficiently and flexibly, the advantages of non-volatility, low power consumption and the like of a ferroelectric memory are inherited, and the integration level and the performance of logic operation are improved.

The invention relates to the technical field of chip testing, in particular to a forced testing circuit of a chip. The circuit comprises a target interface, a forced test signal, a first target three-state gate, a second target three-state gate, a first target AND gate, a first target OR gate, a first target phase inverter, a second target phase inverter, a first target output end, a first target input end, a first control signal and a second control signal. When the forced test signal is at a high level, the first target three-state gate is in a cut-off state, and the second target three-state gate is in a conducting state, so that the target interface is ensured to be in an input state, and the target interface can be a second interface and a third interface; therefore, the second interface and the third interface are kept in the input state in the test mode so as to receive the configuration of the test sub-mode, namely, the priority of the configuration of the test sub-mode is improved.

The invention provides a three-dimensional computing architecture and a computing method, relates to the field of computing architectures, and aims to solve the problems that an existing computing architecture lacks multifunctional fusion capability and is high in energy consumption. The computing architecture comprises a logic circuit layer electrically connected with a first metal layer; the logic circuit layer is used for preprocessing input data to obtain preprocessed data; the in-memory calculation layer is electrically connected with the first metal layer and the second metal layer respectively; the in-memory calculation layer is used for carrying out storage and matrix calculation on the preprocessed data to obtain calculation data; the first circuit layer is used for carrying out sparse check and gating on the calculation data to obtain effective data; the second circuit layer is electrically connected with the second area of the third metal layer; and the second circuit layer is used for temporarily storing and rearranging the effective data to obtain rearranged data. According to the method and the device, invalid information can be eliminated to the greatest extent before data cross-layer transmission, so that the bandwidth requirement and cross-layer communication energy consumption are effectively reduced.

The invention provides a signal generation method, electronic equipment, a receiver and a computer readable storage medium, relates to the technical field of data processing, and can output PPS signals with a relatively large duration as a period. The method is applied to the electronic equipment, the electronic equipment comprises a target instruction sending device, an AND gate circuit, a signal generation device and an event shielding register, the target instruction sending device is connected with the signal generation device through the AND gate circuit, and the event shielding register is connected with the signal generation device through the AND gate circuit. The method comprises the following steps: configuring an event mask register to be low level in a first time period; the event shielding register is configured to be at a high level in a second time period; the first time period is adjacent to the second time period, the second time length is larger than the first time length, the second time length is the sum of the third time length and the fourth time length, the third time length is the time length of the first time period, the fourth time length is the time length of the second time period, and the fourth time length is smaller than the first time length.

This application provides a signal generation method, an electronic device, a receiver, and a computer-readable storage medium, relating to the field of data processing technology, capable of outputting PPS signals with a relatively long duration. The method is applied to an electronic device, which includes a target instruction transmitting device, an AND gate circuit, a signal generation device, and an event mask register. The target instruction transmitting device is connected to the signal generation device via the AND gate circuit, and the event mask register is also connected to the signal generation device via the AND gate circuit. The method includes: configuring the event mask register to a low level during a first time period; configuring the event mask register to a high level during a second time period; the first time period and the second time period are adjacent, the second duration is longer than the first duration, the second duration is the sum of a third duration and a fourth duration, the third duration is the duration of the first time period, the fourth duration is the duration of the second time period, and the fourth duration is shorter than the first duration.

A neural processing element is configured with a hardware AND gate configured to perform a logical AND operation between a sign extension signal and a most significant bit ("MSB") of an operand. A state of the sign extension signal can be based on a type of layer of a deep neural network ("DNN") that generated the operand. If the sign extension signal is a logical false, no signal extension is performed. If the sign extension signal is a logical true, a coupler couples an output of the hardware AND gate and the operand, thereby extending the operand from an N-bit unsigned binary value to an N+1-bit signed binary value. The neural processing element can also include another hardware AND gate and another coupler for similarly processing another operand. An output of the couplers for both operands is provided to a hardware binary multiplier.

A method for implementing a logic circuit employing a combination of binary adders of different lengths having summation and carry outputs and AND gates, comprising the steps of replacing at least one known CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing summation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the binary adder circuit, for compensating for voltage level losses when the output is in a high logic state or low logic state. The at least one CMOS AND gate is replaced with a high Fan-in AND gate being above a predetermined threshold, by an improved AND gate consisting of a logic block for performing an AND operation between binary inputs of the logic block; a restoration block, connected between the output of the logic block and the output of the AND gate, for compensating for voltage level losses when the output being in a high logic state or low logic state.

Embodiments of the present disclosure provide a monostable circuit, wherein the monostable circuit comprises: a monostable main circuit, a shielding time window circuit; wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, a feedback of an output signal of the monostable circuit, a time window signal output by the shielding time window circuit through an AND gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate, the time window signal being a signal resisting interference of the output signal by abnormal pulses of the input signal; the shielding time window circuit is configured to receive the feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and a logic gate. The problem that the existing monostable circuit may be mis-triggered due to abnormal pulses of an input signal is solved.

The invention describes a method (100) for reducing error in the determination of an observable of a quantum system in a quantum state on a noisy quantum computer platform, comprising the following steps: • dividing (101) an observable operator into series of base operators; • providing (102) calibration operators; • measuring (103) the calibration operators, comprising determining (104) noisy measurement results (1040) and gate-error-reduced measurement results (1050) of the calibration operators; • ascertaining (106) a calibration function (1060) for mapping the noisy measurement results (1040) to the gate-error-reduced measurement results (1050) of the calibration operators; • determining (107) noisy measurement results (1070) of the series of base operators; • determining (108) error-reduced measurement results (1080) of the series of base operators by mapping (109) the noisy measurement results (1070) by means of the calibration function (1060); • determining (110) the observable by combining the error-reduced measurement results (1080) of the series of base operators.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

The present application relates to in-memory computing field, especially to a maximum and minimum value search circuit, a median generation circuit and application thereof.The maximum and minimum value search circuit comprises N cascaded comparison units; each comparison unit is connected with an input unit, and each input unit is used for synchronously inputting respective input data to the respective connected comparison unit in descending order bit by bit. Each comparison unit comprises 2 PMOS tubes, 5 NMOS tubes, 2 AND gates, 2 OR gates and 1 inverter; and comprises a data control module, a larger value comparison module and a smaller value comparison module. The circuit can directly output the maximum value and the minimum value contained therein after the input unit completes data input. The maximum value search circuit is combined with the median generator based on the adder and the D flip-flop chain, and the median generation circuit is obtained. The two circuits provided by the present application can solve the problem that the working frequency and the area are limited in the existing floating point in-memory computing architecture.

The present invention provides a multi-cycle full-data A / D conversion sampling method, which includes the following steps: S1, the processor is started; S2: after assigning the i-th analog input signal to 0, the i-th analog input signal is selected and gated, and wait for the analog signal to be fully established; S3: start the conversion; S4: start the tasks of the current cycle; S5: determine whether i is less than N-1. If it is less, go to step S6. If i is equal to N-1, assign 0 to i and then go to step 7; S6: increment i by 1; S7: perform parallel processing on the address gating of the (i + 1)-th analog input signal and the conversion judgment of the i-th analog input signal; S8: start the conversion of the data of i + 1 and then perform other tasks of the current cycle; S9: after the tasks of the current cycle are completed, return to step S4 to perform the next cycle. This method fully improves the operating efficiency of the processor and effectively reduces the ineffective waiting time during the A / D conversion sampling process.

The invention discloses a 9T-SRAM (9 T-Static Random Access Memory)-based dual-bit line in-memory calculation unit, circuit and chip, and relates to the technical field of SRAM circuit design. A 9T storage unit is designed according to the highest 16-row multiply-accumulate calculation of a 2-bit activation value and a 1-bit weight, and two phase inverters are introduced to generate opposite control signals S and S'based on a single bit line; the S and 2bit activation values are subjected to AND operation through corresponding AND gates, and the S'and 2bit activation values are subjected to AND operation through corresponding AND gates, so that the 2bit activation values are controlled to be input into the 9T storage unit to discharge corresponding bit lines, the bit lines capable of participating in discharge are increased to two bit lines BL and BLB from the bit line BL, and the linearity is remarkably improved; and S and S'are used for controlling corresponding bit lines to be connected with the five-bit analog-to-digital converter through the output control part to perform low five-bit quantization, and the highest-bit quantization value is directly obtained in the S state, so that the area and the power consumption can be reduced by half.

The application discloses a flood scheduling gate operation logic anti-misoperation method and device based on rule self-learning, and particularly relates to the technical field of gate scheduling control systems. Trend results are generated by differentially determining the signs of the inflow and reservoir water level, consistency checking is performed in combination with the discharge variation direction and gate opening instruction to form an effective instruction sequence; the residual space amount of the downstream sensitive area is calculated, and the channel impact coefficient is generated in combination with the discharge impact amount and channel conditions; on this basis, the over-limit channel flow is reduced and distributed to the normal channel to form a rechecked sharing result. The application can realize trend dynamic judgment and instruction direction matching, guarantee discharge adjustment and hydrological condition consistency, and through the closed logic of reduction and distribution, the multi-channel flow sharing structure is optimized, the gate adjustment sequence logic is set according to the gate operation principle of the power station design, automatic matching of the discharge and gate adjustment is realized, and the situation of lower gate operation order is prevented.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The application provides an intelligent edge processing method with logical relationship power switch quantity, and the specific steps include: S1, two input ports are formed by collecting signals and high level signals, and the signals are stored in gateway memory through an AND gate circuit as current data of switches; the data stored in the gateway is expressed as follows: A x ={S1, S2, S3, S4, S5...S n} (1); S2, the data of all current switches are re-collected at a preset switch collection frequency; the data set is: A' x ={S'1, S'2, S'3, S '4 , S'5...S' n} (3); S3, if S n +S' n =0, it is indicated that the switch is not in a variable position, the result is input into the gateway memory as a feedback signal, and the switch state at the latest time is updated; if S n +S' n =1, it is indicated that the switch has been in a variable position, the signal is sent to a background in real time, and a power system topology is updated according to the signal.

The invention provides a data verification circuit and method, a chip, an electronic device and electronic equipment, and relates to the technical field of circuit design, and through connection of multiple layers of AND gates and OR gates, AND operation and OR operation are continuously performed, so that a final result can intuitively reflect the quantity condition of effective data in to-be-verified data, and the data verification efficiency is improved. Therefore, whether the to-be-verified data is the target data can be determined. And each layer in the circuit is subjected to AND operation and OR operation based on the AND gate and the OR gate at the same time, so that the generated time delay is relatively small, and application in large-scale and high-speed digital circuit design is facilitated.