5464 results about "AND gate" patented technology

A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an Al_yGa_1−yN (y=1 or y 1) layer on the GaN buffer layer. An Al_xGa_1−xN (0≦x≦0.5) barrier layer on to the Al_yGa_1−yN layer, opposite the GaN buffer layer, Al_yGa_1−yN layer having a higher Al concentration than that of the Al_xGa_1−xN barrier layer. A preferred Al_yGa_1−yN layer has y=1 or y˜1 and a preferred Al_xGa_1−xN barrier layer has 0≦x≦0.5. A 2DEG forms at the interface between the GaN buffer layer and the Al_yGa_1−yN layer. Respective source, drain and gate contacts are formed on the Al_xGa_1−xN barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the Al_yGa_1−yN layer and a nucleation layer between the Al_xGa_1−xN buffer layer and the substrate.

A example method of forming of a contact hole by removing residue and oxide spacer beside a nitride spacer after a CF containing etch. We provide a gate structure with nitride spacers on the sidewalls of the gate. We provide a dielectric layer (oxide) over the substrate and gate structure. We form a contact photoresist pattern over the oxide dielectric layer. We etch the oxide dielectric layer using fluorocarbons (CxFy) to form contact openings and residual spacer. The photoresist is striped. Preferably, a NF₃ and N₂ and H₂ plasma treatment is performed to deposit a byproducts layer over the residual spacer. The byproducts layer and residual spacer are removed preferably using one of the following processes: (1) heat (2) DI rinse or (3) IR or UV radiation.

The invention provides a method of driving an electro-optical device and an electronic apparatus which are capable of reducing the time for writing data without providing special circuits. In the electro-optical device pixel circuits having reset transistors for controlling an electric connection between drains and gates of driving transistors between the drains and the gates of the driving transistors are arranged on a display panel in a matrix. The pixel circuits arranged in a matrix are electrically connected to a scanning line driving circuit via scanning lines. The scanning line driving circuit sequentially switches on the reset transistors from the pixel circuit connected to first scanning lines in accordance with scanning line control signals supplied from a control circuit and then lets organic EL elements emit light.

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

A method of performing physiological gating in a medical procedure includes acquiring a sequence of images having at least a first image and a second image of a target region, determining a first composite image based on the first and second images, and gating a medical procedure based on the composite image. A method of performing a medical procedure includes providing a plurality of templates, each of the templates having an image and treatment data, acquiring an input image, registering the input image with one of the templates, and performing a medical procedure based on the treatment data of the one of the templates that is registered with the input image.

A system for continuously circulating fluid to and through a tubular string either of coiled tubing or made up of a plurality of tubulars connected end-to-end while an upper tubular is added to or removed from a top tubular of the plurality of tubulars, all tubulars having a top-to-bottom fluid flow channel therethrough, the system having an upper chamber with a bottom opening, a top opening, and an upper sealing apparatus for sealingly encompassing a portion of the upper tubular, a lower chamber with a bottom opening, a top opening and a lower sealing apparatus for sealingly encompassing a portion of the top tubular, one of the upper chamber and the lower chamber sized for accommodating connection and disconnection therein of the upper tubular and the top tubular, and gate apparatus between and in fluid communication with the upper chamber and the lower chamber. Such a system may have apparatus for isolating a tubular therein from an axial load imposed by fluid pressure in a chamber; at least one of the lower chamber and the upper chamber with inner bushing apparatus with a portion thereof movably disposable within the chamber's sealing apparatus for facilitating movement of a tubular with respect to the chamber's sealing apparatus, and the system connectible to and rotatable by a rotating system for rotating the tubular string; and/or heave compensation interconnections for interconnecting the system to an offshore rig's heave compensation system. The system in certain aspects including fluid flow lines to each of the top and bottom chambers, a supply of fluid for circulating through the tubular string and through the upper and lower chambers, apparatus for continuously moving circulating fluid from the supply through the system into the tubular string.

A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.

Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film serving as a front-end film and the chromium film is etched to be patterned by using a resist as a mask. Next, a micro-crystal silicon film on which the residual substances exist is exposed to plasma of a mixed gas including chlorine gas and oxygen gas to selectively etch the residual substances on a surface of the micro-crystal silicon film. After that, the micro-crystal silicon film is dry etched.

A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n⁺ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.

The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

A calibration method for a two-port VNA includes presenting a high reflection calibration standard and measuring reflection data for each of the two ports, calculating a location of the high reflection calibration standard at each of the two ports, presenting a load calibration standard and measuring the reflection characteristic for each of the two ports to provide load data, converting the load data to the time domain to provide time domain impulse response load data, and gating the time domain impulse response load data based on the locations of the high reflection calibration standard at each of two ports. The method further includes reconstructing frequency domain load data from the gated time domain data, connecting the two ports together and determining forward and reverse transmission characteristics, and calculating systematic error coefficients for the VNA based on the reconstructed frequency domain data and the forward and reverse transmission characteristics.

A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.

A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.