65 results about "AND gate" patented technology

The invention relates to the technical field of wireless communication synchronization and gate valve action collaboration, in particular to a multichannel audio master-slave sound role intelligent conversion system and method.A master control unit broadcasts a time calibration packet to synchronize unit clocks, and an automatic calibration protocol is executed to generate an inherent processing delay baseline value; the subordinate gate valve unit records an instruction receiving and action completion timestamp through a delay detection module, calculates actual delay containing wireless transmission and local processing delay, and packages the actual delay into a structured feedback data packet for real-time feedback; a dynamic adjustment module of the main control unit filters noise through a weighted moving average algorithm, and calculates individual compensation delay parameters in combination with the dynamic buffer compensation amount of the environment interference monitoring module and delay trend prediction of an adaptive learning engine; and when abnormity occurs, historical data is called for replacement and self-inspection is triggered, an instruction distribution time sequence is adjusted according to compensation parameters, a gate valve action execution confirmation module verifies the displacement precision, and the fluid control precision and stability are improved.

The present invention relates to a computer implemented decoding method that includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature. Additionally the present invention also relates to an apparatus configured to carry out the method. The apparatus being implemented either with at least one memory and at least one processor or with a plurality of finite state machines and a plurality of logical AND gates.

The invention relates to the technical field of chip testing, in particular to a forced testing circuit of a chip. The circuit comprises a target interface, a forced test signal, a first target three-state gate, a second target three-state gate, a first target AND gate, a first target OR gate, a first target phase inverter, a second target phase inverter, a first target output end, a first target input end, a first control signal and a second control signal. When the forced test signal is at a high level, the first target three-state gate is in a cut-off state, and the second target three-state gate is in a conducting state, so that the target interface is ensured to be in an input state, and the target interface can be a second interface and a third interface; therefore, the second interface and the third interface are kept in the input state in the test mode so as to receive the configuration of the test sub-mode, namely, the priority of the configuration of the test sub-mode is improved.

The invention provides a three-dimensional computing architecture and a computing method, relates to the field of computing architectures, and aims to solve the problems that an existing computing architecture lacks multifunctional fusion capability and is high in energy consumption. The computing architecture comprises a logic circuit layer electrically connected with a first metal layer; the logic circuit layer is used for preprocessing input data to obtain preprocessed data; the in-memory calculation layer is electrically connected with the first metal layer and the second metal layer respectively; the in-memory calculation layer is used for carrying out storage and matrix calculation on the preprocessed data to obtain calculation data; the first circuit layer is used for carrying out sparse check and gating on the calculation data to obtain effective data; the second circuit layer is electrically connected with the second area of the third metal layer; and the second circuit layer is used for temporarily storing and rearranging the effective data to obtain rearranged data. According to the method and the device, invalid information can be eliminated to the greatest extent before data cross-layer transmission, so that the bandwidth requirement and cross-layer communication energy consumption are effectively reduced.

This application provides a signal generation method, an electronic device, a receiver, and a computer-readable storage medium, relating to the field of data processing technology, capable of outputting PPS signals with a relatively long duration. The method is applied to an electronic device, which includes a target instruction transmitting device, an AND gate circuit, a signal generation device, and an event mask register. The target instruction transmitting device is connected to the signal generation device via the AND gate circuit, and the event mask register is also connected to the signal generation device via the AND gate circuit. The method includes: configuring the event mask register to a low level during a first time period; configuring the event mask register to a high level during a second time period; the first time period and the second time period are adjacent, the second duration is longer than the first duration, the second duration is the sum of a third duration and a fourth duration, the third duration is the duration of the first time period, the fourth duration is the duration of the second time period, and the fourth duration is shorter than the first duration.

A neural processing element is configured with a hardware AND gate configured to perform a logical AND operation between a sign extension signal and a most significant bit ("MSB") of an operand. A state of the sign extension signal can be based on a type of layer of a deep neural network ("DNN") that generated the operand. If the sign extension signal is a logical false, no signal extension is performed. If the sign extension signal is a logical true, a coupler couples an output of the hardware AND gate and the operand, thereby extending the operand from an N-bit unsigned binary value to an N+1-bit signed binary value. The neural processing element can also include another hardware AND gate and another coupler for similarly processing another operand. An output of the couplers for both operands is provided to a hardware binary multiplier.

Embodiments of the present disclosure provide a monostable circuit, wherein the monostable circuit comprises: a monostable main circuit, a shielding time window circuit; wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, a feedback of an output signal of the monostable circuit, a time window signal output by the shielding time window circuit through an AND gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate, the time window signal being a signal resisting interference of the output signal by abnormal pulses of the input signal; the shielding time window circuit is configured to receive the feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and a logic gate. The problem that the existing monostable circuit may be mis-triggered due to abnormal pulses of an input signal is solved.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

The invention discloses a 9T-SRAM (9 T-Static Random Access Memory)-based dual-bit line in-memory calculation unit, circuit and chip, and relates to the technical field of SRAM circuit design. A 9T storage unit is designed according to the highest 16-row multiply-accumulate calculation of a 2-bit activation value and a 1-bit weight, and two phase inverters are introduced to generate opposite control signals S and S'based on a single bit line; the S and 2bit activation values are subjected to AND operation through corresponding AND gates, and the S'and 2bit activation values are subjected to AND operation through corresponding AND gates, so that the 2bit activation values are controlled to be input into the 9T storage unit to discharge corresponding bit lines, the bit lines capable of participating in discharge are increased to two bit lines BL and BLB from the bit line BL, and the linearity is remarkably improved; and S and S'are used for controlling corresponding bit lines to be connected with the five-bit analog-to-digital converter through the output control part to perform low five-bit quantization, and the highest-bit quantization value is directly obtained in the S state, so that the area and the power consumption can be reduced by half.

The application discloses a flood scheduling gate operation logic anti-misoperation method and device based on rule self-learning, and particularly relates to the technical field of gate scheduling control systems. Trend results are generated by differentially determining the signs of the inflow and reservoir water level, consistency checking is performed in combination with the discharge variation direction and gate opening instruction to form an effective instruction sequence; the residual space amount of the downstream sensitive area is calculated, and the channel impact coefficient is generated in combination with the discharge impact amount and channel conditions; on this basis, the over-limit channel flow is reduced and distributed to the normal channel to form a rechecked sharing result. The application can realize trend dynamic judgment and instruction direction matching, guarantee discharge adjustment and hydrological condition consistency, and through the closed logic of reduction and distribution, the multi-channel flow sharing structure is optimized, the gate adjustment sequence logic is set according to the gate operation principle of the power station design, automatic matching of the discharge and gate adjustment is realized, and the situation of lower gate operation order is prevented.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The application provides an intelligent edge processing method with logical relationship power switch quantity, and the specific steps include: S1, two input ports are formed by collecting signals and high level signals, and the signals are stored in gateway memory through an AND gate circuit as current data of switches; the data stored in the gateway is expressed as follows: A x ={S1, S2, S3, S4, S5...S n} (1); S2, the data of all current switches are re-collected at a preset switch collection frequency; the data set is: A' x ={S'1, S'2, S'3, S '4 , S'5...S' n} (3); S3, if S n +S' n =0, it is indicated that the switch is not in a variable position, the result is input into the gateway memory as a feedback signal, and the switch state at the latest time is updated; if S n +S' n =1, it is indicated that the switch has been in a variable position, the signal is sent to a background in real time, and a power system topology is updated according to the signal.

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

The invention relates to an electric wheelchair safety braking system and method based on double-MCU redundancy control, and aims to solve the problems of single-point failure, safety response delay, large braking impact and the like of a single-MCU control framework of an existing electric wheelchair. According to the invention, a master-slave dual-MCU cooperative control architecture is adopted, a master MCU is responsible for whole system core control and sends heartbeat packets to a slave MCU in a 10ms period, and the slave MCU monitors the position of a rocker and the deceleration response state of the master MCU in real time; meanwhile, a hardware-level AND gate logic circuit is arranged to achieve interlocking of output signals of the master MCU and the slave MCU, the slave MCU is provided with an S-curve braking algorithm module, when the master MCU does not trigger a deceleration instruction in a preset window period after the Hall rocker is centered, the slave MCU will generate a progressive PWM modulation signal to achieve stable braking and send a fault mark to the master MCU, and the master MCU stores fault data to a nonvolatile memory. According to the method, the fault response time can be shortened to be within 100 ms, the braking deceleration is smaller than or equal to 0.3 g, and the method can be widely applied to high-reliability motion control systems such as electric wheelchairs and medical robots.

This invention relates to the field of substations and discloses a reliability analysis method for the communication network of a substation secondary system. Taking the overall failure of the substation communication network as the top event, and based on an autonomous and controllable substation safety partitioning architecture, the direct causes leading to the top event are decomposed into multiple intermediate events. A top-level fault tree model is constructed using logical OR gate relationships. Each intermediate event is recursively expanded hierarchically to form an initial subtree. Combining the characteristics of dual-network redundancy and dual-configuration of equipment, the redundancy mechanism is equivalent to AND gate logic and added to the initial subtree to obtain a partitioned subtree model. Equipment-level faults are extracted from the partitioned subtree as bottom events and standardized. Based on engineering statistical data, their failure rate and repair rate are determined. After calculating the unavailability, probability calculations are performed from bottom to top to obtain the overall system availability. This method can accurately output the overall availability of the substation secondary system communication network.

The invention relates to the technical field of chip testing, in particular to a chip testing sub-mode entry system, which is characterized in that a mode decoder sets a signal of a corresponding testing sub-mode as a preset second level according to sub-mode entry information and coding information corresponding to M testing sub-modes, the signal of the test sub-mode and the signal of the test mode serve as the input of an AND gate corresponding to the test sub-mode, the AND gate corresponding to the test sub-mode serves as the input of a test selector, and when the signal of the test sub-mode and the signal of the test mode are both preset second levels, the test selector enters the test sub-mode; the mode register can be configured and the test sub-mode can be entered only by two interfaces of the first communication port, and the two interfaces can be released after entering the test sub-mode and used for participating in test excitation input, so that the reusability of the interfaces is improved, the chip area is effectively saved, the chip design and manufacturing cost is reduced, and the test efficiency is improved. And the convenience of entering the chip sub-test mode is also improved.

The application provides a decoherence time improving method based on mutual inductance adjustment and junction asymmetry compensation, and belongs to the technical field of superconducting quantum computation. The method comprises the following steps: constructing a superconducting quantum bit theoretical model comprising a non-equilibrium mutual inductance and a non-symmetrical Josephson junction; determining the core basic parameters and constraint conditions of the double-junction superconducting quantum bit, deducing a mutual inductance balance compensation condition, adjusting a magnetic flux line ground position, changing the numerical relationship of mutual inductances of left and right arms, and eliminating the relaxation caused by mutual inductance imbalance; defining a junction asymmetry parameter and a mutual inductance imbalance degree, deducing a relaxation compensation condition, making the relaxation caused by mutual inductance imbalance and the relaxation caused by junction asymmetry cancel each other out, and improving the decoherence time of the superconducting quantum bit. The application establishes a quantitative relationship between mutual inductance adjustment and junction asymmetry compensation, realizes relaxation cancellation by using the interaction between mutual inductance imbalance and junction asymmetry, and significantly improves the decoherence time and gate fidelity of the quantum bit.

The application relates to a parallelized fault tree minimal cut set solving method based on bit set minimal cut set representation, and relates to the field of fault tree analysis. In order to solve the problems of redundant cut set data representation, insufficient parallelization degree, low calculation and storage efficiency and difficulty in supporting efficient solving of large-scale complex systems in the prior art, the method generates a standardized equivalent logical structure concise form fault tree by structurally simplifying and modularly decomposing a fault tree model; an intermediate event and a module solving queue are established according to a topological relationship; a multi-core parallel computing environment is established, a bit set is used to represent a cut set and a two-dimensional data array is formed; a bit-by-bit or broadcast operation is performed for an and gate, and row splicing and merging are performed for an or gate, so that parallel calculation of logical gate outputs is realized; and then non-minimal cut sets are screened out through parallel simplification, and a top event minimal cut set result is output. The application is suitable for fault tree analysis and fast solving of minimal cut sets of complex systems such as nuclear power, aerospace, chemical industry and rail transit.

The embodiment of the invention provides a clock signal calibration circuit and method and a chip, and the circuit is characterized in that the output end of a first clock delay module is connected with the input end of a second clock delay module through a phase inverter, and the output end of the first clock delay module is connected with the input end of a clock information detection module through a first AND gate; the output end of the second clock delay module is connected with the input end of the clock information detection module through the first AND gate, and the first clock delay module is used for receiving and adjusting an original clock signal and outputting a first clock signal to the phase inverter and the first AND gate; the second clock delay module is used for receiving and adjusting the first clock signal subjected to logic NOT execution through the phase inverter and outputting a second clock signal to the first AND gate; the clock information detection module is used for receiving a target clock signal and determining a first parameter used for calibrating the target clock signal. The problems that a clock calibration technology is low in precision and large in energy consumption are solved, and the effects of improving clock signal calibration precision and reducing energy consumption are achieved.

The invention discloses a digital chip cross-clock domain processing method under a special application scene, and belongs to the technical field of digital chip cross-clock domain processing. The problem that an existing method is not suitable for special application scenes is solved, six triggers and two AND gate logic programs are used for continuously beating a clock in a source clock domain by using a clock in a target clock domain for three beats, logic AND operation is carried out on negation signals for beating a second beat and a third beat, and a switching signal is generated; the data of the source clock domain is continuously beaten for two beats by using a target clock domain clock, the synchronized data and a switching signal are subjected to AND gate logical operation, and a signal output by an AND gate is the synchronized data, so that cross-clock domain processing is realized; meanwhile, it can be effectively guaranteed that only when the data of the source clock domain changes, the output signal is updated, and therefore unnecessary energy consumption is avoided; compared with other methods, the method has the advantages that the chip area can be reduced, and the cost is reduced.

The invention discloses an asynchronous logic circuit suitable for a loop expansion type SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) and the loop expansion type SAR ADC. The asynchronous logic circuit comprises a two-input exclusive-OR gate unit, a delay unit, a D trigger unit and a four-input AND gate unit. According to the embodiment of the invention, the problems that the performance of the asynchronous clock is influenced by the metastable state, the power consumption is high and the speed is low in the prior art are solved.

The utility model relates to the technical field of energy storage, in particular to a maximum pulse width limiting circuit based on a DQ trigger and a logic gate, which comprises the DQ trigger, a logic AND gate circuit and an RC circuit, the clock end of the DQ trigger is connected with the PWM generator, and the data end D and the setting end Sn of the DQ trigger are connected with a fixed high level; and a negative output pin Qn and a reset pin Rn of the DQ trigger are connected to the RC circuit. The maximum pulse width limitation is directly realized through hardware logic, and the problems of high response delay and dependence on software reliability in the prior art are solved by utilizing the rising edge detection characteristic of the DQ trigger, the charging and discharging characteristic of the RC network and the real-time comparison function of the logic gate without software intervention.

The invention discloses an SAT elastic logic locking module for improving output damage, a module variant and application, and relates to the technical field of hardware security, the SAT elastic logic locking module comprises an n-bit traveling wave carry adder, a controllable output damage unit and a first AND gate; the module variant of the SAT elastic logic locking module is that a comparator and a second AND gate are added on the basis of the SAT elastic logic locking module; an SAT elastic logic locking module or a module variant forms an integrated circuit with an SFLL or an SARLock, and the integrated circuit can be applied to resisting deletion attacks, sensitization attacks, function analysis attacks and AppSAT attacks. According to the method, the effective resistance to the SAT attack is realized, and a new technical enlightenment is provided for the development of an SAT attack resistance technology.

The neural processing element is configured with a hardware AND gate configured to perform a logical AND operation between the symbol extension signal and a most significant bit ("MSB") of an operand. The state of the symbol spread signal may be based on the type of layer of a deep neural network ("DNN") that generates an operand. If the symbol spread signal is logically false, no signal spread is performed. If the symbol extension signal is logically true, a coupler couples the output of the hardware AND gate and the operand to extend the operand from an N-bit unsigned binary value to an N + 1-bit signed binary value. The neural processing element may also include another hardware AND gate and another coupler for similarly processing another operand. The output of the coupler for the two operands is provided to a hardware binary multiplier.

This application provides a method and apparatus for cutting quantum circuits. The method includes dividing the quantum circuit to obtain two bits of data; generating cutting position data based on the quantum circuit and the two bits; cutting the quantum circuit based on the cutting position data to obtain circuit cutting information, which includes two initial quantum sub-circuits; updating the wire cutting position and gate cutting position to obtain new cutting position data if either initial quantum sub-circuit does not meet the bit number constraint; determining the circuit cutting cost for generating new circuit cutting information based on the new cutting position data if the new initial quantum sub-circuit meets the bit number constraint; and determining the target circuit cutting information from multiple new circuit cutting information or from existing circuit cutting information based on the circuit cutting cost.

The invention discloses a matrix parallel computing method for solving a minimum cut set of a fault tree, and relates to the field of fault tree analysis. The matrix parallel computing method for solving the minimum cut set of the fault tree aims at solving the problems that in the prior art, the computing process is serialized, the parallel efficiency is low, a data structure is not matched with a GPU architecture, and the minimum cut set of the large-scale fault tree cannot be efficiently solved. According to the method, structured coding is carried out on a fault tree, and gate events and input relations are constructed into a structure description matrix; vectorizing the basic event and representing a candidate cut set of the intermediate event in a binary matrix form; under a GPU parallel architecture, row merging is performed on an OR gate, broadcast type combination is performed on an AND gate, parallel cut set simplification is performed, and meanwhile, a blocking and cache multiplexing strategy is introduced to improve the calculation throughput rate and reduce memory occupation. And carrying out loop iteration until the top event matrix is stable, and outputting a minimum cut set. The method is suitable for safety and reliability analysis of a large complex engineering system.

A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared variables in the register stage. Thus, the inputs to the cross-domain multiplication and the compression are performed on variables that have been refreshed by additional randomness. This AND gate does not need statistically independent inputs, is secure in the probing model even in the presence of glitches, also known as the robust probing model. A two-domain input and two domain output AND gate can be implemented using six (6) registers, four (4) two input logical AND gates, and eight (8) exclusive-OR (XOR) gates. The AND gate may also be used to implement an AES S-box that has two (2) register stages and takes two (2) clock cycles per computation.

The invention relates to the technical field of semiconductors, in particular to a characterization method and device for residual amorphous silicon between a fin and a grid electrode. The characterization method of the residual amorphous silicon between the fin and the grid electrode comprises the following steps: shooting a top view of a sample to be tested, and selecting a test area and a reference area; wherein the test area comprises an included angle between the fin and the grid electrode, and the content of residual amorphous silicon in the reference area is zero; respectively carrying out energy spectrum testing on the testing area and the reference area, and drawing a first curve graph of the silicon content of the testing area along with the position change and a second curve graph of the silicon content of the reference area along with the position change; and calculating the difference between the half-peak widths of the first curve graph and the second curve graph as the characteristic size of the residual amorphous silicon between the fin and the grid electrode. According to the method and the device for characterizing the residual amorphous silicon between the fin and the grid electrode provided by the invention, the accuracy and the stability of a characterization result are relatively high; in addition, the method has the advantages of high efficiency and low cost, and can be widely used.

The application discloses a parallel testing device and method for a multi-stack memory package. The parallel testing device comprises a testing machine and a first number of AND gate operators. The testing machine comprises a first number of comparators. The outputs of the first number of AND gate operators are connected to the first inputs of the first number of comparators one by one. The first inputs of each AND gate operator are connected to pins with the same preset identification of each single memory at the same time, and the preset identifications of the pins connected to the first inputs of each AND gate operator are different from each other. The second inputs of the AND gate operators are used for inputting a preset reference voltage. The second inputs of the comparators are used for inputting a preset expected voltage. The parallel testing device for the multi-stack memory package can simultaneously perform parallel testing on a plurality of single memories in the multi-stack memory package, thereby greatly reducing the testing time, improving the testing efficiency, and reducing the testing time cost.

Computer systems and methods are provided for compiling a computer program to run on a quantum processor comprising a plurality of qubits, qudits or quantum continuous variables. A compiler obtains the program in a unified language, that is effectively a classical language, as opposed to a quantum language, and performs code refactoring on all or a portion of the program to form a refactored code and converts the refactored code into a first code. The compiler compiles the first code into a second code comprising a plurality of data elements in one or more quantum data structures. The compiler converts the second code to a third code expressed in a quantum gate-level language in accordance with an instruction set and gate locality constraints of the target quantum processor.