166 results about "Semi insulating" patented technology

The invention relates to the field of silicon carbide wafer preparation, in particular to a semi-insulating silicon carbide wafer annealing device and method, the annealing device comprises a crucible cover and a graphite crucible which are detachably connected, an annealing chamber is arranged in the graphite crucible, the annealing chamber comprises a wafer supporting area and a powder area, and the powder area is arranged in the crucible cover. The gas pressure control assembly is used for controlling gas components and pressure intensity in the annealing chamber; the heating device is used for heating the annealing chamber in a partitioned manner; and the heat preservation system is arranged outside the crucible cover and the graphite crucible in a sleeving manner. By means of the annealing device, the problems of silicon carbide wafer intrinsic point defect screening and concentration control can be effectively solved, the Fermi energy level is controlled at the EH6 / 7 energy level position, and the silicon carbide wafer obtained through annealing finally achieves control over the electrical resistivity larger than 1E12 ohm cm.

The invention discloses a wavelength-tunable high-speed EML laser which comprises a substrate and four functional areas which are arranged on the substrate and are connected in sequence, wherein the four functional areas include an electric absorption modulation area (EAM), a gain area, a phase regulation and control area and a distributed Bragg reflection area (DBR). Wherein the P / N type electrodes of the functional areas are uniformly distributed on the same main surface of the chip to form a coplanar electrode structure; according to the laser, a coplanar P / N electrode structure is adopted, an EAM area, a gain area, a phase regulation and control area and a DBR area are integrated, the refractive indexes of the phase regulation and control area and the DBR area are jointly regulated and controlled through current injection, fast-response wide-range wavelength tuning is achieved, all the electrodes are evenly distributed on the same main surface of a chip, stray capacitance is remarkably reduced, high-frequency modulation performance is improved, and the laser is suitable for wide-range wavelength tuning. The device grows based on the semi-insulating InP substrate, so that the electrical isolation is enhanced, the transverse electric leakage and the crosstalk between the function intervals are effectively inhibited, and the integration consistency and stability are improved.

The subject of the present disclosure provides the production of N-type or P-type or semi-insulating rutile germanium dioxide templates and thin films in order to obtain sun-blind photo detectors from optical systems in the ultraviolet (UV) wavelength, or to obtain UV light emitting diodes, or to produce semiconductor materials required for UV laser diode production, especially for use in the field of power electronics in the defence industry and / or in missile and aircraft tracking systems. The disclosure describes a system and a method for growing r-GeO2 (rutile germanium dioxide) template and thin films using the chemical vapour deposition (CVD) method.

The invention discloses a preparation method of a gallium oxide semi-insulating substrate and the gallium oxide semi-insulating substrate, which comprises the following steps: performing proton irradiation treatment on a gallium oxide single-crystal substrate to introduce lattice defects into the gallium oxide single-crystal substrate, and performing annealing treatment on the gallium oxide single-crystal substrate into which the lattice defects are introduced to obtain the gallium oxide semi-insulating substrate. According to the technical scheme, lattice defects are introduced into the gallium oxide single crystal substrate by adopting a proton irradiation process to form a deep energy level trap to effectively capture free carriers, so that the carrier concentration of the material is remarkably reduced, and the resistivity of the material is increased, thereby realizing stable conversion from a conductive state to a semi-insulating state; therefore, the conditions of poor doping uniformity, insufficient thermal stability and local resistivity fluctuation existing in a traditional element doping method are overcome, meanwhile, the defects of lattice mismatch, insufficient thermal conductivity and the like caused by a heterogeneous substrate are avoided, and the electrical property uniformity and the material structure integrity of the gallium oxide substrate are effectively improved. The method has the advantages of non-contact, low cost, easy regulation and control and the like.

The invention discloses an IGBT device, a preparation method and a preparation system thereof, and a storage medium. The device comprises a substrate; the second groove region and the first groove region are formed in the substrate; the semi-insulating material layer is formed in the first groove region and the second groove region; a CS layer, a Pwell layer and an NSD layer; a contact hole penetrating from top to bottom; the contact hole is filled with a metal contact layer. According to the invention, the first groove region and the second groove region are formed on the side wall of the first HM layer, gate oxidation, polysilicon filling and the second HM layer are carried out in sequence, ion implantation and annealing are carried out, and the gate oxide layer between the grooves is used as a barrier mask to realize etching of the contact hole. The method is suitable for forming the contact hole under the condition that the cellular mesa is small, photoetching sleeve deviation between the contact hole and the groove can be effectively avoided, so that the in-chip consistency of saturation voltage drop is greatly improved, and meanwhile, a wider upper opening can be formed so as to be beneficial to further reducing the conduction voltage drop of a device.

The application discloses a silicon carbide-based high-resistance resistor, which comprises a semi-insulating 4H-SiC type silicon carbide substrate, symmetric aluminum oxide insulation layers with an atomic thickness are arranged on a silicon surface and a carbon surface of the silicon carbide substrate, the thickness of the aluminum oxide insulation layer is 0.2nm-2nm, and conductive metal electrodes are evaporated on two sides of the aluminum oxide insulation layer, and the thickness of the metal electrode is 100nm-500nm. The silicon carbide-based high-resistance resistor with the above structure is used to make an ohmic contact electrode on the semi-insulating silicon carbide substrate, so that a resistor with a resistance value of 100TΩ or more is obtained, and the needs of the precision measurement industry are met.

The invention discloses a manufacturing process of a silicon carbide substrate based on DBA and DPC processes, and relates to the technical field of semiconductors. The silicon carbide substrate is prepared by cleaning semi-insulating silicon carbide, sputtering a seed layer for the first time, performing DBA aluminum plating and sintering, sputtering the seed layer for the second time, performing pattern transfer for the first time, electroplating a lead, performing pattern transfer for the second time, electroplating and thickening a copper seed layer, performing surface treatment, electroplating nickel and gold, electroplating a metal layer and performing scribing and forming. According to the manufacturing process, a semi-insulating silicon carbide substrate and a negative film process are adopted for manufacturing, a layer of aluminum film is additionally arranged on the basis to serve as a connecting layer between copper and the substrate, and the service life of the whole heat sink is greatly prolonged while efficient heat conduction transmission is guaranteed; the silicon carbide has excellent thermal conductivity and strength, and has good performance in coping with high temperature and high pressure when the laser works, so that the service life of the laser is greatly prolonged, and the performance of the laser is greatly improved.

The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.

The invention discloses a mid-infrared laser based on three-device on-chip integration and a preparation method thereof, relates to the crossing field of a semiconductor laser technology and an optical communication technology, and solves the problem that the existing quantum cascade laser QCL technology cannot give consideration to both high modulation rate and high power. An intermediate infrared laser comprises a QCL unit, an EAM unit and an SOA unit which are sequentially arranged on a substrate. The substrate comprises a semi-insulating InP (Indium Phosphate); the QCL unit, the EAM unit and the SOA unit share the same ridge-shaped waveguide structure and grow through epitaxy butt joint. The method provided by the invention is suitable for a mid-infrared band space communication scene with high requirements on the laser modulation rate, the output power and the single-mode stability.

The invention relates to the field of semiconductor production, in particular to high-purity semi-insulating silicon carbide heat treatment equipment which comprises a base, and a heat treatment mechanism and a lifting mechanism are arranged on the base. A plurality of heating modules are arranged in the heating cylinder, the lifting mechanism comprises a supporting frame, connecting plates are symmetrically arranged on the supporting frame, the connecting plates can move up and down along the supporting frame, and the connecting plates are fixedly connected to the upper end face of the end cover; lifting rods are symmetrically arranged on the lower surface of the end cover, a supporting plate is fixedly connected to the end parts of the lifting rods, and a crucible is placed on the supporting plate; a structure capable of completely placing materials in a stable environment for heat treatment is arranged, namely, a crucible is arranged in a heating cylinder with a heat preservation layer, the quality of the materials after heat treatment can be guaranteed, a plurality of probes of a temperature monitoring instrument are arranged, the heat treatment temperature is controlled, then a lifting mechanism is arranged, the crucible is arranged on an end cover, and the heat treatment temperature is controlled. The crucible can move along with the end cover, and feeding and discharging operation of the crucible and materials is facilitated.

1. The name of the design product: semi-insulating pole-mounted quick access device. 2. The use of the design product: the design product is used in the field of complete equipment for electric power, realizing quick access on the electric power system. 3. The design points of the design product: the shape of the product of design 1, the shape, color and their combination of the product of design 2. 4. The picture or photo best indicating the design points: the perspective view of design 2. 5. The design for which protection is sought contains color. 6. Design 1 is designated as the basic design.

This optical modulator-integrated semiconductor laser (500) is provided with a semiconductor laser unit (101) formed on a semi-insulating substrate (1), a first connection waveguide unit (102), a first EA modulator unit (103), a second connection waveguide unit (104), a second EA modulator unit (105), and a first EA modulator n-type electrode (31) provided in the first EA modulator unit (103) and a second EA modulator unit (105) provided in the second EA modulator unit (105). And a first common electrode (45) electrically connected to the second EA modulator p-type electrode (42).

A semiconductor device includes, within an outer peripheral region: an outer peripheral p-type layer; an outer peripheral n-type layer positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer arranged to include a portion of an upper surface of a semiconductor substrate located between the outer peripheral p-type layer and the outer peripheral n-type layer; a drift n-type layer extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode disposed above the high breakdown voltage p-type layer via an interlayer insulating film and electrically connected to an upper electrode; and a semi-insulating film covering the upper surface between the protective electrode and the outer peripheral n-type layer and having a resistivity of 1×108 Ω·cm to 1×1014 Ω·cm at 25° C.

The invention provides a photoconductive switch of a comb electrode, which comprises a semi-insulating gallium arsenide substrate layer, a low-temperature gallium arsenide layer and an insulating protective layer, and is characterized in that the low-temperature gallium arsenide layer is formed on the semi-insulating gallium arsenide substrate layer, and the insulating protective layer is arranged on the low-temperature gallium arsenide layer; a switch anode and a switch cathode are respectively formed on the inner side of the low-temperature gallium arsenide layer surface insulation protection layer; a comb-shaped electrode is arranged on the surface of the low-temperature gallium arsenide layer and located at the switch anode. According to the invention, by arranging the comb-shaped electrode structure, a plurality of comb-tooth electrodes which are distributed in a staggered manner are formed in the electrode region, so that the action area of incident light and a semiconductor active region is increased under an illumination condition, and generation and collection of photon-generated carriers are facilitated; meanwhile, the distribution state of an electric field near the electrode is improved, and the possibility of local electric field concentration is reduced; in addition, a low-temperature gallium arsenide material is adopted as the photoconductive layer, the service life of a current carrier is short, and the device is suitable for photoelectric trigger application scenes with requirements for response speed and stability.

The application provides a shield gate trench VDMOS device and a preparation method thereof. The device comprises a substrate, an intermediate layer, a semi-insulating layer and a gate layer. The intermediate layer is arranged on the upper side of the substrate and comprises a drift layer and a source layer. The drift layer is arranged on the substrate, and the upper side of the drift layer is provided with the source layer. At least one trench is formed in the intermediate layer. The semi-insulating layer is arranged in the trench, contacts the drift layer and has a resistivity. The gate layer is arranged in the trench, is close to the source layer and contacts the upper surface of the semi-insulating layer. The device has improved withstand voltage capacity through improvement of the structure in the trench.

Provided here are: a mesa strip which has an n-type cladding layer, an active layer and a p-type cladding layer that are stacked sequentially on a surface of an n-type substrate; Fe-doped semi-insulating layers which are embedded along both sides of the mesa stripe, each up to a height higher than the mesa stripe; n-type blocking layers which are stacked on respective surfaces of the Fe-doped semi-insulating layers located on the both sides of the mesa stripe, and which are spaced apart from each other with an interval that is a space corresponding to a central portion of the active layer and is thus narrower than the active layer; p-type cladding layers which are formed on back surfaces of respective mesa-stripe-side end portions of the n-type blocking layers; and a p-type cladding layer which buries a top of the mesa stripe, the p-type cladding layers and the n-type blocking layers.

The present disclosure relates to the technical field of optoelectronics, and in particular to a resonance-enhanced mesa-type photodetector based on a chirped Bragg reflector. The photodetector comprises: a high-reflectance structure on a P-type ohmic contact layer, a P-type epitaxial layer, a graded doping absorption layer, an annular metal electrode on an N-type ohmic contact, an N-type epitaxial layer, a chirped Bragg reflector, and a semi-insulating indium phosphide substrate, which are sequentially formed from top to bottom.

The invention relates to the technical field of preparation of silicon carbide crystals, and discloses a crucible for growing high-purity semi-insulating silicon carbide crystals, which comprises an inner container layer, a transition layer and an outer support layer which are sequentially compounded from inside to outside, the inner container layer of the crucible is of a composite structure of a high-purity tantalum carbide matrix and rare earth oxide, rare earth elements form a continuous segregation layer through a grain boundary diffusion behavior in a high-temperature crystal growth environment, grain boundary active sites are passivated, oxygen impurities are prevented from permeating inwards, meanwhile, gradual matching of thermal expansion coefficients is achieved through the gradient material design of the transition layer, and the thermal expansion coefficient is increased. The interface stress in the thermal cycle process is fully absorbed, the interlayer stripping risk is avoided, so that high stability and long service life of the semi-insulating characteristic of the silicon carbide crystal are guaranteed, the microgroove array structure arranged on the outer surface of the inner container layer is subjected to pyrolytic carbon coating treatment, a regular gaseous substance transmission path is constructed, the polymorphic phase change tendency of a crystal growth interface is reduced, and the service life of the silicon carbide crystal is prolonged. Therefore, a silicon carbide single crystal structure with uniform height and no inclusion is obtained.

A semiconductor device includes a substrate, an insulator layer, and a field plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type complementary to the first conductivity type. The insulator layer is formed on a main surface of the substrate. The field plate structure is formed on the insulator layer between the first doped region and an edge structure. The field plate structure has a high-resistive and / or semi-insulating connection with at least one non-floating conductive structure.

The invention discloses a single-photon avalanche detector with high detection efficiency and a preparation method of the single-photon avalanche detector. The single-photon avalanche detector comprises a semi-insulating substrate, an n + InGaAs substrate epitaxial layer, an n + InAlAs substrate epitaxial layer, an i: InAlAs epitaxial multiplication layer, a p + InAlAs charge layer, an InAlAs / InAlGaAs superlattice gradient layer, an InAlGaAs / InGaAs superlattice absorption layer, a p +: InAlAs epitaxial layer and a p +: InP epitaxial layer which are sequentially arranged from bottom to top, the InAlAs / InAlGaAs superlattice gradient layer is arranged in a periodic cycle mode, and the InAlGaAs / InGaAs superlattice absorption layer is arranged in a periodic cycle mode. Compared with the prior art, the quantum efficiency of the device can be improved, the width of a depletion region can be increased, the electric field of the absorption layer is reduced, and the carrier collection efficiency is improved.

Group III oxide semiconducting devices with effective device isolation and edge termination regions.

The invention discloses an annular micro-cavity quantum cascade laser. The laser comprises substrates which are sequentially arranged from bottom to top; the annular microcavity is arranged on the substrate, the annular microcavity is an elliptical resonator with a notch, and a groove is formed in the central area of the annular microcavity; the semi-insulating InP: Fe filling layer is arranged in the groove in the central area of the annular microcavity, and the difference between the resistivity of the semi-insulating InP: Fe filling layer and the refractive index of the upper cladding and the contact layer is less than 1%; the supporting ridges are arranged on the substrate, and the two supporting ridges are arranged on the two sides of the annular microcavity and are as high as the annular microcavity; the coplanar electrode comprises a central electrode arranged on the upper surface of the annular microcavity and grounding electrodes symmetrically arranged on the outer surface of the supporting ridge structure, and the central electrode and the grounding electrodes are the same in height. The quantum cascade laser has high-frequency modulation performance, improves heat dissipation performance, and has high response rate.

The invention provides a manufacturing method of a crimping type high-power high-voltage diode chip, and relates to the technical field of power semiconductor device manufacturing, and the method comprises the steps: forming an annular groove in the surface of a semiconductor wafer through laser grooving, and forming a circular PN junction isolation wall of a single chip in the groove in combination with a closed tube gallium-aluminum diffusion technology; carrying out boron-phosphorus double-substance diffusion in a unit cell region enclosed by the isolation wall to form a PN junction doping structure; a photoetching mask is adopted to limit an area, and a double-angle mesa structure is formed through chemical corrosion of an HF / HNO3 mixed solution; sequentially depositing a semi-insulating polycrystalline silicon layer and a double-layer glass passivation layer; performing laser cutting along the separating wall to separate the single chip; and sintering an anode molybdenum sheet on the anode surface of the chip, performing vacuum evaporation on a cathode aluminum film on the cathode surface of the chip, and alloying to form an electrode. According to the invention, the consistency and stability of chip manufacturing can be improved through the wafer-level mesa modeling and the inorganic passivation process.

The invention discloses a semi-insulating silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. At least one semi-insulating silicon carbide epitaxial layer located on one side of the substrate; and the first epitaxial layer is positioned on one side, far away from the substrate, of the at least one semi-insulating silicon carbide epitaxial layer. The semi-insulating silicon carbide epitaxial material can be effectively prepared, the quality of the first epitaxial layer is improved, the defects of the first epitaxial layer are reduced, and therefore the preparation requirements of different devices are met.

The invention provides an electro-absorption modulator and an optical semiconductor device which are excellent in high extinction ratio characteristics and high-speed operation. The electro-absorption modulator includes: a semi-insulating semiconductor layer; a first electro-absorption modulator section including a first n-type semiconductor layer, a first absorption layer, and a first p-type semiconductor layer; a second electro-absorption modulator section including a second p-type semiconductor layer, a second absorption layer, and a second n-type semiconductor layer; a connection waveguide layer disposed between the first absorption layer and the second absorption layer; a first EA electrode electrically connected to the first p-type semiconductor layer and electrically connected to the outside; a second EA electrode electrically connected to the second n-type semiconductor layer and electrically connected to the outside; and a connection medium configured to electrically connect the first n-type semiconductor layer and the second p-type semiconductor layer to each other.

The present invention addresses the problem of raising the breakdown voltage of a semiconductor device. This semiconductor device comprises a semiconductor substrate having an element region and an outer peripheral region. The semiconductor substrate comprises: an element p-type layer disposed in the element region; an outer peripheral p-type layer disposed in the outer peripheral region so as to surround the element region; an outer peripheral n-type layer disposed on the outer peripheral side of the outer peripheral p-type layer so as to be spaced apart from the outer peripheral p-type layer; and a breakdown voltage p-type layer located between the outer peripheral p-type layer and the outer peripheral n-type layer. The semiconductor device comprises: an interlayer insulating film disposed on a substrate upper surface; an upper electrode disposed in the element region; a specific electrode disposed in the outer peripheral region; a semi-insulating film disposed in a range from the upper electrode to the specific electrode; and a protective insulating film disposed on a surface of the semi-insulating film. The semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers a specific electrode corner part.

The invention is suitable for the technical field of sintering equipment, and provides a sintering machine coke powder distribution system which comprises a distribution device erected above a sintering ore vehicle and a lifting frame in sliding fit with the distribution device. A sintering layer is filled in the sintering ore vehicle; semi-insulating cylinders are fixed on the circumferential side surfaces of the two fixed rings; an insulating roller is rotationally arranged between the two fixing rings; a stirring part is arranged in the semi-insulating cylinder in a sliding manner; a first unipolar ion fan is fixed on the side surface of the fixed plate; insulating inserting plates are fixed at two ends of the lifting plate; according to the device, air with negative ions is input into the sintering layer through the second unipolar ion fan, so that the surface of the sintering layer is negatively charged, air with positive ions is input into the semi-insulating cylinder through the first unipolar ion fan, and coke powder is positively charged; coke powder with positive charges is controlled to fall down, the fallen coke powder is adsorbed by the surface of the sintering layer with negative charges, and the uniformity of coke powder distribution is improved.

The invention discloses a gallium nitride high-electron-mobility transistor with a fin-type gate and a preparation method of the gallium nitride high-electron-mobility transistor, and relates to the field of semiconductor devices. The semi-insulating high-resistance layer, the n-type doped layer, the back barrier layer and the channel layer are sequentially formed on the same side of the substrate; the surface of the side, away from the back barrier layer, of the channel layer comprises a source region, a gate region and a drain region which are sequentially distributed in the first direction; the source electrode is positioned in the source region; the drain electrode is positioned in the drain region; the gate region is provided with two grooves distributed in the second direction, and the bottoms of the grooves at least extend to the back barrier layer; the channel layer and the back barrier layer between the two grooves form a fin-type structure; the second direction and the first direction are vertical and parallel to the plane of the substrate; the grid electrode comprises a front grid electrode and a back grid electrode; a front gate electrode is arranged on one side, deviating from the substrate, of the fin-shaped structure; the bottoms of the two grooves are respectively provided with a back gate electrode. According to the invention, the control capability of the grid electrode on channel electrons can be improved.

The invention discloses a high-responsivity photoelectric detector using an air cavity, which is characterized in that a dilution waveguide, the air cavity and a photoelectric detector are integrated on a semi-insulating substrate, and the air cavity is obtained in a dilution waveguide layer in an etching and wafer bonding mode; and finally, the transition waveguide and the photoelectric detector table are etched according to a conventional technological process. When the photoelectric detector works, the vast majority of signal light incident from the side surface is gradually coupled to the active region under the guidance of the dilution waveguide in front of the air cavity, and the leakage of the light from the active region to the dilution waveguide and the semi-insulating substrate below is effectively inhibited due to the large refractive index difference between the air cavity and the surrounding material; most of the light is limited in the active area and is converted into an electric signal after being absorbed by the absorption layer. According to the air cavity structure, the penetration depth of evanescent waves at the interface of the dilution waveguide and the air cavity can be reduced, the concentration degree of light in an active area is effectively improved, and the responsivity of the photoelectric detector is improved.

The invention belongs to the technical field of SiC single crystal growth and discloses a semi-insulating SiC single crystal growth device and method.The semi-insulating SiC single crystal growth device comprises a heat preservation shell and a growth crucible, the growth crucible is placed in the heat preservation shell, and a first gap is reserved between the side wall of the growth crucible and the heat preservation shell; a plurality of first air channels are uniformly formed in the area, close to the crucible cover, of the upper part of the crucible body; the flow guide component is arranged in the crucible body, a plurality of second air channels are formed in the flow guide component, and the second air channels partially or completely coincide with the first air channels; a second gap is reserved between the flow guide component and the seed crystal; the graphite gas pipe penetrates through the top of the heat preservation shell, the gas outlet end of the graphite gas pipe faces a crucible cover of the growth crucible, and a third gap is reserved between the gas outlet end and the crucible cover. The problems of high impurity content, unqualified resistivity and the like of the semi-insulating silicon carbide single crystal are solved.