90 results about "Semi insulating" patented technology

The invention relates to the field of silicon carbide wafer preparation, in particular to a semi-insulating silicon carbide wafer annealing device and method, the annealing device comprises a crucible cover and a graphite crucible which are detachably connected, an annealing chamber is arranged in the graphite crucible, the annealing chamber comprises a wafer supporting area and a powder area, and the powder area is arranged in the crucible cover. The gas pressure control assembly is used for controlling gas components and pressure intensity in the annealing chamber; the heating device is used for heating the annealing chamber in a partitioned manner; and the heat preservation system is arranged outside the crucible cover and the graphite crucible in a sleeving manner. By means of the annealing device, the problems of silicon carbide wafer intrinsic point defect screening and concentration control can be effectively solved, the Fermi energy level is controlled at the EH6 / 7 energy level position, and the silicon carbide wafer obtained through annealing finally achieves control over the electrical resistivity larger than 1E12 ohm cm.

The invention discloses a manufacturing process of a silicon carbide substrate based on DBA and DPC processes, and relates to the technical field of semiconductors. The silicon carbide substrate is prepared by cleaning semi-insulating silicon carbide, sputtering a seed layer for the first time, performing DBA aluminum plating and sintering, sputtering the seed layer for the second time, performing pattern transfer for the first time, electroplating a lead, performing pattern transfer for the second time, electroplating and thickening a copper seed layer, performing surface treatment, electroplating nickel and gold, electroplating a metal layer and performing scribing and forming. According to the manufacturing process, a semi-insulating silicon carbide substrate and a negative film process are adopted for manufacturing, a layer of aluminum film is additionally arranged on the basis to serve as a connecting layer between copper and the substrate, and the service life of the whole heat sink is greatly prolonged while efficient heat conduction transmission is guaranteed; the silicon carbide has excellent thermal conductivity and strength, and has good performance in coping with high temperature and high pressure when the laser works, so that the service life of the laser is greatly prolonged, and the performance of the laser is greatly improved.

The application discloses a composite channel structure high electron mobility transistor and a preparation method thereof, and the transistor comprises a semi-insulating InP substrate, an undoped InAlAs buffer layer, an InP auxiliary channel, a first undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped In 0.7 Ga 0.3 As main channel, a second undoped In 0.22 Ga 0.78 As auxiliary channel, an undoped InAlAs isolation layer, a delta-doping layer, an undoped InAlAs barrier layer, an n + InGaAs source cap layer, an n + InGaAs drain cap layer, a source electrode, a drain electrode, a passivation layer and a gate electrode. The application can improve the breakdown voltage of the InP-based HEMT, maintain the output characteristics and cutoff frequency of the high In-component channel, improve the stability of transistor uniformity and repeatability, and meet the application requirements of the InP-based electronic device in the low-power low-noise and digital circuit field.

The invention relates to the field of semiconductor production, in particular to high-purity semi-insulating silicon carbide heat treatment equipment which comprises a base, and a heat treatment mechanism and a lifting mechanism are arranged on the base. A plurality of heating modules are arranged in the heating cylinder, the lifting mechanism comprises a supporting frame, connecting plates are symmetrically arranged on the supporting frame, the connecting plates can move up and down along the supporting frame, and the connecting plates are fixedly connected to the upper end face of the end cover; lifting rods are symmetrically arranged on the lower surface of the end cover, a supporting plate is fixedly connected to the end parts of the lifting rods, and a crucible is placed on the supporting plate; a structure capable of completely placing materials in a stable environment for heat treatment is arranged, namely, a crucible is arranged in a heating cylinder with a heat preservation layer, the quality of the materials after heat treatment can be guaranteed, a plurality of probes of a temperature monitoring instrument are arranged, the heat treatment temperature is controlled, then a lifting mechanism is arranged, the crucible is arranged on an end cover, and the heat treatment temperature is controlled. The crucible can move along with the end cover, and feeding and discharging operation of the crucible and materials is facilitated.

A semiconductor device includes, within an outer peripheral region: an outer peripheral p-type layer; an outer peripheral n-type layer positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer arranged to include a portion of an upper surface of a semiconductor substrate located between the outer peripheral p-type layer and the outer peripheral n-type layer; a drift n-type layer extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode disposed above the high breakdown voltage p-type layer via an interlayer insulating film and electrically connected to an upper electrode; and a semi-insulating film covering the upper surface between the protective electrode and the outer peripheral n-type layer and having a resistivity of 1×108 Ω·cm to 1×1014 Ω·cm at 25° C.

The invention provides a photoconductive switch of a comb electrode, which comprises a semi-insulating gallium arsenide substrate layer, a low-temperature gallium arsenide layer and an insulating protective layer, and is characterized in that the low-temperature gallium arsenide layer is formed on the semi-insulating gallium arsenide substrate layer, and the insulating protective layer is arranged on the low-temperature gallium arsenide layer; a switch anode and a switch cathode are respectively formed on the inner side of the low-temperature gallium arsenide layer surface insulation protection layer; a comb-shaped electrode is arranged on the surface of the low-temperature gallium arsenide layer and located at the switch anode. According to the invention, by arranging the comb-shaped electrode structure, a plurality of comb-tooth electrodes which are distributed in a staggered manner are formed in the electrode region, so that the action area of incident light and a semiconductor active region is increased under an illumination condition, and generation and collection of photon-generated carriers are facilitated; meanwhile, the distribution state of an electric field near the electrode is improved, and the possibility of local electric field concentration is reduced; in addition, a low-temperature gallium arsenide material is adopted as the photoconductive layer, the service life of a current carrier is short, and the device is suitable for photoelectric trigger application scenes with requirements for response speed and stability.

The present disclosure relates to the technical field of optoelectronics, and in particular to a resonance-enhanced mesa-type photodetector based on a chirped Bragg reflector. The photodetector comprises: a high-reflectance structure on a P-type ohmic contact layer, a P-type epitaxial layer, a graded doping absorption layer, an annular metal electrode on an N-type ohmic contact, an N-type epitaxial layer, a chirped Bragg reflector, and a semi-insulating indium phosphide substrate, which are sequentially formed from top to bottom.

A semiconductor device includes a substrate, an insulator layer, and a field plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type complementary to the first conductivity type. The insulator layer is formed on a main surface of the substrate. The field plate structure is formed on the insulator layer between the first doped region and an edge structure. The field plate structure has a high-resistive and / or semi-insulating connection with at least one non-floating conductive structure.

Group III oxide semiconducting devices with effective device isolation and edge termination regions.

The invention discloses an annular micro-cavity quantum cascade laser. The laser comprises substrates which are sequentially arranged from bottom to top; the annular microcavity is arranged on the substrate, the annular microcavity is an elliptical resonator with a notch, and a groove is formed in the central area of the annular microcavity; the semi-insulating InP: Fe filling layer is arranged in the groove in the central area of the annular microcavity, and the difference between the resistivity of the semi-insulating InP: Fe filling layer and the refractive index of the upper cladding and the contact layer is less than 1%; the supporting ridges are arranged on the substrate, and the two supporting ridges are arranged on the two sides of the annular microcavity and are as high as the annular microcavity; the coplanar electrode comprises a central electrode arranged on the upper surface of the annular microcavity and grounding electrodes symmetrically arranged on the outer surface of the supporting ridge structure, and the central electrode and the grounding electrodes are the same in height. The quantum cascade laser has high-frequency modulation performance, improves heat dissipation performance, and has high response rate.

The invention provides an electro-absorption modulator and an optical semiconductor device which are excellent in high extinction ratio characteristics and high-speed operation. The electro-absorption modulator includes: a semi-insulating semiconductor layer; a first electro-absorption modulator section including a first n-type semiconductor layer, a first absorption layer, and a first p-type semiconductor layer; a second electro-absorption modulator section including a second p-type semiconductor layer, a second absorption layer, and a second n-type semiconductor layer; a connection waveguide layer disposed between the first absorption layer and the second absorption layer; a first EA electrode electrically connected to the first p-type semiconductor layer and electrically connected to the outside; a second EA electrode electrically connected to the second n-type semiconductor layer and electrically connected to the outside; and a connection medium configured to electrically connect the first n-type semiconductor layer and the second p-type semiconductor layer to each other.

The present invention addresses the problem of raising the breakdown voltage of a semiconductor device. This semiconductor device comprises a semiconductor substrate having an element region and an outer peripheral region. The semiconductor substrate comprises: an element p-type layer disposed in the element region; an outer peripheral p-type layer disposed in the outer peripheral region so as to surround the element region; an outer peripheral n-type layer disposed on the outer peripheral side of the outer peripheral p-type layer so as to be spaced apart from the outer peripheral p-type layer; and a breakdown voltage p-type layer located between the outer peripheral p-type layer and the outer peripheral n-type layer. The semiconductor device comprises: an interlayer insulating film disposed on a substrate upper surface; an upper electrode disposed in the element region; a specific electrode disposed in the outer peripheral region; a semi-insulating film disposed in a range from the upper electrode to the specific electrode; and a protective insulating film disposed on a surface of the semi-insulating film. The semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers a specific electrode corner part.

The invention discloses a high-responsivity photoelectric detector using an air cavity, which is characterized in that a dilution waveguide, the air cavity and a photoelectric detector are integrated on a semi-insulating substrate, and the air cavity is obtained in a dilution waveguide layer in an etching and wafer bonding mode; and finally, the transition waveguide and the photoelectric detector table are etched according to a conventional technological process. When the photoelectric detector works, the vast majority of signal light incident from the side surface is gradually coupled to the active region under the guidance of the dilution waveguide in front of the air cavity, and the leakage of the light from the active region to the dilution waveguide and the semi-insulating substrate below is effectively inhibited due to the large refractive index difference between the air cavity and the surrounding material; most of the light is limited in the active area and is converted into an electric signal after being absorbed by the absorption layer. According to the air cavity structure, the penetration depth of evanescent waves at the interface of the dilution waveguide and the air cavity can be reduced, the concentration degree of light in an active area is effectively improved, and the responsivity of the photoelectric detector is improved.

This invention relates to the field of silicon carbide crystal preparation technology, and discloses a crucible for growing high-purity semi-insulating silicon carbide crystals, comprising an inner liner layer, a transition layer, and an outer support layer sequentially composited from the inside out. The inner liner layer of the crucible adopts a composite structure of high-purity tantalum carbide matrix and rare earth oxides. Under high-temperature crystal growth environment, rare earth elements form a continuous segregation layer through grain boundary diffusion behavior, passivating active sites at grain boundaries and preventing oxygen impurities from penetrating inward. At the same time, the gradient material design of the transition layer achieves progressive matching of the coefficient of thermal expansion, fully absorbing the interfacial stress during thermal cycling and avoiding the risk of interlayer delamination, thereby ensuring the high stability and long service life of the semi-insulating properties of silicon carbide crystals. The microgroove array structure set on the outer surface of the inner liner layer is treated with pyrolytic carbon coating to construct a regular gaseous material transport path, reducing the tendency of polymorphic phase transitions at the crystal growth interface, thereby obtaining a highly uniform, inclusion-free silicon carbide single crystal structure.

The application relates to the technical field of semiconductor materials, in particular to a preparation method of a semi-insulating silicon carbide substrate, which comprises the following steps: mixing high-purity silicon powder and carbon powder according to a preset ratio to synthesize silicon carbide particles; performing crystal growth to obtain a silicon carbide crystal ingot; cutting, grinding and polishing the silicon carbide crystal ingot to obtain a silicon carbide single crystal substrate; and performing high-temperature annealing and impurity removal treatment on the silicon carbide single crystal substrate to obtain a high-purity semi-insulating silicon carbide substrate. In the cutting process, the following steps are included: cutting after pre-annealing treatment is performed on the silicon carbide crystal ingot; collecting contact pressure data, temperature data, cutting speed data, cooling liquid flow and integrity data in the cutting process, and then determining the optimal contact pressure and the optimal cutting temperature, so as to determine the adjustment mode of the cutting parameters. The application effectively improves the cutting quality and shortens the cutting time.

Apparatus is disclosed for generating and modulating the power of a laser beam to be transmitted in an optical communication fiber. The apparatus includes a laser source and an electro-absorption modulator located on a common insulating or semi-insulating substrate. The laser source generates the laser beam. A high- frequency electrical signal encodes data to be transmitted by the modulated laser beam. The modulator is differentially driven by the electrical signal, which is terminated on the common substrate to minimize cross talk with other data channels. Traveling-wave electrodes connecting segments of the modulator and a termination network maintain electrical signal integrity and minimize losses.

The utility model discloses a straight type semi-insulating terminal assembly machine which comprises a fixing frame, a supporting plate is fixed at the top of the fixing frame, a mounting seat is fixed at the top of the supporting plate, and a first fixing plate and a second fixing plate are fixed on one side of the mounting seat. A sheath positioning air cylinder is installed on the first fixing plate, a second sheath feeding air cylinder is connected to the second fixing plate in a sliding mode, and a first sheath feeding air cylinder is installed on one side of the second sheath feeding air cylinder. The top of the fixing frame is provided with a direct vibration feeder, the top of the direct vibration feeder is provided with a terminal guide rail, and according to the terminal assembling machine, through coherent cooperation of all the components, assembling of two terminals can be effectively and rapidly achieved on the assembling machine, the assembling efficiency of the terminals can be greatly improved, products of one batch can be assembled more rapidly, the assembling efficiency is improved, and the assembling efficiency is improved. And efficient production of products is achieved, and the equipment purchasing cost of enterprises is reduced.

The invention discloses a photoelectric detector chip integrated with double high-thermal-conductivity substrates and a preparation method and application of the photoelectric detector chip. The photoelectric detector chip comprises a diamond substrate, a metal electrode, a photoelectric detector active region, a passivation layer and a SiC substrate. The method comprises the following steps: firstly, growing a photoelectric detector epitaxial layer on an InP semi-insulating substrate; the obtained InP epitaxial wafer is bonded to a SiC high thermal conductivity substrate in a flip-chip manner; stripping the InP substrate, and preparing a photoelectric conversion functional area of the detector; and finally, bonding to a diamond high-thermal-conductivity substrate in a flip-chip manner to obtain the photoelectric detector chip. By integrating the SiC and diamond double high-thermal-conductivity substrates and adopting the upper and lower double-channel heat dissipation design, the junction temperature of the device under the high-power working condition is effectively reduced, and the thermal failure threshold value is improved, so that the saturation output power of the photoelectric detector is remarkably improved.

The application discloses a kind of quantum cascade laser light frequency comb based on on-chip dispersion regulation and preparation method thereof, comprising: sequentially growing lower waveguide layer, passive waveguide layer, low-doped waveguide layer, high-doped waveguide layer, lower limiting layer, active region, upper limiting layer, upper waveguide layer, ohmic contact layer on substrate;SiO2 layer is grown on the surface of ohmic contact layer, and double-groove strip-shaped ridge structure is formed on the surface, and the etching depth reaches the lower waveguide layer;Fill half-insulating InP:Fe in double groove, remove residual SiO2 layer;Insulating layer is grown on the surface of ohmic contact layer;Surface of insulating layer is prepared front metal electrode window;Insulating layer surface and inside front metal electrode window, front metal electrode layer is grown;Thicken front metal electrode layer;Substrate is thinned and polished, back metal electrode layer is grown, annealing treatment, packaging, and quantum cascade laser light frequency comb is obtained.The dispersion problem of mid-infrared quantum cascade laser is solved, the yield is high, the cost is low, the process is simple, and the manufacturing demand of large-scale application is met.

The invention discloses a metal-oxide-semiconductor field effect transistor (MOSFET) device and a preparation method thereof. The MOSFET device comprises a substrate which comprises a substrate and an epitaxial layer which are stacked; the doped region is located in the epitaxial layer, the doped region comprises a first doped region and a second doped region which are spaced in the direction parallel to the surface of the substrate, and the first doped region and the second doped region are regions formed by performing ion implantation on one side surface of a part of the epitaxial layer; the semi-insulating region is located in the epitaxial layer, and the two sides of the semi-insulating region are in contact with the first doped region and the second doped region respectively; the transparent insulating layer is located on the surface of the substrate, and the transparent insulating layer is in contact with the semi-insulating region; the light-emitting layer is located over the transparent insulating layer, and the light-emitting layer makes contact with the transparent insulating layer. According to the technical scheme, the problems that in the prior art, the switching speed of a traditional MOSFET device is limited, reliability is low, and the device is prone to failure due to an electric field can be effectively solved.

The invention discloses a composite barrier epitaxial material structure of an indium phosphide high-mobility transistor and a buried gate control method of the composite barrier epitaxial material structure. The device sequentially comprises a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doping layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP corrosion self-stop layer and a cap layer from bottom to top. The buried gate control method comprises the following steps: firstly, preparing a 4-inch InP wafer, and simultaneously completing isolation and source-drain ohmic contact pre-process; an InP HEMT grid electrode is prepared; performing buried gate process heat treatment; other front and back processes are completed, and independent chips are formed through cutting-up. According to the invention, an InP-InAlAs-InGaP composite barrier structure is provided in an epitaxial structure, stable diffusion Schottky contact is formed by adopting a buried gate process, and an InGaP buried gate stop layer is added, so that the buried gate depth is controllable. The InP HEMT device has the characteristics of low noise, low power consumption, high breakdown voltage and the like, and can meet the use requirements of an InP HEMT low-noise amplifier in application scenes of quantum bit reading, radio astronomy, remote sensing imaging and the like.

The application relates to the technical field of silicon carbide single crystal growth, in particular to high-purity semi-insulating silicon carbide single crystal for optical elements and a growth process thereof, which comprises the following steps: S1, assembling silicon carbide powder, a graphite crucible and the like to form a thermal field device, and placing the thermal field device in an induction furnace, sequentially performing room temperature furnace washing treatment, low-temperature furnace washing treatment, and then performing thermal field impurity removal treatment; S2, assembling a silicon carbide seed crystal and the thermal field device after impurity removal, then increasing the temperature in the induction furnace and conveying high-purity argon or a mixed gas of high-purity argon and high-purity hydrogen into the induction furnace to perform crystal growth; and S3, after the crystal growth is completed, performing high-temperature and high-pressure annealing treatment, and then performing furnace cooling treatment to obtain a high-purity semi-insulating silicon carbide crystal ingot for optical elements. Through selection of specific raw materials, reasonable design of an assembly mode and combination of thermal field impurity removal, high-temperature and high-pressure annealing and the like, a silicon carbide crystal ingot with excellent light transmission performance and high resistivity is obtained.

A tunable and reconfigurable transparent electrode for a light valve includes a semi-insulating material substrate having an electrically insulating dark region and a shallow electrically conductive region. The light valve further has a transparent and conductive contact supported by the semi-insulating material substrate, wherein charged carriers are generated optically in response to incident light passing through the transparent and conductive contact and into the semi-insulating material substrate.

The invention belongs to the technical field of semiconductor material characterization, and relates to an antimonide material carrier concentration detection method. The method comprises the following steps: growing a first antimony-containing compound material layer on a conductive gallium antimonide substrate; performing an electrochemical capacitance-voltage test on the first antimony-containing compound material layer to obtain a first carrier concentration value; growing a second antimony-containing compound material layer on the semi-insulating gallium arsenide substrate; performing a Hall effect test on the second antimony-containing compound material layer to obtain a second carrier concentration value; obtaining a carrier concentration correction factor based on the ratio of the second carrier concentration value to the first carrier concentration value; growing an antimony-containing compound material layer on one side, far away from the substrate, of the first antimony-containing compound material layer and / or the second antimony-containing compound material layer, and performing electrochemical capacitance-voltage test on each antimony-containing compound material layer to obtain a corresponding carrier concentration value; and obtaining the carrier concentration of each antimony-containing compound material layer based on the carrier concentration value and the carrier concentration correction factor.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The invention relates to the technical field of monolithic photoelectric integration, and discloses a monolithic photoelectric integrated chip structure and a manufacturing method thereof.The monolithic photoelectric integrated chip structure structurally comprises a semi-insulating gallium arsenide substrate, and a quantum well light-emitting diode area is arranged on the semi-insulating gallium arsenide substrate; an N-type heavily-doped gallium arsenide electrode layer, a multi-quantum well structure and a P-type heavily-doped gallium arsenide electrode layer are sequentially arranged in the quantum well light-emitting diode region from bottom to top; the multi-quantum well structure comprises an N-type AlGaAs lower cladding layer, a GaAs / AlGaAs multi-quantum well active layer and a P-type AlGaAs upper cladding layer which are sequentially arranged from bottom to top; a germanium photoelectric detector area is reserved on the semi-insulating gallium arsenide substrate, and a P-type germanium electrode layer and an intrinsic germanium absorption layer are arranged on the germanium photoelectric detector area in a selective epitaxy mode. The invention has the effects of improving the transmission rate and the integration level of the device and reducing the complexity and the cost of the system.

A mid-infrared laser based on on-chip integration of three devices and its fabrication method is disclosed, involving the intersection of semiconductor laser technology and optical communication technology. This invention alleviates the problem of the existing quantum cascaded laser (QCL) technology being unable to simultaneously achieve high modulation rate and high power. The mid-infrared laser includes a QCL unit, an EAM unit, and an SOA unit sequentially disposed on a substrate; the substrate comprises semi-insulating InP; the QCL unit, EAM unit, and SOA unit share the same ridge waveguide structure and are grown through epitaxial docking. The method described in this invention is applicable to mid-infrared band space communication scenarios with high requirements for laser modulation rate, output power, and single-mode stability.

The application provides a gallium arsenide-based terahertz frequency-doubling Schottky diode and a preparation method thereof. The preparation method comprises the following steps: growing a gallium arsenide polycrystalline thin film layer on a diamond substrate, wherein the gallium arsenide polycrystalline thin film layer is semi-insulating gallium arsenide; and preparing a device layer of the Schottky diode on the gallium arsenide polycrystalline thin film layer. According to the application, the gallium arsenide polycrystalline thin film layer is directly grown on the diamond substrate, and the Schottky diode is prepared on the basis, the diamond substrate replaces the gallium arsenide substrate to serve as the structural support of the Schottky diode, the process flow is simple, the production cycle is short, the reliability is high, and the heat dissipation performance of the gallium arsenide-based terahertz frequency-doubling Schottky diode is improved.

Epitaxial substrate (10) for semiconductor elements (20), containing: a semi-insulating, freestanding substrate (1) formed from Zn-doped GaN, whose dislocation density is less than or equal to 5.0 × 10 7 cm -2 is, a buffer layer (2) adjacent to the freestanding substrate (1); a channel layer (3) adjacent to the buffer layer (2); and a barrier layer (4) provided on the opposite side of the buffer layer (2) with an intervening channel layer (3), wherein the buffer layer (2) made of Al p Ga 1-p N (0.7 ≤ p ≤ 1) is a diffusion-suppressing layer of a thickness of 1 nm to 100 nm and suppresses diffusion of Zn from the freestanding substrate (1) into the channel layer (3) and a concentration of Zn in the channel layer (3) less than or equal to 1×10 16 cm -3 is.

Power semiconductor device comprising a cell region (1) and a terminal region (2) surrounding the cell region (1) in a top view: a semiconductor base (11) having a first principal surface (S1); a first insulating layer (5) which is formed on the first main surface (S1) in an inner circumferential end part region of the connection area (2); a second insulating layer (15) which is formed on the first main surface (S1) in an outer circumferential end part region of the connection area (2); a first electrode (10) formed on the first main surface (S1) and the first insulating layer (5) in the cell area (1); a second electrode (9) formed on the first main surface (S1) and the second insulating layer (15) in the outer circumferential end region of the connection area (2); and a semi-insulating layer (8) that has contact with the first electrode (10), the second electrode (9), the first insulating layer (5) and the second insulating layer (15) and has contact with the first main surface (S1) between the first insulating layer (5) and the second insulating layer (15), wherein the semiconductor base layer (11) has: a semiconductor substrate (3) of a first conductivity type; and one or more separate first diffusion layers (4) of a second conductivity type, which are formed on a surface layer on one side of the first main surface (S1) of the semiconductor substrate (3) in the connection area (2), the semiconductor base (11) further comprises at least one third insulating layer (25) formed on the first main surface (S1) of the semiconductor base (11) between the first insulating layer (5) and the second insulating layer (15), the semi-insulating layer (8) has contact with the third insulating layer (25) on the third insulating layer (25) and has contact with the first main surface (S1) in at least two areas where the third insulating layer (25) is not formed between the first insulating layer (5) and the second insulating layer (15), and a ratio of a contact area between the semi-insulating layer (8) and the first main surface (S1) of the semiconductor base (11) in the terminal area (2) to a distance from an inner circumferential end region of one of the one or more first diffusion layers (4) located in an innermost circumference of the terminal area (2) to an inner circumferential end region of the second electrode (9) is equal to or greater than 15% and equal to or less than 50%.