28 results about "Arsenide" patented technology

The invention provides a feeding control method and device for an arsenic hydride reaction kettle, equipment and a storage medium, and belongs to the technical field of arsenic hydride reaction, and the method comprises the following steps: determining an initial feeding mode of raw materials at the initial reaction stage based on the volume of the reaction kettle and an expected reaction molar ratio; the raw materials comprise zinc arsenide and dilute sulphuric acid; the desired reaction molar ratio is the desired molar ratio between zinc arsenide and dilute sulphuric acid; in response to the situation that the pressure change rate in the reaction kettle is smaller than a preset change rate value, the initial feeding mode is switched into a constant-speed feeding mode of raw materials in the middle stage of reaction; in response to the condition that the generation rate of the arsenic hydride is lower than a preset generation rate value, switching the constant-speed feeding mode into a final feeding mode of raw materials at the end of the reaction; according to the arsenic hydride reaction kettle feeding control method and device, the equipment and the storage medium provided by the invention, the feeding opportunity and the feeding speed of the reaction kettle can be accurately grasped.

The invention belongs to the technical field of hydrometallurgy, and particularly relates to a pretreatment method for enhancing peroxide to improve the leaching rate of high-sulfur-arsenic gold ore. Comprising the following steps that the high-sulfur-arsenic gold ore is ground and then prepared into ore pulp; an oxidizing agent is added into the ore pulp, oxidation pretreatment is conducted on the high-sulfur-arsenic gold ore under the catalytic action of ultraviolet light, and ore pulp activation liquid is formed; and the pH of the ore pulp activating solution is adjusted to 9-12, a gold leaching agent is added into the ore pulp complexing solution, and stirring gold leaching treatment is conducted. According to the method, efficient oxidation of sulfide and arsenide is achieved under the mild condition through the synergistic effect of photocatalysis and chemical oxidation, the leaching rate of gold is remarkably increased, compared with a conventional peroxide oxidation method for pretreatment, the leaching rate can be increased by 10%-35%, and meanwhile the agent use amount and environmental pollution are reduced.

A light-emitting diode (LED) epitaxial structure, an LED device, and a manufacturing method of an LED epitaxial structure are provided. The LED epitaxial structure 100 includes an n-type confinement layer 20, an n-type waveguide layer 30, a light-emitting layer 40, a p-type waveguide layer 50, and a p-type confinement layer 60 that are sequentially stacked. The p-type waveguide layer 50 includes a first p-type waveguide sub-layer 51, an electron blocking layer 52, and a second p-type waveguide sub-layer 53 that are sequentially stacked, where the first p-type waveguide sub-layer 51 is disposed closer to the light-emitting layer 40 than the second p-type waveguide sub-layer 53, and the electron blocking layer 52 includes at least one oxide layer of aluminumygallium1-yarsenide (AlyGa1-yAs) 521.

The present invention provides a method for preparing a photoelectric device. In the process of preparing a photoelectric device epitaxial wafer using the preparation method, a phosphide protective layer and an arsenide capping layer lattice-matched with the ohmic contact layer are provided on the side of the ohmic contact layer facing away from the substrate. This method can effectively prevent reactant deposition particles on quartz parts and graphite parts in the epitaxial wafer cavity from falling onto the ohmic contact layer after the epitaxial wafer growth is completed. After the epitaxial wafer growth is completed, the phosphide protective layer and the arsenide capping layer are removed to obtain an ohmic contact layer with good film quality, thereby enabling the ohmic contact layer to form better ohmic contact, thereby further improving the performance of the photoelectric device and the yield of the chip.

The utility model relates to the field of denitration catalyst performance evaluation, in particular to a denitration catalyst arsenic poisoning resistance evaluation device which comprises a mixing preheater, an As2O3 steam reactor, a catalyst reactor, a flue gas analyzer and a collector, and the mixing preheater and the As2O3 steam reactor are both communicated with the front end of the catalyst reactor; the flue gas analyzer and the collector are both communicated with the tail end of the catalyst reactor. The device has high controllability, can accurately adjust and stably maintain key parameters such as arsenide concentration, temperature, humidity and the like, and can simulate complex gas components and dynamic change conditions in actual flue gas. Therefore, a more real and reliable experimental environment is provided for arsenic poisoning resistance evaluation of the catalyst, the research and development process of the efficient arsenic poisoning resistance catalyst is accelerated, and continuous progress, application and popularization of the SCR technology are promoted.

A gallium arsenide single-crystal substrate has a main surface with a circular shape and features R1, R2, R3, R4, R5, and R6, each of which is a first integrated intensity ratio. The first integrated intensity ratio is obtained by determining a spectrum of the detection intensity of a 3d electron of arsenic with respect to a binding energy of a photoelectron emitted outwards from the gallium arsenide single-crystal substrate based on X-ray photoelectron spectroscopy, in which X-rays are applied centrally to the main surface under specific conditions. The first integrated intensity ratio is a ratio of an integrated intensity of an arsenic element present as diarsene pentoxide to the sum of the integrated intensity of the arsenic element present as diarsene pentoxide and the integrated intensity of an arsenic element present as arsenic trioxide.an integrated intensity of an arsenic element present as gallium arsenide and an integrated intensity of an arsenic element present as metallarsene, and wherein R2 and / or R3 and / or R4 is the largest among R1, R2, R3, R4, R5 and R6.

The invention provides a method for determining a trace As component in InGaAsP, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: aiming at a plurality of different y values, growing a corresponding InGaAsyP1-y epitaxial layer on a substrate to obtain a plurality of epitaxial samples; a preset corrosion solution is adopted, the corrosion rate corresponding to each y is obtained, data fitting is carried out, and the corresponding relation between the corrosion rate and the y is obtained; for an InGaAsy0P1-y0 epitaxial layer sample with the thickness smaller than 40 nm and the component y0 smaller than 0.02 on the arsenide epitaxial layer, the corrosion rate is determined, and the component y0 is determined according to the corresponding relation. According to the method, the corresponding relation between the corrosion rate and the As component is established, the component y0 of the thin layer InGaAsy0P1-y0 epitaxial layer can be determined according to the corresponding relation only by measuring the corrosion rate of the thin layer InGaAsy0P1-y0 epitaxial layer, and quantitative testing of the trace As component in the thin layer epitaxial layer is achieved.

The invention provides a solar cell and a manufacturing method thereof. The solar cell comprises a substrate; the epitaxial structure is arranged on the surface of one side of the substrate; the ohmic contact layer is arranged on the surface, deviating from the substrate, of the epitaxial structure; the grid line electrode is in contact with the ohmic contact layer; the back electrode is arranged on the surface of one side, deviating from the epitaxial structure, of the substrate; wherein the ohmic contact layer comprises a composite stacked structure formed by a phosphide layer and an arsenide layer. Through the arrangement, the conduction band bottom of the phosphide layer is higher than the arsenide layer, and an electron barrier (delta Ec) is formed at the interface of the phosphide layer and the arsenide layer; heavy doping is carried out on the ohmic contact layer, so that a Schottky barrier between the grid line electrode and the phosphide layer and a heterojunction barrier (delta Ec) between the phosphide layer and the arsenide layer become thin barriers capable of being tunneled by electrons due to narrowing of a depletion region, and overall low-resistance ohmic contact is achieved.

This application belongs to the field of saturable absorber technology, and particularly relates to a saturable absorber based on tantalum arsenide quantum dots, its preparation method, and a mode-locked fiber laser. The saturable absorber provided by this application includes a tapered optical fiber and tantalum arsenide quantum dots loaded thereon. The tantalum arsenide quantum dots have excellent nonlinear optical properties and saturation intensity, so when the laser passes through the tantalum arsenide quantum dots on the saturable absorber, the laser reaches saturation quickly, enabling the output of ultrafast laser with a repetition frequency and stable laser mode-locked signal, thereby solving the technical problem of low performance of saturable absorbers based on two-dimensional materials in the prior art.

A process for producing semiconductor structures comprising one of more layers of Group III / IV Compounds deposited onto a template using PVD sputtering the resulting semiconductor structures is provided according to the invention. The Group III or Group IV material may be gallium, hafnium, indium, aluminum, silicon, germanium, magnesium and / or zirconium. The anion provided by a reactive gas may be nitride, oxide, arsenide, or phosphide. The flow of the reactive gas to the vacuum chamber used to react with the sputtered Group III or Group IV target material for produce the Group III / IV Compound layer onto the template is modulated during a duty cycle during the PVD sputtering process between a target-rich condition and a reactive gas-rich condition to enhance the efficiency of the PVD sputtering process and improve the crystallinity of the Group III / IV Compound layer within the resulting semiconductor structure.

According to the present invention there is provided use of a lead electrode in a method for removing one or more impurities from a copper refinery electrolyte. Preferably, the method is a single-stage electrolyte purification / liberation (EPP) method. More preferably, the one or more impurities comprise arsenic. Also provided is a lead cathode, per se, for use in such a method. Preferably, the method comprises the steps of: providing an electrolyte having a concentration of arsenic that is sufficiently elevated as to affect the purity of the final copper cathode product; providing a cell adapted for performing a single- stage electrolyte purification / liberation (EPP) method; providing to the EPP cell a cathode comprised of about 90 to about 100 wt.% lead; performing the EPP method for a predetermined period, thereby to effect a copper / arsenic reduction step; and obtaining the resultant cupric arsenide deposit in a sludge layer at the bottom of the EPP cell.

The invention provides a semiconductor structure and an image sensor. The semiconductor structure comprises a substrate, a photodiode and a color filter element, the photodiode comprises a first photoelectric function layer, a second photoelectric function layer and a third photoelectric function layer which are sequentially stacked on the surface of a pixel area, and fourth photoelectric function layers formed on the two sides of the first photoelectric function layer. The first photoelectric functional layer is made of silicon arsenide, the second photoelectric functional layer and the fourth photoelectric functional layer are made of silicon phosphide, and the third photoelectric functional layer is made of silicon antimonide; the second photoelectric functional layer is located on the surface of one side of the first photoelectric functional layer away from the substrate; the bottom surface and the side surface, close to one side of the first photoelectric function layer, of the third photoelectric function layer are in contact with the second photoelectric function layer and are surrounded by the second photoelectric function layer. According to the semiconductor structure, a potential energy well and an efficient electron transport channel can be formed in the photodiode, so that more photoelectrons are generated, and the photoelectric conversion efficiency is improved.

The invention belongs to the technical field of mineral processing engineering, and particularly relates to a composite binder for iron oxide ore pellets and a pellet preparation and arsenic removal method thereof. Calcium carbonate-ammonium bicarbonate serves as a composite binder, efficient arsenic removal is achieved through the unique action mechanism of ammonium bicarbonate, iron oxide ore powder and a composite binder solution are mixed and pelletized to obtain green pellets, the green pellets are cured for 5-8 h at the temperature of 20-30 DEG C and the humidity of 60-80%, dried for 3-4 h at the temperature of 100 + / -5 DEG C and roasted for 2-4 h at the temperature of 600-800 DEG C; ammonium bicarbonate is decomposed during roasting to generate NHH, the NHH reacts with arsenide in the pellets to generate volatile arsenic ammonia compounds, arsenic removal is completed along with gas escape, and meanwhile calcium carbonate provides framework support for the pellets to guarantee strength. The arsenic removal rate reaches 85% or above, the arsenic content of the pellets is reduced to 0.02% or below, the compressive strength of dry pellets is larger than or equal to 2000 N / pellet, the roasting temperature is reduced by 30% or above compared with a traditional technology, low-energy-consumption and high-purity clean utilization of iron oxide ore resources is achieved, the technological process is short, and the method is suitable for industrial application.

The invention discloses a process method for deeply removing copper from crude lead by using dangerous solid wastes, and belongs to the technical field of non-ferrous metal metallurgy and resource utilization of the dangerous solid wastes. Dangerous solid waste containing arsenic and sulfur serves as a copper removal agent and is added into molten lead bullion, stirring and smelting are conducted at the temperature of 450-900 DEG C, copper reacts with arsenic and sulfur to generate cuprous sulfide, copper arsenide and other compounds insoluble in lead liquid by means of the preferential affinity of arsenic and sulfur to copper, the compounds float upwards to form a low-density arsenic matte scum layer, and efficient separation of copper is achieved through mechanical slag scattering. The copper content in the lead liquid after copper removal can be reduced to 0.1% or below, and meanwhile harmless treatment of dangerous solid waste and resource recycling of valuable elements are achieved. The method is simple in process, low in cost and high in copper removal efficiency, and has remarkable environmental benefits and economic benefits.

The invention relates to a method for deeply removing arsenic from high-purity antimony, and belongs to the technical field of metallurgical engineering. According to the method, tin serves as a trapping agent under the vacuum condition, tin and arsenic preferentially form a stable tin arsenide compound, and high-selectivity separation of antimony and arsenic is achieved; the method specifically comprises the following steps: (1) preparing and mixing raw materials; (2) vacuum distillation reaction: placing the high-temperature-resistant container in a vacuum furnace, and starting a vacuum system to reduce the pressure in the furnace to 10 Pa or below; heating the furnace to a reaction temperature of 580-630 DEG C at a heating rate of 8-15 DEG C / min, and keeping the temperature for 30-120 minutes at the temperature; and (3) separating the product to obtain an antimony product subjected to deep arsenic removal. According to the method, traditional physical separation (vacuum distillation) and chemical reaction (alloying) are successfully combined, and the dynamic bottleneck existing in a single physical method is overcome. By forming volatile tin arsenide, the migration path and the existence form of arsenic are ingeniously changed, so that high-selectivity and high-efficiency removal of low-content arsenic is realized.

Semiconductor chip (100) with a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material, wherein the semiconductor layer sequence (10) includes a p-type semiconductor region (4) and an n-type semiconductor region (2), and an active layer (3) arranged between the p-type semiconductor region (4) and the n-type semiconductor region (2), wherein - the n-type semiconductor region (2) comprises a superlattice structure (20) to improve current expansion, wherein the superlattice structure (20) has a periodic arrangement of semiconductor layers (21, 22, 23, 24), - a period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and one doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E1 of the undoped first semiconductor layer (21), and - the undoped first semiconductor layer (21) in the superlattice structure (20) is arranged between an undoped first intermediate layer (23) and an undoped second intermediate layer (24), and - the doped second semiconductor layer (22) is between 10 nm and 200 nm thick.

The invention relates to an LED comprising a semiconductor layer stack having a first layer of a first doping type, a second layer of a second doping type, and an active region arranged between the first layer and the second layer. The semiconductor layer stack includes a bottom surface and a top surface and mesa structured side surfaces connecting the top surface and the bottom surface, and includes a central region having a lateral dimension less than half a lateral dimension of the semiconductor layer stack. Further, the semiconductor layer stack includes a material including at least one of phosphide and arsenide, and a current path from the first layer through the active region to the second layer is limited to the central region.

The invention relates to a micro-LED comprising a semiconductor layer stack with a first layer of a first doping type, a second layer of a second doping type, and an active region arranged between the first and second layers. The semiconductor layer stack comprises a bottom and a top surface, as well as mesa-structured side surfaces connecting the top and bottom surfaces, and a central region with a lateral dimension that is less than half a lateral dimension of the semiconductor layer stack. Furthermore, the semiconductor layer stack comprises a material comprising at least one phosphide and one arsenide, and a current path from the first layer to the second layer through the active region is confined to the central region.

The invention discloses a magnesium gallate avalanche detector and a preparation method thereof. The magnesium gallate avalanche detector comprises an Nb: STO layer, an MgO: Al layer and an MgGa2O4 layer which are sequentially arranged from bottom to top, wherein the Nb: STO layer and the MgGa2O4 layer are respectively led out through a first electrode and a second electrode. After Al is doped with MgO, lattice distortion can be formed, the electron-phonon interaction is enhanced, photon absorption by phonon vibration is promoted, and the MgO: Al optical band gap is increased; secondly, Al doping can change the Fermi level position on the surface of MgO, so that the bottom energy of a conduction band on the surface of MgO is increased, and the band gap of MgO: Al is indirectly increased; for an avalanche detector, the dark current of the device can be reduced.

The invention discloses a biological oxidation-suspension oxidation roasting pretreatment-supercritical CO2 leaching method for refractory gold ore, and belongs to the technical field of mineral processing and metallurgy. According to the method, sulfide and arsenide in the gold ore are oxidized by adopting microbial flora in an acid environment, then the ore subjected to biological oxidation is subjected to suspension oxidizing roasting at high temperature, and supercritical CO2 and sodium cyanide are used for combined leaching, so that the solubility and the leaching rate of gold are improved, the recovery rate of gold is remarkably improved, and the method is suitable for industrial production. Meanwhile, environmental pollution caused by a traditional cyanide method is reduced. Through the combined process of biological oxidation, suspension oxidation roasting and supercritical CO2 leaching, the recovery rate of gold is greatly increased, the use of cyanide and the emission of harmful waste are reduced, the environmental protection requirement of the green mining industry is met, meanwhile, the resource utilization is optimized through the integrated technological process, the overall production cost is reduced, and the method is suitable for industrial production. And energy and consumption of chemical reagents are saved, and the method is particularly suitable for refractory gold ores.

A nanopore sensing system includes a cis well, a trans well, and a metal based membrane positioned between the cis and trans wells so that a channel defined in the metal based membrane fluidically connects the cis and trans wells. The metal based membrane has a thickness ranging from about 1 nm to about 3 nm and is selected from the group consisting of a metal oxide, a metal sulfide, a metal nitride, a metal phosphide, a metal arsenide, a metal antimonide, a metal selenide, and a metal telluride.

The invention discloses a low-cost reverse matching two-junction GaInP / GaAs solar cell and a preparation method thereof, the outer edge structure of the solar cell comprises a gallium arsenide substrate, and three GaAs buffer layers, three GaInP barrier layers, three GaAs cap layers, three AlGaInP top cells, a first tunneling junction, three GaAs bottom cells and three AlGaAs cap layers which are arranged on the gallium arsenide substrate, the three GaAs buffer layers, the three GaInP barrier layers, the three GaAs cap layers, the three AlGaInP top cells, the three GaAs bottom cells and the three AlGaAs cap layers are all middle layers, and the growth rate of the middle layers is larger than that of the upper layers and the lower layers of the three GaAs buffer layers, the three GaInP barrier layers, the three GaAs cap layers, the three AlGaInP top cells and the three GaAs bottom cells. The growth mode of the epitaxial structure adopts a slow-fast-slow gradual-change growth mode with different rates, so that a buffer material has a lower reverse domain, layered growth of an arsenic or phosphorus compound material is realized, interface defects of an arsenide material and a phosphide material at an interface or a steep interface can be overcome, efficient growth of an epitaxial material is met, and the performance of the epitaxial structure is improved. The epitaxial growth time is reduced, and the growth time cost is reduced.

A method of extracting a metal of interest comprises dissolving an oxidizable metal compound in an electrolyte contained in an electrochemical cell; dissolving a sulfoarsenide compound comprising the metal of interest in the electrolyte; applying a current between an anode and a cathode of the electrochemical cell to produce an electrochemical product solution comprising soluble metal ions of the oxidizable metal compound, soluble metal ions of the metal of interest, and a soluble arsenic acid; reacting the soluble arsenic acid with the metal ions of the oxidizable metal compound to form an insoluble arsenate compound comprising the metal of the oxidizable metal compound; and separating the soluble metal ions of the metal of interest from the insoluble arsenate compound. Also disclosed is a method of extracting a metal of interest from a metal containing feed stream, and a method of isolating cobalt from a metal containing feed stream.

The invention relates to a method for producing an optoelectronic semiconductor chip (100), comprising the following steps: epitaxially growing a semiconductor layer sequence (1) having an active layer (2) for emitting electromagnetic radiation, the active layer (2) comprising a phosphide compound semiconductor material or an arsenide compound semiconductor material; a through-hole (3) for electrically contacting the semiconductor layer sequence (1) is formed in the semiconductor layer sequence (1), and an electron and hole barrier (4) is formed in the semiconductor layer sequence (1) at an edge (31) of the through-hole (3). Furthermore, an optoelectronic semiconductor chip is specified herein.

The application belongs to the technical field of semiconductor process, and discloses a three-waveband image sensor and a manufacturing method thereof. The image sensor comprises a substrate layer, a silicon oxide layer, an aluminum oxide layer, a first electrode layer, an ultraviolet light sensing layer, a visible light sensing layer, an infrared light sensing layer, a second electrode layer and a passivation layer which are sequentially stacked. A plurality of rectangular grooves with the same shape and distributed at a preset interval penetrate the second electrode layer, the infrared light sensing layer, the visible light sensing layer and the ultraviolet light sensing layer in sequence. The ultraviolet light sensing layer adopts intrinsic aluminum arsenide material. The visible light sensing layer adopts intrinsic gallium arsenide material. The infrared light sensing layer adopts intrinsic germanium material with a 6-degree bevel. The passivation layer uniformly covers the inner walls of the second electrode layer and each rectangular groove. The application can solve the problems of lattice mismatch and polarity mismatch between the three sensing layers in the prior art, reduce manufacturing cost and be suitable for mass production.

The utility model relates to a device for preparing high-purity arsenic, which comprises an electrode reaction tank, the electrode reaction tank comprises an anode plate, a cathode plate and a power supply, the anode plate and the cathode plate are arranged in the electrode reaction tank, the power supply is electrically connected with the anode plate and the cathode plate, and an oxygen outlet and an arsenious acid inlet are sequentially arranged on the side wall of the electrode reaction tank close to the anode plate from top to bottom. An arsenic hydride discharge port is formed in the upper part of the side wall, close to the cathode plate, of the electrode reaction tank; the arsenic hydride discharge port is connected with a tubular heater, an outlet of the tubular heater is connected with a condensation collecting tank, and an outlet of the condensation collecting tank is connected with a hydrogen peroxide washer. According to the device, the electrode reaction tank, the tubular heater and the condensation collection tank are connected to form the high-purity arsenic preparation device adopting the electrode and thermal decomposition method, and the device can be used for preparing high-purity arsenic, can be used for efficiently recovering arsenic elements in arsenide waste residues generated in the metallurgical process, and fully realizes resource recycling.

The invention provides an angle regulation and control all-optical switch based on a Goos-Hansen displacement polarity jump effect, and relates to the technical field of optoelectronic devices. A photonic crystal adopts a high-refractive-index dielectric layer titanium dioxide (TiO2) and a low-refractive-index dielectric layer p-phenyleneacetylene which are alternately arranged as dielectric sheets, semimetal tantalum arsenide is used as a defect layer, and the angle regulation and control all-optical switch based on the Goos-Hansen displacement polarity jump effect is obtained. A PT symmetric periodic photonic crystal PCN with the structural formula of (AB) N (A 'B') N is formed, and rapid positive and negative value conversion of GH displacement, significant amplitude enhancement and dynamic regulation and control of a control angle are realized by adjusting an incident angle. The core of the invention is that Weyl semimetal is used as a defect layer of the PT symmetric photonic crystal, and the performance limitation of a traditional all-optical switch is broken through by using the synergistic effect of the Weyl semimetal and the PT symmetric photonic crystal.

The objective is to provide a field-effect transistor that can shorten the gate length without forming spike grooves. [Solution] The device comprises an active layer 2 containing GaAs formed on a semi-insulating substrate 1, a recess 8 formed in the active layer 2 between a source electrode 3 and a drain electrode 4, an insulating film 5a formed in the active layer 2 extending toward the recess 8, an insulating film 5b formed in the active layer 2 extending to the upper part of the recess 8 on the electrode 4 side, and a gate electrode 14 having a recessed portion 13 of platinum arsenide layer that sinks from the recess bottom surface 20 toward the substrate 1 side. The gate electrode 14 comprises a sequentially formed titanium layer 9, platinum layer 10, and gold layer 12. The titanium layer 9 is formed on the recess bottom surface 20 and the insulating film 5b. The platinum layer 10 is formed on the opposite surfaces 45a, 45b and the side surfaces 46a, 46b on the electrode 3 side of the titanium layer 9. The recessed portion 13 is connected to the platinum layer 10.