196 results about "Arsenide" patented technology

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm². The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

A mineral separation process includes wet-grinding the ore to liberation of minerals, oxidizing the slurry using air, hydrogen peroxide or other oxidants and floating the valuable minerals at a pH between about 9.0 and 10.0 with a xanthate as collector, and a combination of a polyamine and a sulfur containing species as depressants for arsenide minerals. This depressant suite effectively depresses the flotation of arsenide minerals with no effect on the flotation of the valuable minerals.

High quality epitaxial layers of monocrystalline III-V arsenide nitride materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline III-V arsenide nitride material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, an accommodating buffer layer comprising a barium strontium titanium oxide and a monocrystalline III-V arsenide nitride layer, such as GaAsN, having a nitrogen concentration ranging from 1-5% function to further reduce any lattice mismatch between layers.

This invention relates to the arsenide gallium single-crystal growth with level three temperature areas gradient concretion method, the character as follows: the furnace where the single-crystal grows is not moved; the temperature of high temperature T1 decreases gradually according to the single-crystal shaping point temperature, and the decreasing rate inosculates to the single-crystal growth rate.

The invention provides a method for preparing rare earth ion europium-doped sodium gadolinium tetrafluoride (NaGdF4:Eu3+) luminescent nanorods and a method thereof, belonging to the technical field of preparation of rare earth doped luminescent materials. The present invention comprises the following steps: (1) mixing compound rare earth ions and sodium lauryl sulfate in proportion, and then adding fluoride to form a mixed solution; (2) carrying out hydrothermal reaction on the mixed solution at a certain temperature and time, Obtain the NaGdF4:Eu3+luminescent nanorods. The method has a simple synthesis process and is easy to produce in batches, and the prepared NaGdF4:Eu3+ nanorods have good red luminescent properties. The invention uses rare earth metal oxides as raw materials and sodium lauryl sulfate as a surfactant, and the whole reaction is carried out in an aqueous solution without any organic solvent, which is economical and environmentally friendly, has strong practicability, and has wide application prospects.

The invention relates to a surface nano grating-based wavelength tunable vertical cavity surface emitting laser and a preparation method, which belong to the field of semiconductor photoelectronic devices. The laser has an inner cavity contact laminated structure; a positive electrode layer (1) is arranged on a P-type ohmic contact layer (5); an air-gap layer (12), a gallium arsenide layer (2a), and a gallium aluminum arsenide layer (2b) are arranged above the ohmic contact layer (5) in turn; a gallium aluminum arsenide oxidation current limitation layer (6), an active region (7), an n-type gallium aluminum arsenide layer (8a), an n-type gallium arsenide (8b), an n-type gallium arsenide substrate (10), and a substrate electrode layer (11) are formed below the ohmic contact layer (5) in turn; and a nano grating (15) is positioned on the surface of the gallium arsenide layer (2a). The thickness of the air-gas layer can be subjected to mechanical adjustment of an electrostatic force and the like, so that photon phase change can be transmitted in the resonant cavity of a laser and an outputted light beam passes through the nano grating (15) immediately; therefore, a wavelength and polarization can be simultaneously controlled.

A semiconductor laser cascaded by indium phosphide based quantum consists of a N type of indium phosphide substrate , a N type of indium gallium arsenide bottom wave guide layer ,an active region of indium gallium arsenide / indium aluminum arsenide alternitation in 35 cycles , a N type of indium gallium arsenide top wave guide layer , a N type of indium phosphide top clad layer , a N type of indium phosphide contact layer , a N type of indium gallium arsenide ohm contact layer , insulation layer on double channel mesa , a front N type of electrode and a back N type of electrode .

The invention relates to a growth method of gallium arsenide monocrystal or germanium arsenide monocrystal, which belongs to the field of crystal growth. Firstly, PBN is flattened with sand paper No. 1200 till PBN has no obvious steps, then PBN is put in mixed washing liquid of de-ionized water, ammonia and oxyful in the volume ratio of 2:1:1 to be immersed for 30 minutes, and then PBN is cleaned with de-ionized water; PBN is baked for about 30 minutes in a baking furnace at 180 to 220 DEG C in vacuum state, and then is baked for more than 30 minutes in the baking furnace at 900 to 1050 DEG C in vacuum state; 1atm high purity oxygen is filled into PBN, to ensure that PBN is baked for more than 30 minutes in the baking furnace at 900 to 1050 DEG C; after PBN is cooled down to 50 DEG C, clear polycrystalline material is directly loaded, the loading is accomplished within 2 minutes, the loading environment temperature is controlled to be between 20 to 25 DEG C, and the humidity is controlled to be below 40 percent; and after the loading, the crystal growth is accomplished according to traditional VGF process. The growth method of gallium arsenide monocrystal or germanium arsenide monocrystal not only ensures that the content of impurity B in the grown monocrystal is reduced, but also ensures that the quality of a substrate is not affected.

The invention discloses a yellow phosphoric tail gas purification method and a device thereof. Aiming at the characteristics of tail gas containing multi-form impurities such as phosphide, sulphide, arsenide, fluorid and the like, the pretreatment of yellow phosphoric tail gas utilization is effectively carried out. The yellow phosphoric tail gas fuel gas purification device comprises a yellow phosphoric tail gas fuel gas pretreatment device (I) and a yellow phosphoric tail gas fuel gas follow-up purifying device (II). A special dephosphorization desulphurization dearsenization unit triplet catalytic oxidation catalyst is used for absorbing H2S and PH3 and residual AsH3 in a tower. The invention comprises a turbulence little lime washing dust-removal system, a washer lime cream washing, and adesorption fluroid, part arsenide and phosphorus, oxysulphide system. The invention realizes that the yellow phosphoric tail gas with the thermal value as high as 10048-11723KJ/Nm is effectively utilized, solves the key difficult problem that yellow phosphorus manufactures can not effectively use yellow phosphoric tail gas as fuel gas. The purified yellow phosphoric tail gas can meet the fuel gas requirements of a gas fired boiler and a fuel gas electric generating set and can be circularly and comprehensively used by the yellow phosphoric manufactures, thus laying the foundation for the sustainable development of the yellow phosphorus industry.

The invention relates to solid or gel-type nanocomposite material which can be polymerised, containing a) 4.9 95.9 wt. % of a soluble polymer; b) 4-95 wt. % of a partially or totally condensed silane selected from the group of epoxyalkoxysilanes, alkoxysilanes and alkylalkoxysilanes, the silane having an inorganic condensation degree of between 33-100% and an organic conversion degree of between 0-95%; c) 0-60 wt. % of an acrylate; d) 0.1-50 wt. % of surface modified nanometric particles selected from the group of oxides, sulphides, selenides, tellurides, halogenides, carbides, arsenides, antimonides, nitrides, phosphides, carbonates, carboxylates, phosphates, sulphates, silicates, titanates, zirconates, aluminates, stannates, plumbates and a mixed oxides; e) 0-50 wt.-% of a plasticiser, f) 0-5 wt. % of a thermal or photochemical cross-linking initiator, sensitizer, auxiliary wetting agent, adhesive agent, antioxidant, stabiliser, colouring agent, photochrome material and thermochrome material in relation to the total weight (dry weight) of the nanocomposite material.

The invention relates to a method for preparing a p-type ZnO nano-wire, belonging to the semiconductor doping technical field. The invention relates to a doping technology for the p-type ZnO nano-wire, in particular to a doping technology by adoption of the chemical vapor deposition technology and utilization of arsenide as a p-type dopant of ZnO. The doping technology is characterized in that: the doping technology adopts the arsenide as a doping source of the p-type ZnO and utilizes the chemical vapor deposition technology to prepare the arsenic doped p-type ZnO nano-wire. Under the condition that the heating temperature is between 400 and 700 DEG C, the proportion of arsenic doped into the ZnO is controlled by adjusting the mol ratio of the arsenide and zinc, so as to perform growth of the p-type ZnO. The doping technology has the advantages that: the doping technology provides a simple and effective growth technology for preparing the p-tyype ZnO nano-wire with high quality and strong controllability, overcomes the defect of difficult doping of the p-type ZnO nano-wire, and further realizes a p-n junction photoelectric device of the ZnO nano-wire.

The invention provides a method for purifying a copper electrolyte by using a chemical reduction method. The method comprises the following steps of adding reducing agents comprising hydrazine hydrate, sulfur dioxide and the like, and a compound which contains Cl-irons, Br-irons and I-irons and is used as additives in the copper electrolyte, filtering after the reduction reaction, or evaporating and crystallizing copper sulfate and filtering to obtain the purified electrolyte, and adding the purified electrolyte in an electrolytic bath to return to an electrolyzing system. Adopting the chemical reduction method to purify the electrolyte, the invention eliminates black copper powder and arsenide hydrogen generated in an electro-deposition method and greatly reduces the energy consumption during purifying the copper electrolyte.

The invention discloses a method for processing low concentration arsenide in water. The water is suitable for processing low concentration arsenide in water, or carrying out deep treatment on high concentration arsenic-containing wastewater. The method organically combines a traditional flocculation coprecipitation technology with a hydroxyl free radical oxidation system, iron ions and hydrogen peroxide form hydroxyl free radicals with extremely strong oxidizability, a Fe-(.OH) reaction system composed of the iron ions and hydroxyl groups can efficiently complete conversion of trivalent arsenic, an iron ion complex generated in the .OH generation process continuously participates in a reaction to generate FeAsO4 with very small solubility, and the arsenide is removed in a precipitate form. The method enhances the adsorption and coacervation effects of fine particles difficult to settle, and the processed arsenide concentration can meet III type water quality requirements in Underground Water Quality Standard (GB/T14848-93).

A hetero-field-effect transistor comprises an InP substrate (21), a channel layer (23) formed on a buffer layer (22) on the InP substrate, a spacer layer (25a) made of a semiconductor having a bandgap larger than that of the channel layer and having a heterojunction with the channel layer, and a carrier supply layer (26) adjacent to the spacer layer. The channel layer includes a predetermined semiconductor layer made of a compound semiconductor the composition of which is expressed by chemical formula GaxIn1-xNyA1-y, where A is As or Sb, the number x is 0<=x<=0.2, the number y is 0.03<=y<=0.10.

The invention relates to a method for manufacturing a lattice graded buffer layer, which comprises the following steps of: (1) using a commercial germanium single crystal, arsenide gallium single crystal or indium phosphide single crystal as a substrate; (2) epitaxially forming a layer of material in lattice matching with the substrate material as a nucleation layer by utilizing epitaxial technology; (3) epitaxially growing a lattice graded layer on the nucleation layer until the lattice of the material of a top layer has an ideal lattice constant or a lattice constant slightly lower than theideal lattice constant, wherein the lattice graded layer consists of a plurality of indium gallium arsenide materials with gradually increased components; (4) epitaxially forming a layer of indium gallium arsenide material with the lattice constant more than the ideal lattice constant on the lattice graded layer as a lattice overshoot layer; and (5) epitaxially forming a layer of material which has the lattice constant equal to the ideal lattice constant and is the same as that grown on an adjacent upper layer thereof as the lattice buffer layer. The method solves the problem of influence of device appearance degradation caused by lattice mismatching between a conventional epitaxial material and the substrate, and can effectively control threading dislocation density on the surface of a device.

The invention provides a method and a system for preparing a silicon-based III-V gallium arsenide semiconductor material. The method comprises the following steps: preparing a silicon dioxide film on a clean single crystal silicon substrate surface; obtaining a silicon dioxide nanometer pattern layer on the silicon dioxide film by adopting the nanometer imprinting technology, wherein the silicon dioxide nanometer pattern layer comprises a growth window area exposed on the single crystal silicon substrate surface and a silicon dioxide pattern area, and the growth window area and the silicon dioxide pattern area are arranged in a staggered manner; depositing a galium arsenide buffer layer on the growth window area, wherein the height of the galium arsenide buffer layer is close to or equal to that of a table surface of the silicon dioxide pattern area; growing the III-V semiconductor material on the galium arsenide buffer layer and the silicon dioxide pattern area in an extension manner. According to the method, the silicon dioxide nanometer pattern layer is prepared by adopting the nanometer imprinting technology to be used as a pattern substrate for growth of the semiconductor material, and the problem of limitation of material sizes is solved, so that the growth and the preparation of industrial materials are facilitated, the material production cost is effectively lowered, and the method has a broad application prospect.

A hetero field effect transistor according to the present invention comprises an InP substrate, a channel layer provided on the InP substrate with a buffer layer disposed between the InP substrate and the channel layer, a spacer layer constituted by a semiconductor having a band gap larger than that of the channel layer formed to hetero-join to the channel layer, and a carrier supply layer formed to be adjacent to the spacer layer, wherein the channel layer comprises a predetermined semiconductor layer constituted by a compound semiconductor represented by a formula Ga_xIn_1−xN_yA_1−y in which A is As or Sb, composition x satisfies 0≦x≦0.2, and composition y satisfies 0.03≦y≦0.10.

This invention relates to a chemical corrosive with high selectivity towards gallium arsenide among gallium arsenide/aluminium arsenide mixture. It uniquely contains citric acid solution and oxydol with a volume ratio of 4:1 and is compatible with gallium arsenide integration technique. Besides, it also has the advantages of nontoxic solution and simple technique.

The invention provides a growth method for controlling the nucleation of self-organization In-Ga-As quantum dots, which is characterized by comprising the following: step 1, choosing a substrate; step 2, depositing a buffer layer on the substrate by adopting a molecular beam epitaxy method or a metal-organic chemical vapor deposition method so as to isolate impurities and dislocation in the substrate and allow a growth surface to be leveler; step 3, depositing a stress buffering-reducing layer on the buffer layer so as to buffer and reduce strain between the buffer layer and In-Ga-As material; and step 4, sequentially depositing a first In-Ga-As layer, ultra-thin aluminum arsenide and a second In-Ga-As layer on the stress buffering-reducing layer, forming an In-Ga-As soakage layer and an In-Ga-As quantum-dot layer and finishing growth preparation.