12 results about "Arsenide" patented technology

A light-emitting diode (LED) epitaxial structure, an LED device, and a manufacturing method of an LED epitaxial structure are provided. The LED epitaxial structure 100 includes an n-type confinement layer 20, an n-type waveguide layer 30, a light-emitting layer 40, a p-type waveguide layer 50, and a p-type confinement layer 60 that are sequentially stacked. The p-type waveguide layer 50 includes a first p-type waveguide sub-layer 51, an electron blocking layer 52, and a second p-type waveguide sub-layer 53 that are sequentially stacked, where the first p-type waveguide sub-layer 51 is disposed closer to the light-emitting layer 40 than the second p-type waveguide sub-layer 53, and the electron blocking layer 52 includes at least one oxide layer of aluminumygallium1-yarsenide (AlyGa1-yAs) 521.

The utility model relates to the field of denitration catalyst performance evaluation, in particular to a denitration catalyst arsenic poisoning resistance evaluation device which comprises a mixing preheater, an As2O3 steam reactor, a catalyst reactor, a flue gas analyzer and a collector, and the mixing preheater and the As2O3 steam reactor are both communicated with the front end of the catalyst reactor; the flue gas analyzer and the collector are both communicated with the tail end of the catalyst reactor. The device has high controllability, can accurately adjust and stably maintain key parameters such as arsenide concentration, temperature, humidity and the like, and can simulate complex gas components and dynamic change conditions in actual flue gas. Therefore, a more real and reliable experimental environment is provided for arsenic poisoning resistance evaluation of the catalyst, the research and development process of the efficient arsenic poisoning resistance catalyst is accelerated, and continuous progress, application and popularization of the SCR technology are promoted.

A gallium arsenide single-crystal substrate has a main surface with a circular shape and features R1, R2, R3, R4, R5, and R6, each of which is a first integrated intensity ratio. The first integrated intensity ratio is obtained by determining a spectrum of the detection intensity of a 3d electron of arsenic with respect to a binding energy of a photoelectron emitted outwards from the gallium arsenide single-crystal substrate based on X-ray photoelectron spectroscopy, in which X-rays are applied centrally to the main surface under specific conditions. The first integrated intensity ratio is a ratio of an integrated intensity of an arsenic element present as diarsene pentoxide to the sum of the integrated intensity of the arsenic element present as diarsene pentoxide and the integrated intensity of an arsenic element present as arsenic trioxide.an integrated intensity of an arsenic element present as gallium arsenide and an integrated intensity of an arsenic element present as metallarsene, and wherein R2 and / or R3 and / or R4 is the largest among R1, R2, R3, R4, R5 and R6.

The invention provides a solar cell and a manufacturing method thereof. The solar cell comprises a substrate; the epitaxial structure is arranged on the surface of one side of the substrate; the ohmic contact layer is arranged on the surface, deviating from the substrate, of the epitaxial structure; the grid line electrode is in contact with the ohmic contact layer; the back electrode is arranged on the surface of one side, deviating from the epitaxial structure, of the substrate; wherein the ohmic contact layer comprises a composite stacked structure formed by a phosphide layer and an arsenide layer. Through the arrangement, the conduction band bottom of the phosphide layer is higher than the arsenide layer, and an electron barrier (delta Ec) is formed at the interface of the phosphide layer and the arsenide layer; heavy doping is carried out on the ohmic contact layer, so that a Schottky barrier between the grid line electrode and the phosphide layer and a heterojunction barrier (delta Ec) between the phosphide layer and the arsenide layer become thin barriers capable of being tunneled by electrons due to narrowing of a depletion region, and overall low-resistance ohmic contact is achieved.

This application belongs to the field of saturable absorber technology, and particularly relates to a saturable absorber based on tantalum arsenide quantum dots, its preparation method, and a mode-locked fiber laser. The saturable absorber provided by this application includes a tapered optical fiber and tantalum arsenide quantum dots loaded thereon. The tantalum arsenide quantum dots have excellent nonlinear optical properties and saturation intensity, so when the laser passes through the tantalum arsenide quantum dots on the saturable absorber, the laser reaches saturation quickly, enabling the output of ultrafast laser with a repetition frequency and stable laser mode-locked signal, thereby solving the technical problem of low performance of saturable absorbers based on two-dimensional materials in the prior art.

A process for producing semiconductor structures comprising one of more layers of Group III / IV Compounds deposited onto a template using PVD sputtering the resulting semiconductor structures is provided according to the invention. The Group III or Group IV material may be gallium, hafnium, indium, aluminum, silicon, germanium, magnesium and / or zirconium. The anion provided by a reactive gas may be nitride, oxide, arsenide, or phosphide. The flow of the reactive gas to the vacuum chamber used to react with the sputtered Group III or Group IV target material for produce the Group III / IV Compound layer onto the template is modulated during a duty cycle during the PVD sputtering process between a target-rich condition and a reactive gas-rich condition to enhance the efficiency of the PVD sputtering process and improve the crystallinity of the Group III / IV Compound layer within the resulting semiconductor structure.

According to the present invention there is provided use of a lead electrode in a method for removing one or more impurities from a copper refinery electrolyte. Preferably, the method is a single-stage electrolyte purification / liberation (EPP) method. More preferably, the one or more impurities comprise arsenic. Also provided is a lead cathode, per se, for use in such a method. Preferably, the method comprises the steps of: providing an electrolyte having a concentration of arsenic that is sufficiently elevated as to affect the purity of the final copper cathode product; providing a cell adapted for performing a single- stage electrolyte purification / liberation (EPP) method; providing to the EPP cell a cathode comprised of about 90 to about 100 wt.% lead; performing the EPP method for a predetermined period, thereby to effect a copper / arsenic reduction step; and obtaining the resultant cupric arsenide deposit in a sludge layer at the bottom of the EPP cell.

The invention discloses a process method for deeply removing copper from crude lead by using dangerous solid wastes, and belongs to the technical field of non-ferrous metal metallurgy and resource utilization of the dangerous solid wastes. Dangerous solid waste containing arsenic and sulfur serves as a copper removal agent and is added into molten lead bullion, stirring and smelting are conducted at the temperature of 450-900 DEG C, copper reacts with arsenic and sulfur to generate cuprous sulfide, copper arsenide and other compounds insoluble in lead liquid by means of the preferential affinity of arsenic and sulfur to copper, the compounds float upwards to form a low-density arsenic matte scum layer, and efficient separation of copper is achieved through mechanical slag scattering. The copper content in the lead liquid after copper removal can be reduced to 0.1% or below, and meanwhile harmless treatment of dangerous solid waste and resource recycling of valuable elements are achieved. The method is simple in process, low in cost and high in copper removal efficiency, and has remarkable environmental benefits and economic benefits.

The invention relates to a micro-LED comprising a semiconductor layer stack with a first layer of a first doping type, a second layer of a second doping type, and an active region arranged between the first and second layers. The semiconductor layer stack comprises a bottom and a top surface, as well as mesa-structured side surfaces connecting the top and bottom surfaces, and a central region with a lateral dimension that is less than half a lateral dimension of the semiconductor layer stack. Furthermore, the semiconductor layer stack comprises a material comprising at least one phosphide and one arsenide, and a current path from the first layer to the second layer through the active region is confined to the central region.

A nanopore sensing system includes a cis well, a trans well, and a metal based membrane positioned between the cis and trans wells so that a channel defined in the metal based membrane fluidically connects the cis and trans wells. The metal based membrane has a thickness ranging from about 1 nm to about 3 nm and is selected from the group consisting of a metal oxide, a metal sulfide, a metal nitride, a metal phosphide, a metal arsenide, a metal antimonide, a metal selenide, and a metal telluride.

The invention discloses a low-cost reverse matching two-junction GaInP / GaAs solar cell and a preparation method thereof, the outer edge structure of the solar cell comprises a gallium arsenide substrate, and three GaAs buffer layers, three GaInP barrier layers, three GaAs cap layers, three AlGaInP top cells, a first tunneling junction, three GaAs bottom cells and three AlGaAs cap layers which are arranged on the gallium arsenide substrate, the three GaAs buffer layers, the three GaInP barrier layers, the three GaAs cap layers, the three AlGaInP top cells, the three GaAs bottom cells and the three AlGaAs cap layers are all middle layers, and the growth rate of the middle layers is larger than that of the upper layers and the lower layers of the three GaAs buffer layers, the three GaInP barrier layers, the three GaAs cap layers, the three AlGaInP top cells and the three GaAs bottom cells. The growth mode of the epitaxial structure adopts a slow-fast-slow gradual-change growth mode with different rates, so that a buffer material has a lower reverse domain, layered growth of an arsenic or phosphorus compound material is realized, interface defects of an arsenide material and a phosphide material at an interface or a steep interface can be overcome, efficient growth of an epitaxial material is met, and the performance of the epitaxial structure is improved. The epitaxial growth time is reduced, and the growth time cost is reduced.

A method of extracting a metal of interest comprises dissolving an oxidizable metal compound in an electrolyte contained in an electrochemical cell; dissolving a sulfoarsenide compound comprising the metal of interest in the electrolyte; applying a current between an anode and a cathode of the electrochemical cell to produce an electrochemical product solution comprising soluble metal ions of the oxidizable metal compound, soluble metal ions of the metal of interest, and a soluble arsenic acid; reacting the soluble arsenic acid with the metal ions of the oxidizable metal compound to form an insoluble arsenate compound comprising the metal of the oxidizable metal compound; and separating the soluble metal ions of the metal of interest from the insoluble arsenate compound. Also disclosed is a method of extracting a metal of interest from a metal containing feed stream, and a method of isolating cobalt from a metal containing feed stream.